technology advancements in design...
TRANSCRIPT
Technology Advancements in Design Implementation
2 © 2017 Cadence Design Systems, Inc. All rights reserved.
Innovus Customer Growth
Mar 2015 Jun 2017
• 2 years on, rapid adoption growth, especially at advanced node
3 © 2017 Cadence Design Systems, Inc. All rights reserved.
Technology Leadership Leads to Market AdoptionProgress over last 12 months
Innovus™ SystemDramatic Market
Share Gains
Genus™ Synthesis>100 customers
Tempus™ TimingOver 250 Tapeouts
Voltus™ PowerTrue Signoff Accuracy
for 1B+ Cells
Preferred Solution for
CPUs and GPUs
Market Leadership
at Advanced Nodes
16 out of Top 20 Semi Companies Use
Cadence® Digital NowSource: IC Insights Q4’16
4 © 2017 Cadence Design Systems, Inc. All rights reserved.
Innovus Implementation of 5M+ Instance SoCTargeting GHz performance
• Design challenges– Placeable instances: 5M top + 10M blocks
– Flip chip, 28nm FDSOI with FBB and without FBB regions
– Large increase in corners with modes
– Average operating frequency of 1GHz+
– Multiple ON/OFF power domains
– Top-level channel-based design
• Innovus Technology
GigaPlace™ tool Good initial placement, critical logic timing improved, leakage recovery 18%,
30% runtime reduction over previous release with better QoR
CTS High effort CCOpt™ with routing enabled,
improved inverter count by 20% in clock tree
Routing Timing-driven track assignment during globalroute,
RouteDesign with inRouteOpt – better QoR, wire spreading
Hold fixing Hold Fix without impacting setup degradation at post route by forcing thin
inverters, multiple views handled for Setup and Hold concurrently
Differentiated technology for achieving best QoR on large flat and hierarchical designs
5 © 2017 Cadence Design Systems, Inc. All rights reserved.
Innovus Hierarchical Flow for Thin Channel-Based Design Planning and implementation
• Design complexity and challenges– 50M instances / 10nm process
– Many power domains / multiple scenarios (DVFS)
– Multiple IPs / partitions multi-million instance count
– Flip chip package
– Critical interfaces (DDR, USB, MSDC)
– Tight design schedule: 8-10 weeks
• Innovus – Hierarchical design planning flow– Flexmodel and ShellModel abstraction technology
– Placement and route-based feedthrough insertion
– Guided automated pin assignment
– Time budgeting with complex SDC in Tcl
Runtime achieved: 50M instances: 6hrs (16cpus)
Successful flow execution and tapeout using thin channel-based design planning
6 © 2017 Cadence Design Systems, Inc. All rights reserved.
Innovus 17.1 – Innovation Continues
Faster and Smarter
GigaPlace Technology Update
New GigaOpt™ Power Optimization Flow
Distributed Computing
Latest Advanced-Node Support
Machine Learning, and the Smart Future
IMPLEMENTATION
SMART FLOWS
FAST ENGINES
ELECTRICAL
SIGNOFF
PLACE and
ROUTESYNTHESIS
PHYSICAL
SIGNOFF
7 © 2017 Cadence Design Systems, Inc. All rights reserved.
Improved congestion monitoring
Layer-wise congestion report
Pin-density-based optimized placement
Accurate “congestion-driven” placement
• Seamless Voltus™ integration for dynamic power and IR
• “setPlaceMode –place_detail_irdrop_aware_effort” options
• Preserve route option available for postRoute DB
Enhanced IR Drop placement
• Previously a requirement in 10/7nm designs
• Turned on by default for 16/14nm
• Improved runtime
Full geometry checker enabled for 16nm/14nm
GigaPlace Tool: Improved PPA and Convergence
Significant algorithm improvements and new features for better convergence and PPA
Design
Place_Opt
TNS_16.2
Place_Opt
TNS_17.1
A_800K -345.18 -36.3
B_1.6M -305.47 -210.18
IR-drop violations max voltage drop (mv)Before After Gain Before After Gain
Case A 6958 2682 61.45% 144.102 106.048 26.41%Case B 123 1 99.19% 117.592 36.032 69.36%Case C 2360 1922 18.56% 76.913 76.864 3.94%
Case A before IR-drop refine Case A after IR-drop refine
8 © 2017 Cadence Design Systems, Inc. All rights reserved.
• Clean interface for defining views• set_analysis_view -setup/hold/leakage/dynamic
• Improved timer performance, full-flow control of powerEffort
Improved power view definition
Separate weighting used for placements
Default when vectors are provided
Secondary benefits of improved wirelength/congestion with power
Activity-driven placement
Avoids loss of activity information due to different flop naming
Activity information preserved for decision on split/merge
Multi-bit FF merge/split (activity based)
Innovus 17.1 - Power Optimization Improvements
Low
EffortLeakage
Recovery
Activity
Driven
Placement
Clock
Skewing For
Power
Full Power
Aware
Optimization
Dynamic
Recovery
Clock Power
Focused
ICG
Placement
High Effort
F
F
F
F
FI
C
GF
F
F
F
FI
C
G
F
F
F
F
FI
C
G
F F
F
F
F
I
C
G
F
F
F
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FI
C
G
F
F
F
F
FI
C
G
F
F
F
F
FI
C
G
F
F
F
F
FI
C
G
9 © 2017 Cadence Design Systems, Inc. All rights reserved.
GPU Tapeout with Innovus Solution—Exceptional PPA Improvements and Shorter Schedule
• Innovus deployed for production on GPU and Tegra on
FinFET technologies(16FF)
• Advanced node GPU tapeout completed ahead of schedule
with Innovus solution—over 30 blocks taped-out
Tapeout schedule cut by three weeks due to better timing convergence.”
– NVIDIA
“Innovus provided one of the best starting points for march to tapeout.”
– NVIDIA
Average of 7% improvement in total design power
10 © 2017 Cadence Design Systems, Inc. All rights reserved.
Distributed Computing
11 © 2017 Cadence Design Systems, Inc. All rights reserved.
Massively Parallel Full Flow
TempusSignoff STA
VoltusSignoff IR
InnovusImplementation System
GenusRTL Synthesis
Machine N
…
CPU-M
CPU-1…
Massively
ParallelMachine 1 CPU-M
CPU-1…
Distributed +
Multi-Thread
Distributed Multi-Thread
5X faster, runs
6M+ cell blocks
Mobile SoC timing
ECO in 12hrs
500M-cell SoC
signoff in 24hrs
Guaranteed same
signoff result for any
CPU configuration
GigaPlace
GigaOpt(pre-cts)
CCOpt
NanoRoute™
Inn
ovu
s
Distributed Multi-Thread
Distributed optimization
• Breakthrough technology
• 10s of CPUs → 100s of CPUs
• Faster TAT and better PPA
GigaOpt(post-route)
12 © 2017 Cadence Design Systems, Inc. All rights reserved.
Innovus Distributed Processing
Removing limitations of multi-thread
Auto Partition by Timing Density Map
▪ Transparent to user
▪ Avoid cut through hotspot
▪ Full-flow distributed GigaOpt
Distribute
CPU1 CPU2 CPU<n>
Timing-graph partition technology
Multi-Thread Su
per
Th
read
Design1: 7nm, 5.7Mil instances
0:00:00
24:00:00
48:00:00
72:00:00
96:00:00
Flat (8CPU) Dist Flow (16+1*16)
Flat vs Dist Flow
place place_opt ccopt route PR
Design2: 7nm, 3Mil instances, 4 setup views
1.5X
QOR
Flat (8CPU)
WNS/TNS/Density
Dist opt (16+16)
WNS/TNS/Density
Post Route -32ps/-1ns/52.2% -26ps/-3ns/52.1%
BETA Access
2x Faster TAT
TAT: -1.4x
Pwr: -8%
TAT: -1.5x
Pwr: -10%
“This slide contains forward-looking statements regarding Cadence's business or products. Actual results may differ materially from the information presented here.”
13 © 2017 Cadence Design Systems, Inc. All rights reserved.
Advanced-Node Digital Implementation
14 © 2017 Cadence Design Systems, Inc. All rights reserved.
Advanced-Node Digital Implementation Flow
• Complete 7nm digital implementation flow production ready
– Complex placement alignment rules
– Via pillar support for high performance
– Metal trim layer optimized routing
– SOCV timing analysis for accuracy
– Statistical EM rule checking and correction
– Self-heating effects analysis for reliability
• Signoff 7nm accuracy used for final design closure to remove pessimism
– Tempus solution for timing and power
– Voltus solution for IR and EM
• 7nm-ready full-flow engines enable exceptional design convergence
GenusSynthesis
Joules™
RTL Power Analysis
InnovusImplementation
Quantus™
Extraction
VoltusPower
TempusTiming
Wire1
TR
IM Wire2 Wire3
TR
IM
Dera
te
Path depth
Ideal derate
OCV derate
AOCV derate
SOCV derate
VIA Pillar
Metal Trim Shapes
SOCV Analysis
15 © 2017 Cadence Design Systems, Inc. All rights reserved.
TSMC Advanced-Node Certification
TSMC Certifies Cadence Innovus Implementation System on 16-nanometer FinFET Plus Process
TSMC and Cadence are actively collaborating to certify the Innovus Implementation System on the TSMC
10nm FinFET process
SAN JOSE, Calif., 08 Jun 2015
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® Innovus™
Implementation System has achieved v1.0 Design Rule Manual (DRM) certification from TSMC for its 16-
nanometer FinFET Plus (16FF+) process. The Innovus Implementation System successfully passed
rigorous testing and has
Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET
Process
Cadence tools validated by TSMC on high-performance reference designs in order to enable customers to
reduce iterations and improve predictability
Cadence and TSMC collaborate on delivering new capabilities for 10nm custom design reference flow
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, custom/analog and signoff
tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve
V1.0 completion by Q4 2015. The certification enables systems and semiconductor companies to deliver
advanced-node designs to market faster for mobile phones, tablets, application processors and high-end
servers.
TSMC Certifies Cadence Innovus Implementation System on 10nm FinFET Process
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its Cadence® Innovus™
Implementation System has achieved V0.9 certification for TSMC’s 10nm FinFET process and is currently on
track to complete V1.0 in Q4 2015. The Innovus Implementation System is a next-generation physical
implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-
performance reference designs, providing customers with a fast path to implementation, closure, and optimal
power, performance and area (PPA).
Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
Cadence tools and PDK enabled based on the latest 7nm DRM and SPICE for early customers
Cadence and TSMC collaborate on delivering new capabilities for 10nm digital, custom, and mixed-signal
reference flowsCadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several important deliveries in its collaboration with
TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms.
TSMC and Cadence have collaborated on an integrated flow based on tool certification targeting TSMC’s 7nm mobile and
HPC platforms. The integrated flow ensures that the certified tools work seamlessly when used
Cadence Achieves Certification for TSMC’s 7nm Process Technology
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several new capabilities resulting from
its close collaboration with TSMC to further 7nm FinFET design innovation for mobile and high-performance
computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved
certification for v1.0 Design Rule Manual (DRM) and SPICE certification for the TSMC 7nm process.
TSMC N20 N16 N10 N7
INNOVUS
16 © 2017 Cadence Design Systems, Inc. All rights reserved.
Intel Custom Foundry Certifies Cadence Implementation and Signoff Tools for 10nm Tri-Gate Process
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its implementation and signoff tools
have achieved certification on the Intel® third-generation 10nm tri-gate process for customers of Intel
Custom Foundry. Intel Custom Foundry utilized a PowerVR GT7200 graphics processing unit (GPU) from
Imagination Technologies as part of the certification process
Additional Advanced-Node Foundry Certifications
Cadence Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 22FDX Platform Reference Flow
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital and signoff tools are now
enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow.
GLOBALFOUNDRIES has qualified these tools for the 22FDX reference flow to provide customers with the
design flexibility of software-controlled body bias to manage power, performance and leakage needed to
create next-generation chips for mainstream mobile, Internet of Things (IoT) and consumer applications. In
addition, the ARM® Cortex®-A17 processor was used to validate the implementation flow with the Cadence®
Innovus™ Implementation System and Genus™ Synthesis Solution.
GLOBALFOUNDRIES Solidifies 14nm FinFET Design Infrastructure for Next-Generation Chip Designs
In collaboration with design ecosystem partners, GLOBALFOUNDRIES provides digital design flows for
customers designing on leading-edge technologyCadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES
7LP Process Node
Reference flow available for early customer engagement
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow
digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance
(7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40 percent better
performance and twice the area scaling than the previous 14nm FinFET technology.
Cadence Digital and Signoff Tools Certified on Samsung Foundry’s 14LPP Process
Reference flow enables system and semiconductor companies to accelerate delivery of 14nm
FinFET design
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its complete suite of digital and
signoff tools has achieved certification for Samsung Foundry’s Process Design Kit (PDK) and foundation
library for the 14LPP process.
Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process
Technologies
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and
custom/analog tools are enabled on Samsung Electronics’ 7LPP and 8LPP process technologies. The
7LPP and 8LPP process technologies continue to deliver power, performance and area optimizations with
additional scaling benefits over previous generations of advanced FinFET nodes, and customers can begin
working on early designs using these next-generation technologies.
17 © 2017 Cadence Design Systems, Inc. All rights reserved.
Full-Flow 7nm Customer ExampleTestchip tapeouts and production deployment
Testchips Phase 1
• Goal: Flow flush, check Innovus compliance of new process requirements
• 1st testchip tapeout for Oct Shuttle
• 2nd testchip with memories and library updates
• High-performance CPU core
Testchips Phase 2
• Goal: Test technology port from 10nm on a large mobile SoC
• GPU and 5 SoC blocks – with varying complexity
• 3 peripheral IP blocks - congested designs
CPU PPA Push
• Next-generation high-performance CPU core implementation with frequency target
• Next-generation high-efficiency CPU core implementation with power reduction goal
• Innovus solution achieved 7% above set frequency target and 5% power improvement
Next: High-end production multi-core implementation with full-flow including signoff
Design Creation
Implementation
InnovusImplementation
GenusSynthesis
Leading Edge
Mobile Designs
Test chips
Tapeouts
Tempus/
Voltus
Timing and
Power Signoff
18 © 2017 Cadence Design Systems, Inc. All rights reserved.
Customer Migrating from 10nm to 7nmDatacenter, networking, and mobile designs
7nm Tapeout #1 7nm Tapeout #2 7nm Tapeouts
October 2016 2017
• Hierarchical testchip
• Excellent correlation
Innovus vs Signoff DRC
• Signoff-level DRC clean
• High-performance library
• Competition could not route
congested block
• Innovus trial shows full routability
• Innovus CTS showed 10-15%
improvement over competition
• High-performance Genus-
Innovus CPU core
• 4 production tapeouts
• Voltus solution used for
power/IR signoff
• Timing/power signoff trials
Successful testchip tapeouts—Customer moving to multiple 7nm production using full Cadence Full-Flow
Design Creation
InnovusImplementation
GenusSynthesis
Tempus/
Voltus
Timing and
Power Signoff
Implementation
19 © 2017 Cadence Design Systems, Inc. All rights reserved.
What Next? Smart Implementation with Machine Learning
InnovusMachine Learning
InnovusDefault
MetricMachine
LearningDefault
TNS (ns) -225.2 -256.2
12% PPA (TNS) Improvement
10nm design
Design
(Netlist, SDC)
Design
Guidance
Machine Learning
Training Set
(Large Design
Data Cache)
Model Actual
Machine
Learning
Design
data
extraction
This slide contains forward-looking statements regarding Cadence's business or products. Actual results may differ materially from the information presented here
20 © 2017 Cadence Design Systems, Inc. All rights reserved.
Virtuoso
Platform
Innovus
Genus
Tempus
Quantus
Voltus
Full-Flow Mixed-Signal 7nm Design and Signoff
Unified design database
OpenAccess
MS FloorplanningBetter Area
Effective MS ECOTAT
Full Timing ModelBetter QoR
Constraints PassingProductivity
No need to create any timing models for analog,
no data translation/re-characterization
Automatically identifies digital logic in the design,
deep in the physical hierarchy
MS STA improved from weeks to daysComplete 7nm OpenAccess-based mixed-signal solution
7nm Rules Support
7nm Trim
Metal
21 © 2017 Cadence Design Systems, Inc. All rights reserved.
Driving Innovation, Delivering Best-in-Class Technology
Fast: 10M+ instance capacity
• Multi-CPU and multi-machine distributed architecture
• Core engines for all tools threaded and distributed
• Enables scalability for enormous advanced-node designs
Smart: Convergent physical optimization
• Concurrent power, performance, and area (PPA) optimization
• Physically aware across whole flow for advanced-node
convergence and rules support
• Each stage of the flow feeds information forward for optimal
correlation and better predictability
De
sig
n
Imp
lem
en
tati
on
InnovusImplementation System
Stratus™
High Level Synthesis
GenusRTL Synthesis
Conformal®
LEC, ECO, LP
Modus™
Test SolutionJoules™
RTL Power
Pegasus™
DRC, LVS, DFM
Tempus™Signoff STA
Quantus™Signoff Extraction
VoltusSignoff Power
TempusSignoff STA
Quantus™
Signoff Extraction
Sig
no
ffD
es
ign
Cre
ati
on
Full-Flow: Unified engines across flow
• Shared placement, routing, extraction, and delay calculation
• Stylus common user environment
• Integrated in-design signoff solutions
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.