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TMS320F2807x Piccolo Microcontrollers

Technical Reference Manual

Literature Number: SPRUHM9October 2014

Contents

Preface....................................................................................................................................... 711 C28x Processor.................................................................................................................. 72

1.1 Overview..................................................................................................................... 731.1.1 Floating-Point Unit ................................................................................................ 731.1.2 Trigonometric Math Unit ......................................................................................... 731.1.3 Viterbi, Complex Math, and CRC Unit II (VCU-II) ............................................................ 74

2 System Control .................................................................................................................. 752.1 Introduction.................................................................................................................. 762.2 System Control Functional Description.................................................................................. 76

2.2.1 Device Identification .............................................................................................. 762.2.2 Device Configuration Registers ................................................................................. 76

2.3 Resets ....................................................................................................................... 762.3.1 Reset Sources ..................................................................................................... 762.3.2 External Reset (XRS) ............................................................................................. 772.3.3 Power-On Reset (POR) .......................................................................................... 772.3.4 Debugger Reset (SYSRS) ....................................................................................... 772.3.5 Watchdog Reset (WDRS) ........................................................................................ 782.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 782.3.7 DCSM Safe Code Copy Reset (SCCRESET) ................................................................. 782.3.8 Hibernate Reset (HIBRESET) ................................................................................... 782.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 782.3.10 Test Reset (TRST) ............................................................................................... 78

2.4 Peripheral Interrupts ....................................................................................................... 792.4.1 Interrupt Concepts................................................................................................. 792.4.2 Interrupt Architecture.............................................................................................. 792.4.3 Interrupt Entry Sequence......................................................................................... 802.4.4 Configuring and Using Interrupts................................................................................ 812.4.5 PIE Channel Mapping ............................................................................................ 832.4.6 Vector Tables ...................................................................................................... 84

2.5 Exceptions and Non-Maskable Interrupts ............................................................................... 902.5.1 Configuring and Using NMIs ..................................................................................... 902.5.2 Emulation Considerations ........................................................................................ 902.5.3 NMI Sources ....................................................................................................... 912.5.4 Illegal Instruction Trap (ITRAP).................................................................................. 91

2.6 Safety Features............................................................................................................. 912.6.1 Write Protection on Registers.................................................................................... 912.6.2 Missing Clock Detection Logic................................................................................... 922.6.3 PLLSLIP Detection ................................................................................................ 932.6.4 CPU1 Vector Address Validity Check .......................................................................... 932.6.5 NMIWDs ............................................................................................................ 942.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection .................................................. 942.6.7 ECC Enabled Flash Memory .................................................................................... 942.6.8 Error Pin ............................................................................................................ 94

2.7 Clocking ..................................................................................................................... 952.7.1 Clock Sources ..................................................................................................... 95

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2.7.2 Derived Clocks..................................................................................................... 972.7.3 Device Clock Domains............................................................................................ 982.7.4 XCLKOUT .......................................................................................................... 992.7.5 Clock Connectivity................................................................................................. 992.7.6 Clock Source and PLL Setup .................................................................................. 101

2.8 32-Bit CPU Timers 0/1/2 ................................................................................................. 1042.9 Watchdog Timers ......................................................................................................... 105

2.9.1 Servicing the Watchdog Timer ................................................................................. 1052.9.2 Minimum Window Check ....................................................................................... 1062.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 1062.9.4 Watchdog Operation in Low Power Modes .................................................................. 1072.9.5 Emulation Considerations ...................................................................................... 107

2.10 Low Power Modes ........................................................................................................ 1082.10.1 IDLE .............................................................................................................. 1082.10.2 STANDBY ....................................................................................................... 1082.10.3 HALT ............................................................................................................. 1082.10.4 HIB................................................................................................................ 109

2.11 Memory Controller Module .............................................................................................. 1102.11.1 Functional Description ......................................................................................... 110

2.12 Flash and OTP Memory ................................................................................................. 1182.12.1 Features.......................................................................................................... 1182.12.2 Flash Tools ...................................................................................................... 1182.12.3 Default Flash Configuration ................................................................................... 1192.12.4 Flash Bank, OTP and Pump .................................................................................. 1192.12.5 Flash Module Controller (FMC) ............................................................................... 1192.12.6 Flash and OTP Automatic Power-Down Modes ............................................................ 1202.12.7 Flash and OTP Performance.................................................................................. 1212.12.8 Flash Read Interface ........................................................................................... 1212.12.9 Erase/Program Flash........................................................................................... 1242.12.10 Error Correction Code (ECC) Protection ................................................................... 1252.12.11 Reserved Locations Within Flash and OTP ............................................................... 1292.12.12 Procedure to Change the Flash Control Registers ....................................................... 129

2.13 Dual Code Security Module (DCSM)................................................................................... 1302.13.1 Functional Description ......................................................................................... 1302.13.2 CSM Impact on Other On-Chip Resources ................................................................. 1362.13.3 Incorporating Code Security in User Applications .......................................................... 137

2.14 Registers ................................................................................................................... 1422.14.1 Base Addresses ................................................................................................ 1422.14.2 CPUTIMER_REGS Registers................................................................................. 1432.14.3 PIE_CTRL_REGS Registers .................................................................................. 1502.14.4 WD_REGS Registers .......................................................................................... 1772.14.5 NMI_INTRUPT_REGS Registers............................................................................. 1832.14.6 XINT_REGS Registers......................................................................................... 1942.14.7 DMA_CLA_SRC_SEL_REGS Registers .................................................................... 2032.14.8 DEV_CFG_REGS Registers .................................................................................. 2102.14.9 CLK_CFG_REGS Registers .................................................................................. 2552.14.10 CPU_SYS_REGS Registers................................................................................. 2762.14.11 ROM_PREFETCH_REGS Registers ....................................................................... 3092.14.12 DCSM_Z1_OTP Registers ................................................................................... 3112.14.13 DCSM_Z2_OTP Registers ................................................................................... 3182.14.14 DCSM_Z1_REGS Registers................................................................................. 3252.14.15 DCSM_Z2_REGS Registers................................................................................. 3452.14.16 DCSM_COMMON_REGS Registers ....................................................................... 365

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2.14.17 MEM_CFG_REGS Registers ................................................................................ 3722.14.18 ACCESS_PROTECTION_REGS Registers ............................................................... 4152.14.19 MEMORY_ERROR_REGS Registers ...................................................................... 4342.14.20 ROM_WAIT_STATE_REGS Registers..................................................................... 4512.14.21 FLASH_CTRL_REGS Registers ............................................................................ 4532.14.22 FLASH_ECC_REGS Registers ............................................................................. 465

3 ROM Code and Peripheral Booting ..................................................................................... 4873.1 Introduction ................................................................................................................ 4883.2 Device Boot Philosophy.................................................................................................. 4883.3 Device Clocking on Power-up and Boot Time ........................................................................ 4883.4 Clock Configurations in Boot ROM ..................................................................................... 488

3.4.1 CPU1 Boot ROM Clocking Configuration..................................................................... 4883.5 Faster Flash Power Up................................................................................................... 4893.6 Boot ROM DCSM init Sequence........................................................................................ 489

3.6.1 CPU1 DCSM init Sequence .................................................................................... 4893.6.2 DCSM init Sequence ............................................................................................ 489

3.7 Device Calibration ........................................................................................................ 4903.8 CPU1 Boot ROM Procedure ............................................................................................ 4903.9 Boot Modes Supported on CPU1....................................................................................... 4913.10 CPU1 Boot ROM Flow Chart ........................................................................................... 4963.11 Boot ROM Reset Causes and Handling ............................................................................... 4983.12 Exceptions and Interrupts handling..................................................................................... 4993.13 CPU1 OTP Boot Configure Word....................................................................................... 4993.14 Boot ROM Status information ........................................................................................... 500

3.14.1 Boot ROM Health and Status ................................................................................. 5003.14.2 CPU1 Boot ROM IPC NAK Status ........................................................................... 500

3.15 Device Boot Process Timeline Diagram ............................................................................... 5013.16 Boot ROM GPIO Configurations: ....................................................................................... 5013.17 Boot ROM Memory Map ................................................................................................ 5023.18 CPU1 ROM REVISION Information .................................................................................... 5033.19 RAM and Flash Usage and Application Entry Points ................................................................ 503

3.19.1 Reserved RAM Memory for Boot ROM ..................................................................... 5043.19.2 CPU1 RAM Entry Point ........................................................................................ 5043.19.3 CPU1 Flash Entry Point........................................................................................ 5043.19.4 CPU1Flash Reserved Memory ............................................................................... 504

3.20 ROM Wait States ......................................................................................................... 5043.21 Device Boot Modes Description ........................................................................................ 505

3.21.1 Boot Data Stream Structure .................................................................................. 5053.21.2 Basic Data Transfer Procedure ............................................................................... 5093.21.3 CopyData Function ............................................................................................. 5113.21.4 SCI Boot Mode.................................................................................................. 5123.21.5 SPI Boot Mode .................................................................................................. 5153.21.6 I2C Boot Mode .................................................................................................. 5183.21.7 Parallel Boot Mode ............................................................................................ 5213.21.8 CAN Boot Mode................................................................................................. 5253.21.9 USB Boot Mode................................................................................................. 527

3.22 CLA Data ROM ........................................................................................................... 5283.22.1 CPU1CLA Data ROM .......................................................................................... 528

3.23 Secure ROM Contents ................................................................................................... 5303.23.1 CPU1.Secure ROM............................................................................................. 530

4 Direct Memory Access (DMA)............................................................................................. 5314.1 Introduction ................................................................................................................ 5324.2 Architecture ................................................................................................................ 533




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4.2.1 Block Diagram.................................................................................................... 5334.2.2 Common Peripheral Architecture .............................................................................. 5334.2.3 Peripheral Interrupt Event Trigger Sources .................................................................. 5344.2.4 DMA Bus .......................................................................................................... 540

4.3 Pipeline Timing and Throughput ........................................................................................ 5404.4 CPU Arbitration ........................................................................................................... 5414.5 Channel Priority ........................................................................................................... 542

4.5.1 Round-Robin Mode .............................................................................................. 5424.5.2 Channel 1 High Priority Mode .................................................................................. 542

4.6 Address Pointer and Transfer Control ................................................................................. 5434.7 Overrun Detection Feature .............................................................................................. 5474.8 Register Descriptions..................................................................................................... 549

4.8.1 DMA Control Register (DMACTRL) EALLOW Protected ............................................... 5504.8.2 Debug Control Register (DEBUGCTRL) EALLOW Protected.......................................... 5514.8.3 Revision Register (REVISION)................................................................................. 5514.8.4 Priority Control Register 1 (PRIORITYCTRL1) EALLOW Protected .................................. 5524.8.5 Priority Status Register (PRIORITYSTAT) ................................................................... 5534.8.6 Mode Register (MODE) EALLOW Protected ............................................................. 5544.8.7 Control Register (CONTROL) EALLOW Protected ...................................................... 5564.8.8 Burst Size Register (BURST_SIZE) EALLOW Protected ............................................... 5584.8.9 BURST_COUNT Register ...................................................................................... 5584.8.10 Source Burst Step Register Size (SRC_BURST_STEP) EALLOW Protected ...................... 5594.8.11 Destination Burst Step Register Size (DST_BURST_STEP) EALLOW Protected ................. 5604.8.12 Transfer Size Register (TRANSFER_SIZE) EALLOW Protected..................................... 5604.8.13 Transfer Count Register (TRANSFER_COUNT) .......................................................... 5614.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) EALLOW Protected............. 5614.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) EALLOW Protected ........ 5624.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) EALLOW protected) ......... 5624.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) ............................... 5634.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) EALLOW Protected . 5634.8.19 Shadow Source Begin and Current Address Pointer Registers

(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) All EALLOW Protected ............ 5644.8.20 Active Source Begin and Current Address Pointer Registers

(SRC_BEG_ADDR/DST_BEG_ADDR) ....................................................................... 5644.8.21 Shadow Destination Begin and Current Address Pointer Registers

(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) All EALLOW Protected .......................... 5654.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)....... 565

5 Control Law Accelerator (CLA) ........................................................................................... 5665.1 Control Law Accelerator (CLA) Overview ............................................................................. 5675.2 CLA Interface.............................................................................................................. 569

5.2.1 CLA Memory ..................................................................................................... 5695.2.2 CLA Memory Bus ................................................................................................ 5705.2.3 Shared Peripherals and EALLOW Protection ................................................................ 5705.2.4 CLA Tasks and Interrupt Vectors .............................................................................. 571

5.3 CLA Configuration and Debug .......................................................................................... 5745.3.1 Building a CLA Application ..................................................................................... 5745.3.2 Typical CLA Initialization Sequence ........................................................................... 5745.3.3 Debugging CLA Code ........................................................................................... 5765.3.4 CLA Illegal Opcode Behavior .................................................................................. 5775.3.5 Resetting the CLA ............................................................................................... 577

5.4 Pipeline..................................................................................................................... 5785.4.1 Pipeline Overview................................................................................................ 5785.4.2 CLA Pipeline Alignment ......................................................................................... 5785.4.3 Parallel Instructions.............................................................................................. 581




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5.5 Instruction Set ............................................................................................................. 5835.5.1 Instruction Descriptions ......................................................................................... 5835.5.2 Addressing Modes and Encoding.............................................................................. 5855.5.3 Instructions ....................................................................................................... 587

5.6 Registers ................................................................................................................... 6985.6.1 CLA Base Addresses............................................................................................ 6985.6.2 CLA_REGS Registers........................................................................................... 699

5.7 Appendix A: CLA and CPU Arbitration................................................................................. 7276 General-Purpose Input/Output (GPIO) ................................................................................. 728

6.1 GPIO Overview ........................................................................................................... 7296.2 Configuration Overview .................................................................................................. 7306.3 Digital General-Purpose I/O Control.................................................................................... 7306.4 Input Qualification......................................................................................................... 732

6.4.1 No Synchronization (Asynchronous Input) ................................................................... 7326.4.2 Synchronization to SYSCLKOUT Only........................................................................ 7326.4.3 Qualification Using a Sampling Window ...................................................................... 732

6.5 USB Signals ............................................................................................................... 7356.6 SPI Signals ................................................................................................................ 7356.7 GPIO and Peripheral Muxing............................................................................................ 7366.8 Internal Pullup Configuration Requirements........................................................................... 7376.9 Output X-BAR ............................................................................................................. 739

6.9.1 Output X-BAR Architecture ..................................................................................... 7406.10 Input X-BAR ............................................................................................................... 7416.11 Registers ................................................................................................................... 743

6.11.1 GPIO Base Addresses ......................................................................................... 7436.11.2 INPUT_XBAR_REGS Registers .............................................................................. 7446.11.3 OUTPUT_XBAR_REGS Registers ........................................................................... 7826.11.4 GPIO_CTRL_REGS Registers................................................................................ 8756.11.5 GPIO_DATA_REGS Registers .............................................................................. 1014

7 Analog Subsystem .......................................................................................................... 10637.1 Analog Subsystem ...................................................................................................... 1064

7.1.1 Features ........................................................................................................ 10647.1.2 Block Diagram .................................................................................................. 10647.1.3 Lock Registers .................................................................................................. 1066

7.2 Registers ................................................................................................................. 10677.2.1 Analog Subsystem Base Addresses......................................................................... 10677.2.2 ANALOG_SUBSYS_REGS Registers....................................................................... 1068

8 Analog-to-Digital Converter (ADC)..................................................................................... 10768.1 Analog-to-Digital Converter (ADC) .................................................................................... 1077

8.1.1 Features ......................................................................................................... 10778.1.2 ADC Block Diagram............................................................................................ 10778.1.3 ADC Configurability ............................................................................................ 10788.1.4 SOC Principle of Operation ................................................................................... 10818.1.5 SOC Configuration Examples ................................................................................ 10848.1.6 ADC Conversion Priority ...................................................................................... 10868.1.7 Burst Mode ...................................................................................................... 10898.1.8 EOC and Interrupt Operation ................................................................................. 10918.1.9 Post-Processing Blocks ....................................................................................... 10918.1.10 Power-Up Sequence.......................................................................................... 10948.1.11 ADC Calibration ............................................................................................... 1094

8.2 ADC Timings ............................................................................................................. 10958.2.1 ADC Timing Diagrams ......................................................................................... 1095

8.3 Additional Information................................................................................................... 10986 Contents SPRUHM9October 2014

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8.3.1 Choosing an Acquisition Window Duration ................................................................. 10988.3.2 Achieving Simultaneous Sampling ........................................................................... 10988.3.3 Designing an External Reference Circuit.................................................................... 10998.3.4 Internal Temperature Sensor ................................................................................. 1099

8.4 Registers ................................................................................................................. 11008.4.1 ADC Base Addresses.......................................................................................... 11008.4.2 ADC_REGS Registers......................................................................................... 11018.4.3 ADC_RESULT_REGS Registers............................................................................. 1230

9 Buffered Digital to Analog Converter (DAC) ....................................................................... 12519.1 Buffered Digital to Analog Converter (DAC) Overview ............................................................. 1252

9.1.1 Features ......................................................................................................... 12529.1.2 Block Diagram .................................................................................................. 1252

9.2 Using the DAC ........................................................................................................... 12529.3 Lock Registers ........................................................................................................... 12539.4 Registers ................................................................................................................. 1253

9.4.1 DAC Base Addresses.......................................................................................... 12539.4.2 DAC_REGS Registers......................................................................................... 1254

10 Comparator Subsystem (CMPSS)...................................................................................... 126210.1 CMPSS Overview ....................................................................................................... 1263

10.1.1 Features ........................................................................................................ 126310.1.2 Block Diagram ................................................................................................. 1263

10.2 Comparator............................................................................................................... 126410.3 Internal DAC ............................................................................................................. 126410.4 Ramp Generator......................................................................................................... 126510.5 Digital Filter .............................................................................................................. 126610.6 Registers ................................................................................................................. 1268

10.6.1 CMPSS Base Addresses..................................................................................... 126810.6.2 CMPSS_REGS Registers.................................................................................... 1269

11 Sigma Delta Filter Module (SDFM) ..................................................................................... 129211.1 SDFM Module Overview ............................................................................................... 1293

11.1.1 SDFM Features................................................................................................ 129311.1.2 Block Diagram ................................................................................................. 1293

11.2 Input Control Unit........................................................................................................ 129511.2.1 Manchester Decoding ........................................................................................ 1297

11.3 Comparator Unit ......................................................................................................... 129711.4 Data Filter Unit........................................................................................................... 1298

11.4.1 32-bit or 16-bit Data Filter Output Representation ........................................................ 130011.4.2 Data Rate and Latency of the Sinc Filter .................................................................. 1301

11.5 Interrupt Unit ............................................................................................................. 130211.6 Register Descriptions ................................................................................................... 130411.7 Registers ................................................................................................................. 1305

11.7.1 SDFM Base Addresses....................................................................................... 130511.7.2 SDFM_REGS Registers...................................................................................... 1306

12 Enhanced Pulse Width Modulator (ePWM) ......................................................................... 134212.1 Introduction............................................................................................................... 1343

12.1.1 Submodule Overview ......................................................................................... 134412.2 ePWM Submodules ..................................................................................................... 1349

12.2.1 Overview ....................................................................................................... 134912.2.2 Time-Base (TB) Submodule ................................................................................. 135112.2.3 Counter-Compare (CC) Submodule ........................................................................ 136212.2.4 Action-Qualifier (AQ) Submodule ........................................................................... 136812.2.5 Dead-Band Generator (DB) Submodule ................................................................... 1383




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12.2.6 PWM-Chopper (PC) Submodule ........................................................................... 138912.2.7 Trip-Zone (TZ) Submodule................................................................................... 139312.2.8 Event-Trigger (ET) Submodule .............................................................................. 139812.2.9 Digital Compare (DC) Submodule .......................................................................... 140412.2.10 EPWM X-BAR................................................................................................ 1411

12.3 Applications to Power Topologies..................................................................................... 141512.3.1 Overview of Multiple Modules .............................................................................. 141512.3.2 Key Configuration Capabilities .............................................................................. 141512.3.3 Controlling Multiple Buck Converters With Independent Frequencies ................................. 141612.3.4 Controlling Multiple Buck Converters With Same Frequencies ......................................... 141812.3.5 Controlling Multiple Half H-Bridge (HHB) Converters .................................................... 142012.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ....................................... 142212.3.7 Practical Applications Using Phase Control Between PWM Modules.................................. 142512.3.8 Controlling a 3-Phase Interleaved DC/DC Converter .................................................... 142612.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter .................................... 142912.3.10 Controlling a Peak Current Mode Controlled Buck Module ............................................ 143012.3.11 Controlling H-Bridge LLC Resonant Converter .......................................................... 1431

12.4 Registers ................................................................................................................. 143312.4.1 EPWM Base Addresses...................................................................................... 143312.4.2 EPWM_REGS Registers ..................................................................................... 143412.4.3 EPWM_XBAR_REGS Registers ............................................................................ 154212.4.4 TRIG_REGS Registers ....................................................................................... 1626

13 High-Resolution Pulse Width Modulator (HRPWM) .............................................................. 163313.1 Introduction............................................................................................................... 163413.2 Operational Description of HRPWM .................................................................................. 1636

13.2.1 Controlling the HRPWM Capabilities ....................................................................... 163613.2.2 Configuring the HRPWM ..................................................................................... 163913.2.3 Configuring Hi-Res in Deadband Rising Edge and Falling Edge Delay ............................... 164013.2.4 Principle of Operation......................................................................................... 164013.2.5 Deadband High Resolution Operation ..................................................................... 165013.2.6 Scale Factor Optimizing Software (SFO) .................................................................. 165113.2.7 HRPWM Examples Using Optimized Assembly Code. .................................................. 1651

13.3 Appendix A: SFO Library Software - SFO_TI_Build_V7.lib........................................................ 165713.3.1 Scale Factor Optimizer Function - int SFO() .............................................................. 165713.3.2 Software Usage ............................................................................................... 1658

14 Enhanced Capture (eCAP)................................................................................................ 166014.1 Introduction............................................................................................................... 166114.2 Description ............................................................................................................... 166114.3 Configuring Device Pins for the eCAP ............................................................................... 166114.4 Capture and APWM Operating Mode ................................................................................ 166214.5 Capture Mode Description ............................................................................................. 1663

14.5.1 Event Prescaler................................................................................................ 166414.5.2 Edge Polarity Select and Qualifier .......................................................................... 166514.5.3 Continuous/One-Shot Control ............................................................................... 166514.5.4 32-Bit Counter and Phase Control .......................................................................... 166614.5.5 CAP1-CAP4 Registers ....................................................................................... 166714.5.6 Interrupt Control ............................................................................................... 166714.5.7 Shadow Load and Lockout Control ......................................................................... 166814.5.8 APWM Mode Operation ...................................................................................... 1669

14.6 Application of the ECAP Module ..................................................................................... 167014.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger .................................... 167014.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ...................... 167314.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger .................................. 1675




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14.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger .................... 167714.7 Application of the APWM Mode ....................................................................................... 1679

14.7.1 Example 1 - Simple PWM Generation (Independent Channel/s) ....................................... 167914.8 Registers ................................................................................................................. 1681

14.8.1 eCAP Base Addresses ....................................................................................... 168114.8.2 ECAP_REGS Registers ...................................................................................... 1682

15 Enhanced QEP (eQEP)..................................................................................................... 169715.1 Introduction............................................................................................................... 169815.2 Description ............................................................................................................... 1700

15.2.1 EQEP Inputs ................................................................................................... 170015.2.2 Functional Description ........................................................................................ 170115.2.3 eQEP Memory Map ........................................................................................... 1702

15.3 Quadrature Decoder Unit (QDU) ...................................................................................... 170315.3.1 Position Counter Input Modes ............................................................................... 170315.3.2 eQEP Input Polarity Selection ............................................................................... 170615.3.3 Position-Compare Sync Output ............................................................................. 1706

15.4 Position Counter and Control Unit (PCCU) .......................................................................... 170615.4.1 Position Counter Operating Modes ......................................................................... 170615.4.2 Position Counter Latch ....................................................................................... 170915.4.3 Position Counter Initialization................................................................................ 171115.4.4 eQEP Position-compare Unit ................................................................................ 1711

15.5 eQEP Edge Capture Unit .............................................................................................. 171315.6 eQEP Watchdog......................................................................................................... 171615.7 Unit Timer Base ......................................................................................................... 171615.8 eQEP Interrupt Structure ............................................................................................... 171715.9 Registers ................................................................................................................. 1717

15.9.1 eQEP Base Addresses ....................................................................................... 171715.9.2 EQEP_REGS Registers ...................................................................................... 1718

16 Serial Peripheral Interface (SPI) ........................................................................................ 174716.1 SPI Module Overview................................................................................................... 174816.2 SPI Module Signal Summary .......................................................................................... 174916.3 Overview of SPI Module Registers ................................................................................... 175016.4 SPI Operation............................................................................................................ 1750

16.4.1 Introduction to Operation ..................................................................................... 175016.4.2 SPI Module Slave and Master Operation Modes ......................................................... 175116.4.3 Initialization Upon Reset ..................................................................................... 175316.4.4 Data Format.................................................................................................... 175416.4.5 Baud Rate and Clocking Schemes ......................................................................... 175416.4.6 Data Transfer Example ....................................................................................... 1756

16.5 SPI DMA Transfers ..................................................................................................... 175716.5.1 Transmitting Data Using SPI with DMA .................................................................... 175816.5.2 Receiving Data Using SPI with DMA ....................................................................... 1758

16.6 SPI Interrupts ............................................................................................................ 175916.6.1 SPI Interrupt Control Bits..................................................................................... 1760

16.7 SPI FIFO Description ................................................................................................... 176016.8 SPI High-Speed Mode .................................................................................................. 1761

16.8.1 GPIOs Required for High-Speed Mode .................................................................... 176116.8.2 Configuring the SPI for High-Speed Mode................................................................. 1762

16.9 SPI 3-Wire Mode Description .......................................................................................... 176216.10 SPI STEINV Bit in Digital Audio Transfers .......................................................................... 176416.11 SPI Waveforms.......................................................................................................... 176516.12 Registers ................................................................................................................. 1771

16.12.1 SPI Base Addresses ........................................................................................ 1771




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16.12.2 SPI_REGS Registers ....................................................................................... 177217 Serial Communications Interface (SCI) .............................................................................. 1793

17.1 Enhanced SCI Module Overview...................................................................................... 179417.1.1 Architecture .................................................................................................... 1795

17.2 Registers ................................................................................................................. 180617.2.1 SCI Base Addresses.......................................................................................... 180617.2.2 SCI_REGS Registers ......................................................................................... 1807

18 Inter-Integrated Circuit Module (I2C).................................................................................. 182618.1 Introduction to the I2C Module ........................................................................................ 1827

18.1.1 Features ........................................................................................................ 182718.1.2 Features Not Supported...................................................................................... 182718.1.3 Functional Overview .......................................................................................... 182818.1.4 Clock Generation.............................................................................................. 182918.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1830

18.2 I2C Module Operational Details ....................................................................................... 183118.2.1 Input and Output Voltage Levels ............................................................................ 183118.2.2 Data Validity ................................................................................................... 183118.2.3 Operating Modes .............................................................................................. 183118.2.4 I2C Module START and STOP Conditions ................................................................ 183218.2.5 Serial Data Formats........................................................................................... 183318.2.6 NACK Bit Generation ......................................................................................... 183418.2.7 Clock Synchronization ........................................................................................ 183518.2.8 Arbitration ...................................................................................................... 1835

18.3 Interrupt Requests Generated by the I2C Module .................................................................. 183618.3.1 Basic I2C Interrupt Requests ................................................................................ 183618.3.2 I2C FIFO Interrupts ........................................................................................... 1837

18.4 Resetting or Disabling the I2C Module ............................................................................... 183818.5 Registers ................................................................................................................. 1839

18.5.1 I2C Base Addresses .......................................................................................... 183918.5.2 I2C_REGS Registers ......................................................................................... 1840

19 Multichannel Buffered Serial Port (McBSP) ........................................................................ 186219.1 Overview.................................................................................................................. 1863

19.1.1 Features of the McBSPs ..................................................................................... 186319.1.2 McBSP Pins/Signals .......................................................................................... 1864

19.2 McBSP Operation ....................................................................................................... 186519.2.1 Data Transfer Process of McBSPs ......................................................................... 186619.2.2 Companding (Compressing and Expanding) Data........................................................ 186619.2.3 Clocking and Framing Data .................................................................................. 186819.2.4 Frame Phases ................................................................................................. 187019.2.5 McBSP Reception............................................................................................. 187219.2.6 McBSP Transmission ......................................................................................... 187419.2.7 Interrupts and DMA Events Generated by a McBSP..................................................... 1875

19.3 McBSP Sample Rate Generator ...................................................................................... 187519.3.1 Block Diagram ................................................................................................. 187619.3.2 Frame Synchronization Generation in the Sample Rate Generator .................................... 187919.3.3 Synchronizing Sample Rate Generator Outputs to an External Clock ................................. 187919.3.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 1881

19.4 McBSP Exception/Error Conditions ................................................................................... 188219.4.1 Types of Errors ................................................................................................ 188219.4.2 Overrun in the Receiver ...................................................................................... 188219.4.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 188419.4.4 Overwrite in the Transmitter ................................................................................. 188619.4.5 Underflow in the Transmitter................................................................................. 1887




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19.4.6 Unexpected Transmit Frame-Synchronization Pulse..................................................... 188819.5 Multichannel Selection Modes ......................................................................................... 1890

19.5.1 Channels, Blocks, and Partitions............................................................................ 189019.5.2 Multichannel Selection........................................................................................ 189119.5.3 Configuring a Frame for Multichannel Selection .......................................................... 189119.5.4 Using Two Partitions .......................................................................................... 189119.5.5 Using Eight Partitions......................................................................................... 189319.5.6 Receive Multichannel Selection Mode...................................................................... 189419.5.7 Transmit Multichannel Selection Modes ................................................................... 189419.5.8 Using Interrupts Between Block Transfers................................................................. 1896

19.6 SPI Operation Using the Clock Stop Mode .......................................................................... 189719.6.1 SPI Protocol.................................................................................................... 189719.6.2 Clock Stop Mode .............................................................................................. 189819.6.3 Bits Used to Enable and Configure the Clock Stop Mode ............................................... 189819.6.4 Clock Stop Mode Timing Diagrams......................................................................... 189919.6.5 Procedure for Configuring a McBSP for SPI Operation .................................................. 190119.6.6 McBSP as the SPI Master ................................................................................... 190119.6.7 McBSP as an SPI Slave...................................................................................... 1903

19.7 Receiver Configuration ................................................................................................. 190419.7.1 Programming the McBSP Registers for the Desired Receiver Operation ............................. 190419.7.2 Resetting and Enabling the Receiver....................................................................... 190519.7.3 Set the Receiver Pins to Operate as McBSP Pins ....................................................... 190519.7.4 Enable/Disable the Digital Loopback Mode................................................................ 190619.7.5 Enable/Disable the Clock Stop Mode....................................................................... 190619.7.6 Enable/Disable the Receive Multichannel Selection Mode .............................................. 190719.7.7 Choose One or Two Phases for the Receive Frame ..................................................... 190719.7.8 Set the Receive Word Length(s) ............................................................................ 190819.7.9 Set the Receive Frame Length .............................................................................. 190819.7.10 Enable/Disable the Receive Frame-Synchronization Ignore Function................................ 190919.7.11 Set the Receive Companding Mode ...................................................................... 191019.7.12 Set the Receive Data Delay................................................................................ 191119.7.13 Set the Receive Sign-Extension and Justification Mode ............................................... 191319.7.14 Set the Receive Interrupt Mode............................................................................ 191419.7.15 Set the Receive Frame-Synchronization Mode.......................................................... 191419.7.16 Set the Receive Frame-Synchronization Polarity........................................................ 191619.7.17 Set the Receive Clock Mode ............................................................................... 191819.7.18 Set the Receive Clock Polarity............................................................................. 191919.7.19 Set the SRG Clock Divide-Down Value................................................................... 192119.7.20 Set the SRG Clock Synchronization Mode ............................................................... 192119.7.21 Set the SRG Clock Mode (Choose an Input Clock)..................................................... 192219.7.22 Set the SRG Input Clock Polarity.......................................................................... 1923

19.8 Transmitter Configuration .............................................................................................. 192319.8.1 Programming the McBSP Registers for the Desired Transmitter Operation .......................... 192319.8.2 Resetting and Enabling the Transmitter.................................................................... 192419.8.3 Set the Transmitter Pins to Operate as McBSP Pins .................................................... 192519.8.4 Enable/Disable the Digital Loopback Mode................................................................ 192519.8.5 Enable/Disable the Clock Stop Mode....................................................................... 192519.8.6 Enable/Disable Transmit Multichannel Selection ......................................................... 192619.8.7 Choose One or Two Phases for the Transmit Frame .................................................... 192819.8.8 Set the Transmit Word Length(s) ........................................................................... 192819.8.9 Set the Transmit Frame Length ............................................................................. 192919.8.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function ............................... 193019.8.11 Set the Transmit Companding Mode...................................................................... 1931




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19.8.12 Set the Transmit Data Delay ............................................................................... 193219.8.13 Set the Transmit DXENA Mode............................................................................ 193419.8.14 Set the Transmit Interrupt Mode ........................................................................... 193419.8.15 Set the Transmit Frame-Synchronization Mode ......................................................... 193519.8.16 Set the Transmit Frame-Synchronization Polarity....................................................... 193619.8.17 Set the SRG Frame-Synchronization Period and Pulse Width ........................................ 193719.8.18 Set the Transmit Clock Mode .............................................................................. 193819.8.19 Set the Transmit Clock Polarity ............................................................................ 1938

19.9 Emulation and Reset Considerations ................................................................................. 193919.9.1 McBSP Emulation Mode ..................................................................................... 194019.9.2 Resetting and Initializing McBSPs .......................................................................... 1940

19.10 Data Packing Examples................................................................................................ 194219.10.1 Data Packing Using Frame Length and Word Length .................................................. 194219.10.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function ............... 1944

19.11 Interrupt Generation .................................................................................................... 194419.11.1 McBSP Receive Interrupt Generation..................................................................... 194519.11.2 McBSP Transmit Interrupt Generation .................................................................... 194519.11.3 Error Flags ................................................................................................... 194619.11.4 McBSP Interrupt Enable Register ......................................................................... 1946

19.12 McBSP Modes........................................................................................................... 194619.13 McBSP Registers ....................................................................................................... 1948

19.13.1 McBSP Base Addresses.................................................................................... 194819.13.2 Data Receive Registers (DRR[1,2]) ....................................................................... 194919.13.3 Data Transmit Registers (DXR[1,2]) ...................................................................... 194919.13.4 Serial Port Control Registers (SPCR[1,2]) ............................................................... 195019.13.5 Receive Control Registers (RCR[1, 2]) .................................................................. 195519.13.6 Transmit Control Registers (XCR1 and XCR2) .......................................................... 195719.13.7 Sample Rate Generator Registers (SRGR1 and SRGR2) ............................................. 196019.13.8 Multichannel Control Registers (MCR[1,2]) .............................................................. 196219.13.9 Pin Control Register (PCR)................................................................................. 196719.13.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,

RCERG, RCERH) .............................................................................................. 196919.13.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,

XCERG, XCERH) .............................................................................................. 197120 Controller Area Network (CAN) ......................................................................................... 1974

20.1 Overview ................................................................................................................. 197520.1.1 Features ....................................................................................................... 197520.1.2 Functional Description ....................................................................................... 197520.1.3 Block Diagram ................................................................................................ 1976

20.2 Operating Modes ........................................................................................................ 197720.2.1 Software Initialization ........................................................................................ 197720.2.2 CAN Message Transfer (Normal Operation) .............................................................. 197720.2.3 Test Modes .................................................................................................... 1978

20.3 Multiple Clock Source .................................................................................................. 198120.4 Interrupt Functionality .................................................................................................. 1981

20.4.1 Message Object Interrupts .................................................................................. 198120.4.2 Status Change Interrupts .................................................................................... 198120.4.3 Error Interrupts ................................................................................................ 1982

20.5 Global Power-down Mode ............................................................................................. 198220.5.1 Entering Global Power-down Mode ........................................................................ 198220.5.2 Wakeup from Global Power-down Mode .................................................................. 1982

20.6 Local Power-down Mode .............................................................................................. 198220.6.1 Entering Local Power-down Mode ......................................................................... 198220.6.2 Wakeup from Local Power-down Mode ................................................................... 1982




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20.7 Parity Check Mechanism .............................................................................................. 198320.7.1 Behavior on Parity Error ..................................................................................... 1983

20.8 Debug Mode ............................................................................................................ 198320.9 Module Initialization .................................................................................................... 198420.10 Configuration of Message Objects ................................................................................... 1984

20.10.1 Configuration of a Transmit Object for Data Frames ................................................... 198420.10.2 Configuration of a Transmit Object for Remote Frames ............................................... 198520.10.3 Configuration of a Single Receive Object for Data Frames ........................................... 198520.10.4 Configuration of a Single Receive Object for Remote Frames ....................................... 198520.10.5 Configuration of a FIFO Buffer ............................................................................ 1986

20.11 Message Handling ..................................................................................................... 198620.11.1 Message Handler Overview ............................................................................... 198620.11.2 Receive/Transmit Priority .................................................................................. 198620.11.3 Transmission of Messages in Event Driven CAN Communication ................................... 198720.11.4 Updating a Transmit Object ............................................................................... 198720.11.5 Changing a Transmit Object ............................................................................... 198720.11.6 Acceptance Filtering of Received Messages ............................................................ 198820.11.7 Reception of Data Frames ................................................................................. 198820.11.8 Reception of Remote Frames ............................................................................. 198820.11.9 Reading Received Messages ............................................................................. 198820.11.10 Requesting New Data for a Receive Object ........................................................... 198920.11.11 Storing Received Messages in FIFO Buffers .......................................................... 198920.11.12 Reading from a FIFO Buffer ............................................................................. 1989

20.12 CAN Bit Timing ......................................................................................................... 199020.12.1 Bit Time and Bit Rate ....................................................................................... 199120.12.2 Configuration of the CAN Bit Timing ..................................................................... 1995

20.13 Message Interface Register Sets .................................................................................... 199820.13.1 Message Interface Register Sets 1 and 2 ............................................................... 199920.13.2 IF3 Register Set ............................................................................................. 1999

20.14 Message RAM .......................................................................................................... 200020.14.1 Structure of Message Objects ............................................................................. 200020.14.2 Addressing Message Objects in RAM ................................................................... 200220.14.3 Message RAM Representation in Debug Mode ........................................................ 2003

20.15 Registers ................................................................................................................. 200520.15.1 CAN Base Addresses ....................................................................................... 200520.15.2 CAN_REGS Registers ...................................................................................... 2006

21 Universal Serial Bus (USB) Controller................................................................................ 205921.1 Introduction............................................................................................................... 206021.2 Features .................................................................................................................. 2060

21.2.1 Block Diagram ................................................................................................. 206021.2.2 Signal Description ............................................................................................. 206121.2.3 VBus Recommendations ..................................................................................... 2061

21.3 Functional Description .................................................................................................. 206221.3.1 Operation as a Device........................................................................................ 206221.3.2 Operation as a Host........................................................................................... 206621.3.3 DMA Operation ................................................................................................ 206921.3.4 Address/Data Bus Bridge .................................................................................... 2070

21.4 Initialization and Configuration......................................................................................... 207121.4.1 Pin Configuration .............................................................................................. 207221.4.2 Endpoint Configuration ....................................................................................... 2072

21.5 Register Map............................................................................................................. 207221.6 Register Descriptions ................................................................................................... 2077

21.6.1 USB Device Functional Address Register (USBFADDR), offset 0x000................................ 2077




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21.6.2 USB Power Management Register (USBPOWER), offset 0x001....................................... 207821.6.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002 ..................................... 208021.6.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004...................................... 208121.6.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006 .................................... 208221.6.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008 ..................................... 208321.6.7 USB General Interrupt Status Register (USBIS), offset 0x00A ......................................... 208421.6.8 USB Interrupt Enable Register (USBIE), offset 0x00B ................................................... 208621.6.9 USB Frame Value Register (USBFRAME), offset 0x00C................................................ 208821.6.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E ............................................. 208821.6.11 USB Test Mode Register (USBTEST), offset 0x00F.................................................... 208921.6.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3]) ........................................... 209121.6.13 USB Device Control Register (USBDEVCTL), offset 0x060 ........................................... 209221.6.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062...................... 209421.6.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063 ...................... 209521.6.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064...................... 209621.6.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066 ...................... 209721.6.18 USB Connect Timing Register (USBCONTIM), offset 0x07A.......................................... 209821.6.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset

0x07D ............................................................................................................ 209921.6.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset

0x07E ............................................................................................................ 209921.6.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-

USBTXFUNCADDR[3])........................................................................................ 210021.6.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[3]) 210121.6.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[3]) ..... 210221.6.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-

USBRXFUNCADDR[3) ........................................................................................ 210321.6.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[3). 210421.6.26 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[3]) ..... 210521.6.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[3])......... 210621.6.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102 ..................... 210721.6.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103.................... 210921.6.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108....................... 211021.6.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A ........................................... 211021.6.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................ 211121.6.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[3).. 211221.6.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-

USBTXCSRH[3]) ............................................................................................... 211521.6.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[3])......... 211721.6.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[3).. 211821.6.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-

USBRXCSRH[3]) ............................................................................................... 212121.6.38 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[3) .......... 212321.6.39 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[3]) .... 212421.6.40 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[3])... 212521.6.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[3])..... 212621.6.42 USB Host Receive Polling Interval Endpoint n Register (USBRXINTERVAL[1]-

USBRXINTERVAL[3]) ......................................................................................... 212721.6.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-

USBRQPKTCOUNT[3) ........................................................................................ 212821.6.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340..... 212921.6.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 .... 213021.6.46 USB External Power Control Register (USBEPC), offset 0x400 ...................................... 213121.6.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404 ........ 213321.6.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408 ................. 2134




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21.6.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C . 213521.6.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410 ................. 213621.6.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414.................... 213721.6.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418........... 213821.6.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C.................... 213921.6.54 USB DMA Select Register (USBDMASEL), offset 0x450 .............................................. 2140

22 External Memory Interface (EMIF) ..................................................................................... 214222.1 Introduction............................................................................................................... 2143

22.1.1 Purpose of the Peripheral .................................................................................... 214322.1.2 Features ........................................................................................................ 214322.1.3 Functional Block Diagram .................................................................................... 2144

22.2 EMIF Module Architecture ............................................................................................. 214422.2.1 EMIF Clock Control ........................................................................................... 214522.2.2 EMIF Requests ................................................................................................ 214522.2.3 EMIF Signal Descriptions .................................................................................... 214522.2.4 EMIF Signal Multiplexing Control ........................................................................... 214622.2.5 SDRAM Controller and Interface ............................................................................ 214622.2.6 Asynchronous Controller and Interface .................................................................... 215922.2.7 Data Bus Parking.............................................................................................. 217122.2.8 Reset and Initialization Considerations..................................................................... 217122.2.9 Interrupt Support .............................................................................................. 217122.2.10 DMA Event Support ......................................................................................... 217322.2.11 EMIF Signal Multiplexing ................................................................................... 217322.2.12 Memory Map ................................................................................................. 217322.2.13 Priority and Arbitration ...................................................................................... 217422.2.14 System Considerations ..................................................................................... 217522.2.15 Power Management ......................................................................................... 217622.2.16 Emulation Considerations .................................................................................. 2176

22.3 Example Configuration ................................................................................................. 217722.3.1 Hardware Interface............................................................................................ 217722.3.2 Software Configuration ....................................................................................... 2177

22.4 Registers ................................................................................................................. 218522.4.1 EMIF Base Addresses........................................................................................ 218522.4.2 EMIF_REGS Registers ....................................................................................... 218622.4.3 EMIF1_CONFIG_REGS Registers ......................................................................... 2203

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