tdaip01 datasheet rev1 - s3-eu-west-1.amazonaws.com

TDAIP01

Advanced Imaging Platform Rev 1.0 DATASHEET

February 2017 - Rev 1.0 cameramodules.td-next .com

TDnext Advanced Imaging Platform Modules

TDnext TDAIP01 is a compact 30x30 mm module that mounts on a user PCB. The TDAIP01 features video, still image and audio processing using a powerful low cost and low power hardware (the TDAIP01 does not need an external DRAM). By simple configuration, the TDAIP01 is ready to support several audio/video inputs, and to drive many external peripherals such as a 4G/4G modem, Wi-Fi module, SDCard and also provides USB, SPI, UART and GPIOs interfaces for control functions. The integrated high performance processor supports both H.264 and MJPEG video compression.

No firmware development is required: user just has to configure TDAIP01’s both working mode and peripheral settings. Hence, by using “easy” scripts files, the required functionalities can be activated, and actions to be performed are configured; the TDAIP01 can then work in stand-alone mode, no additional processor is mandatory. Such configuration setup may be performed during product manufacturing. ELECTRICAL FEATURES

Power Supply: 3.3 V ± 10%

Power consumption:

o TD7740 VGA w/ H.264 video + AAC audio

compression recording on SDCard:

205 mA @ 3.3V (0.7 W)

TD7740 VGA w/ MJPEG video compression +

PCM 11 ksps audio streaming on USB:

190 mA @ 3.3V (0.6 W)

Adjustable power supply for external camera:

o AVDD : From 1.2 V to 3.3 V

o DVDD : From 1.25 V to 3.3 V

o DOVDD : From 1.2 V to 3.3 V

APPLICATION FEATURES

Frame rates up to 720p @60ps

8-10 bits CMOS parallel DVP Interface

1 or 2-lanes MIPI Interface

I2S Stereo audio codec interface

256Kbytes + 2Mbytes Internal SRAM

2Mbytes Internal serial flash

H.264 compression

o Baseline Profile : Level 3.0 for QVGA @60

fps

o Baseline Profile : Level 3.0 for VGA @60

fps

o Main Profile, Level 4.0 for 720p @60 fps

MJPEG video compression

AAC audio compression:

o High Quality Audio Profile Level 2

Wi-Fi driver for various chips

3G/4G modem drivers for various modules

Embedded protocols:

o ARP, ICMP, IP, UDP, TCP, DHCP, DNS,

HTTP

o RTP, RTCP, RTSP

APPLICATIONS

Home Automation/Security

Video conferencing

Industrial vision

Video door phone

Drones

GENERAL DESCRIPTION

TDAIP01



Disclaimer : The information in this document is provided in connection with Telecom Design products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Telecom Design products. TELECOM DESIGN ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL TELECOM DESIGN BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF TELECOM DESIGN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Telecom Design makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Telecom Design does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Telecom Design products are not suitable for, and shall not be used in, automotive applications. Telecom Design products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2016-2017 Telecom Design S.A. All rights reserved. Telecom Design®, logo and combinations thereof, are registered trademarks of Telecom Design S.A. TDnext is a trademark of TDnext. Other terms and product names may be trademarks of other.

TDAIP01



Description

TDnext TDAIP01 is a compact module that mounts on a user PCB. The TDAIP01 module features video, image and audio processing capabilities using a powerful hardware while maintaining a low cost and low power consumption (the TDAIP01 does not need an external DRAM). By simple configuration, the TDAIP01 module is ready to support simultaneous audio/video inputs, and to drive many external peripherals as a 3G/4G modem, Wi-Fi module, SDCard, behave as an USB camera/mass storage/printer class device and also support SPI, UART and GPIOs interfaces for control functions. The integrated high performance processor supports H.264 and MJPEG compression. No firmware development is required: user just has to configure TDAIP01’s both working mode and peripheral settings. Hence, by using “easy” scripts files, the required functionalities can be activated, and actions to be performed are configured; the TDAIP01 can then work in stand-alone mode, no additional processor is mandatory. Such configuration setup may be performed during product manufacturing. Video streaming over external Wi-Fi module or 3G/4G modem, microSD Card recording, connecting a PIR sensor, an external I/R LED for night vision, are some of the applications that may be achieved easily, only by simple TDAIP01 module configuration. The TDAIP01 low power consumption makes it possible to design battery powered products thanks to the smart highly integrated processor. During video streaming, the H.264 compression uses only the integrated DRAM memory and does not require external additional DRAM chips, thus providing more integration, as well as lowering the cost and power consumption at the same time. The TDAIP01 module can be driven by a host processor if needed. Through several available interfaces like USB device, UART or SPI, a host may configure and receive a video streaming in real-time.

TDAIP01



CONTENT

1 General Description ............................... ........................................................................... 7

1.1 Simplified Block Diagram .......................... ..................................................................................................... 7

1.2 Product Versions................................... .......................................................................................................... 7

1.3 TDAIP01 Pin diagram ............................... ....................................................................................................... 8

1.4 TDAIP01 Pin description ........................... ..................................................................................................... 9

1.5 Mezzanine Connector Pin diagram ................... ........................................................................................... 14

1.6 Mezzanine connector Pin description ............... .......................................................................................... 15

1.7 Package Marking ................................... ........................................................................................................ 16

1.8 Definition of Test Conditions ..................... .................................................................................................. 16

2 Electrical Specifications ......................... ........................................................................ 17

2.1 ESD Notice ........................................ ............................................................................................................. 17

2.2 Absolute Maximum Rating ........................... ................................................................................................ 17

2.3 Recommended Operating Conditions................... ...................................................................................... 17

2.4 DC Characteristics ................................ ........................................................................................................ 18

2.5 AC Characteristics ................................ ........................................................................................................ 19

3 Module Power Description .......................... ................................................................... 20

3.1 Supply voltages for external camera (CIS XXX / ADJXXX) ............................................................................. 20

3.2 DOVDDTDAIP01 power domain ..................................... ................................................................................... 22

4 Recommended design ................................ .................................................................... 24

4.1 TDAIP01 Power Supply .............................. ................................................................................................... 24

4.2 Camera interface .................................. ......................................................................................................... 25

4.3 Peripheral interfaces ............................. ........................................................................................................ 26

5 High speed design guidelines ...................... .................................................................. 29

5.1 PCB definition .................................... ............................................................................................................ 29

5.2 Controlled impedance of high speed differential tra ces ............................................... ............................ 29

5.3 Controlled delay of differential wire ............. ............................................................................................... 31

5.4 Via considerations for high speed signal design ... ................................................................................... 31

6 Mechanical Information ............................ ...................................................................... 34

6.1 Package Outline ................................... ......................................................................................................... 34

6.2 Recommended PCB Land Pattern ...................... ......................................................................................... 35

7 Production Information’s .......................... ...................................................................... 36

7.1 Ordering Information .............................. ...................................................................................................... 36

TDAIP01



7.2 Related Products .................................. ......................................................................................................... 36

7.3 Soldering Profile.................................. .......................................................................................................... 37

7.4 Shipping Packaging ................................ ...................................................................................................... 38

7.5 Product Label ..................................... ........................................................................................................... 38

TDAIP01



1 General Description

1.1 Simplified Block Diagram

Figure 1. TDAIP01 block diagram

1.2 Product Versions The features of the two product variants of TDAIP01 are detailed in the following table Table 1. TDAIP01 variants and key Parameters

Part Number Camera interfaces Package Type Operating Temperature

TDAIP01-RP 2-Lanes MiPi / 10-bits CMOS Parallel / without CIS_xxx and ADJ_xxx supplies power option

LGA128 Pb-free -25°C to +70°C

TDAIP01-LE 2-Lanes MiPi / 10-bits CMOS Parallel LGA128 Pb-free -25°C to +70°C

TDAIP01 2-Lanes MiPi / 10-bits CMOS Parallel / 8-bits CMOS Parallel Mezzanine connector


TDAIP01



1.3 TDAIP01 Pin diagram

Figure 2. TDAIP01 Pin diagram

Please note that the module pins belong to a specific power domain, depending on their color in the above diagram. The 3 available power domains are:

- VDD General purpose power domain for the TDAIP01, used for user interfaces like SPI, I2C, I2S, SD card, Wi-Fi, 3G/4G Modem …

- DOVDD_TDAIP01 Camera module power domain, to comply with Camera requirements - MIPI TDAIP01 internally-generated, compliant with MIPI standard

TDAIP01



1.4 TDAIP01 Pin description Table 2. DC Power pin descriptions

Pin number Signal Name Pin

Type Function Remark

Power and Ground

1 VDD Input Supply Voltage of TDAIP01 module Power = 3.3 V +/-5%

108 VDD Input Supply Voltage of TDAIP01 module Power = 3.3 V +/-5%

97 DOVDDTDAIP01 Input Supply Voltage of TDAIP01 IO interface To be connect at VDD or CISDOVDD

99 ADJDOVDD Input CISDOVDD supply voltage adjustment Pull-down resistor

100 CISDOVDD Output Interface Supply Voltage for external camera (1.2 V – 3.3 V) depending on ADJDOVDD

102 ADJDVDD Input CISDVDD supply voltage adjustment Pull-down resistor

103 CISDVDD Output Digital Supply Voltage for external camera (1.25 V – 3.3 V) depending on ADJDVDD

105 ADJAVDD Input CISAVDD supply voltage adjustment Pull-down resistor

106 CISAVDD Output Analog supply Voltage for external camera (1.2 V – 3.3 V) depending on ADJDOVDD

2 GND Ground TDAIP01 ground














TDAIP01



Table 3. SENSOR interface pin descriptions


Type Function Power Domain

Sensor CMOS Parallel interface

3 Y0 Input Digital video input data 0 DOVDDTDAIP01










13 HSYNC Input Sensor horizontal sync DOVDDTDAIP01

14 PCLK Input Pixel clock input DOVDDTDAIP01

15 VSYNC Input Sensor vertical sync DOVDDTDAIP01

16 XCLK Output Output clock to sensor as reference clock DOVDDTDAIP01

Sensor MIPI interface

36 MRXDP1 Input MIPI receiver data lane 1 differential positive Internal

37 MRXDN1 Input MIPI receiver data lane 1 differential negative Internal

38 MRXCP Input MIPI receiver clock lane differential positive Internal

39 MRXCN Input MIPI receiver clock lane differential negative Internal

40 MRXDP0 Input MIPI receiver data lane 0 differential positive Internal

41 MRXDN0 Input MIPI receiver data lane 0 differential negative Internal

CMOS Image Sensor GPIO

43 CIS_GPIO0 I/O SENSOR GPIO0 with customized power domain DOVDDTDAIP01







28 STROBE Output Strobe output Flash and LED control Directly provided by TDAIPA01 plugged camera

DOVDDTDAIP01

TDAIP01



Table 4. Interface pin descriptions (part 1)



I2C interface

18 SCL Output Master I2C clock (internal 1.5kΩ pull-up) DOVDDTDAIP01

19 SDA I/O Master I2C data (internal 1.5kΩ pull-up) DOVDDTDAIP01

SPI interface

20 MOSI I/O Serial interface with master output and slave input VDD

21 MISO I/O Serial interface with master input and slave output VDD

22 CLK I/O Serial interface clock VDD

23 INT I/O Serial interface interruption VDD

24 CS I/O Serial interface chip select VDD

UART 1 interface

59 TXD1 I/O UART 1 debug data transmit DOVDDTDAIP01

60 RXD1 I/O UART 1 debug data receive (internal pull-up) DOVDDTDAIP01

UART 0 interface

78 CTS0 I/O UART 0 clear to send VDD

79 RTS0 I/O UART 0 request to send VDD

80 TXD0 I/O UART 0 data transmit VDD

81 RXD0 I/O UART 0 data receive (internal pull-up) VDD

USB device interface

57 USBD_DM I/O USB Device differential pair negative VDD

56 USBD_DP I/O USB Device differential pair positive VDD

USB Host interface

74 USBH_DM I/O USB Host differential pair negative VDD

75 USBH_DP I/O USB Host differential pair positive VDD

76 USBH_VBUS Input USB Device detection (May be float) VDD

TDAIP01



Table 5. Interface pin descriptions (part 2)



Storage card interface

67 SDCARD_DAT3 I/O Storage card data 3 VDD




71 SDCARD_CLK I/O Storage card clock VDD

72 SDCARD_SCMD I/O Storage card command VDD

Storage IO interface

48 SDIO_DAT0 I/O Storage IO data 0 VDD




52 SDIO_CLK I/O Storage IO clock VDD

53 SDIO_SCMD I/O Storage IO command VDD

GPIO interface

45 USR_GPIO0 I/O General purpose I/O 0 VDD







TV interface

25 IOP Output TV DAC differential output positive VDD

26 ION Output TV DAC differential output negative VDD

24 DAC RES Input TV DAC Pull-up (May be float) VDD

Audio interface and BOOT MODE

92 I2S_DI1 I/O Audio interface 1 data VDD

93 I2S_LCK1 I/O Audio interface 1 line clock VDD

94 I2S_DI0 I/O Audio interface 0 data VDD

95 I2S_MCLK I/O Audio interface master clock VDD

96 I2S_BCK1 I/O Audio interface 1 bit clock VDD

TDAIP01



Table 6. Miscellaneous pin descriptions



ROM BOOT

88 BOOT0 BOOTMODE [0] DOVDDTDAIP01

89 BOOT1 BOOTMODE [1] DOVDDTDAIP01

90 BOOT2 BOOTMODE [2] VDD


RAM BOOT





Miscellaneous

83 /RST I/O Power on reset (internal pull-up) VDD

33 Reserved NC Reserved I/O NC



TDAIP01



1.5 Mezzanine Connector Pin diagram The TDAIP01 module version (not the TDAIP01-RP or TDAIP01-LE versions) has a mezzanine connector (ref. DF30RB-30DP-0.4V) which can be fitted with an 8/10 bits CMOS Parallel camera (ref. DF30RB-30DS-0.4V). Figure 3 depicts the pins diagram for this connector. Note : The camera must be oriented such that it lays over the TDAIP01 top shield cover.

Figure 3. “ DF30RB-30DP-0.4V” Mezzanine connector pin diagram

TDAIP01



1.6 Mezzanine connector Pin description Table 7. Internal connector pin description 1

Pin number Signal Name Pin Type Function


2 DOVDDTDAIP01 Input Camera Interface Supply Voltage

3 CISAVDD Input Camera Analog supply Voltage

4 XCLK Input Input clock for sensor


6 SDA I/O I2C data

7 CISDVDD Input Camera Digital Supply Voltage

8 SCL Input I2C clock


10 Y0 Output Digital video input data 0


12 NC NC Not connected


14 NC NC Not connected




18 CIS_GPIO5 I/O SENSOR GPIO5




22 HSYNC Output Sensor horizontal sync




26 PCLK Output Pixel clock Output


28 STROBE Output Strobe output flash and LED control

29 DOVDDTDAIP01 Input Camera Interface Supply Voltage

30 VSYNC Output Sensor vertical sync

Notes: 1. All interfaces use the DOVDDTDAIP01 power domain

TDAIP01



1.7 Package Marking

Figure 4. Package marking (Top View)

Trade Mark: TDnext

Module Name: TDAIP01

Lot: XXXXX-XXXX: TDnext Lot No

DC: YYWW: Date code

Label: Label with module ID

1.8 Definition of Test Conditions

1.8.1 Production Test Conditions:

TA = + 25°C

VDD = +3.3 VDC

1.8.2 Qualification Test Conditions:

TA = -25 to +75°C (Typical TA = 25°C)

VDD = +3.3 VDC (Typical VDD = 3.3 VDC)

TDAIP01RP / TDAIP01LE TDAIP01

TDAIP01



2 Electrical Specifications

2.1 ESD Notice TDAIP01 modules are ESD sensitive devices, appropriate precautions should be taken during TDAIP01 assembly in the final product.

2.2 Absolute Maximum Rating Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution: ESD sensitive device. Table 8. Absolute Maximum Ratings

Symbol Description Min Max Unit

VDDmr TDAIP01 Supply Voltage -0.3 3.6 V

DOVDDTDAIP01mr DOVDD TDAIP01 Supply Voltage -0.3 3.6 V

TA Operating Ambient Temperature Range -25 +70 °C

TSTG Storage Temperature Range -40 +95 °C

ICISDOVDDmr1 Interface current consumption of external camera - 350 mA

ICISDVDDmr1 Digital current consumption of external camera - 500 mA

ICISAVDDmr1 Analog current consumption of external camera - 350 mA

Notes: 2. Maximum ratings currents do not include output regulation. Any regulated output voltage less than 3.3V results

in a reduction of the maximum rating value

2.3 Recommended Operating Conditions Table 9. Operating Conditions 1

Symbol Parameter Conditions Min Typ Max Unit

VDD TDAIP01 Supply Voltage 3.2 3.3 3.4 V

DOVDDTDAIP01 DOVDDTDAIP01 Supply Voltage CISDOVDD - 0.2 CISDOVDD or

VDD VDD + 0.2 V

ICISDOVDD Interface current consumption

of external camera

CISDOVDD = 1.2 V CISDOVDD = 1.8 V CISDOVDD = 2.8 V CISDOVDD = 3.3 V

- -

80 120 200 250

mA

ICISDVDD Digital current consumption of external camera

CISDVDD = 1.25 V CISDVDD = 1.8 V CISDVDD = 2.8 V CISDVDD = 3.3 V

- -

200 300 400 450

mA

ICISAVDD Analog current consumption of external camera

CISAVDD = 1.2 V CISAVDD = 1.8 V CISAVDD = 2.8 V CISAVDD = 3.3 V

- -

80 120 200 250

mA

Notes: 1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max

limits are listed in the “Production Test Conditions:” section in “1.8.1” on page 16.

TDAIP01



2.4 DC Characteristics Table 10. DC Characteristics

Symbol Parameter Min Typ Max Unit

VVDDIH Input Voltage High (VDD Power domain I/O) 0.7 x VDD - - V

VVDDIL Input Voltage Low (VDD Power domain I/O) - - 0.3 x VDD V

VDOVDDIH Input Voltage High (DOVDDTDAIP01 Power domain I/O)

0.7 x DOVDDTDAIP01 - - V

VDOVDDIL Input Voltage Low (DOVDDTDAIP01 Power domain I/O) - - 0.3 x DOVDDTDAIP01 V

VVDDOH Output Voltage High (VDD Power domain I/O) 0.9 x VDD - - V

VVDDOL Output Voltage Low (VDD Power domain I/O) - - 0.1 x VDD V

VDOVDDOH Output Voltage High (DOVDDTDAIP01 Power domain I/O) 0.9 x DOVDDTDAIP01 - - V

VDOVDDOL Output Voltage Low (DOVDDTDAIP01 Power domain I/O) - - 0.1 x DOVDDTDAIP01 V

IDD1 Operating current (720p / 30fps) - 180 - mA

Notes: 1. Operating current excluding external camera consumption like CIS_XXX power supply connections

TDAIP01



2.5 AC Characteristics

2.5.1 I²C requirements

Table 11. Timing specifications

Symbol Parameter Min Typ Max Unit

fI2C Clock frequency - - 400 kHz

tLOW Clock low period 1.3 - - µs

tHIGH Clock high period 600 - - ns

tAA I²C low to data out valid 100 900 ns

tBUF Bus free time before new START 1.3 - - µs

tHD:STA START condition hold time 600 - - ns

tSU:STA START condition setup time 600 - - ns

tHD:DAT Data in hold time 0 - - µs

tSU:DAT Data in setup time 100 - - ns

tSU:STO STOP condition setup time 600 - ns

tR, tf I²C rise/fall times - 300 ns

tDH Data out hold time 50 - - ns

2.5.2 Camera interface requirements

Table 12. Timing specifications


Tpclk PCLK period 11 - - ns

tbclk PCLK – Data width offset time Assuming load is 5 pF 6 - - ns

taclk Data end before next PCLK Assuming load is 2 pF 0 - - ns

TDAIP01



3 Module Power Description

3.1 Supply voltages for external camera (CIS XXX / ADJXXX) CISDOVDD, CISDVDD and CISAVDD are power supply voltage generated by the TDAIP01 module dedicated to external camera power supply. Each supply voltage can be customized according to the camera’s requirements using the ADJXXX pins. Note that the TDAIP01 power supply voltage adjustme nt for external camera is an option which is not av ailable on the TDAIP01-RP version. These supplies voltages have internal ON/OFF control in order to optimize consumption. Figure 5 depicts a diagram describing the function of these power management controls. RXXX must be placed as close as possible to the TDAIP01 ADJXXX pin.

Figure 5. Diagram of CIS XXX supplies voltages

Note that if CIS DOVDD is connected to DOVDD TDAIP01, CISDOVDD LDO must remain active. The GPIOs used for LDOs enable are:

- GPIO21 for CISDVDD - GPIO22 for CISDOVDD - GPIO23 for CISAVDD

3.1.1 CISXXX Electrical specifications Table 13. DC Characteristics


CISAVDD Analog supply Voltage for external camera 1.2 - VDD V

ICISAVDD1 Analog DC current of external camera CISAVDD=2.8 V - - 210 mA

CISDOVDD Interface supply Voltage for external camera 1.2 - VDD V

ICISDOVDD1 Interface DC current of external camera CISDOVDD=2.8 V - - 210 mA

CISDVDD Digital supply Voltage for external camera 1.2 - VDD V

ICISDVDD1 Digital DC current of external camera CISDVDD=1.2 V

CISDVDD=1.5 V -

-

210 250 mA

Notes: 1. To determinate maximal DC currents according to the required power supply, see “” section in “3.1.2” on page

21 and section in “3.1.3” on page 21.

TDAIP01



3.1.2 Adjustable operation for CIS DOVDD and CIS AVDD Equation (EQ. 1) illustrates how to compute the shunt resistance value according to the required CISDOVDD and CISAVDD. These supply voltages can be customized from 1.2V to VDD.

( ) ( ) 6.378.0100

3760

−−×=Ω

XXXXXX CIS

kR EQ. 1

Table 14. Recommended Value Output Voltage RXXX

1.2 V 1.5 MΩ

1.8 V 60.4 kΩ

2.5 V 28 kΩ

2.8 V 23.2 kΩ

3.0 V 20.5 kΩ

3.3 V 17.8 kΩ

The maximal current which can be provided by CISDOVDD and CISAVDD is inherent to the desired supply voltage. EQ. 2 depicts how to determinate the maximal authorized current according to the CISXXX voltage supply.

( )XXXCIS

mAI×−

=975.078.3

220max EQ. 2

3.1.3 Adjustable operation for CIS DVDD Equation (EQ. 3) illustrates how to compute the shunt resistance value according to the required CISDVDD. This supply voltage can be customized from 1.25V to VDD.

( ) ( ) 9.27204.147013128

−−×=Ω

DVDDDVDD CIS

kR EQ. 3

Table 15. Recommended Value Output Voltage RXXX

1.25 V OPEN

1.5 V 118 kΩ

1.6 V 82 kΩ

1.8 V 52.3 kΩ

2.8 V 18.2 kΩ

The maximal current which can be provided by CISDVDD is inherent to the desired supply voltage. EQ. 4 depicts how to determinate the maximal authorized current according to the CISDVDD voltage supply.

( )DVDDCIS

mAI×−

=975.078.3550

max EQ. 4

TDAIP01



3.2 DOVDDTDAIP01 power domain

3.2.1 DOVDDTDAIP01 function DOVDDTDAIP01 power domain is available to avoid to use bus transceivers with voltage translation between the TDAIP01 module and the external camera. Based on requirements, DOVDDTDAIP01 can be connected to VDD or to CISDOVDD. Table 16. Interfaces using the DOVDD TDAIP01 power domain


number Signal Name Pin number Signal Name Pin

number Signal Name

3 Y0 10 Y7 18 SCL 60 RXD1

4 Y1 11 Y8 19 SDA 61 CIS_GPIO3

5 Y2 12 Y9 28 STROBE 62 CIS_GPIO4

6 Y3 13 HSYNC 43 CIS_GPIO0 63 CIS_GPIO5

7 Y4 14 PCLK 44 CIS_GPIO1 64 CIS_GPIO6

8 Y5 15 VSYNC 58 CIS_GPIO2 88 BOOT0

9 Y6 16 XCLK 59 TXD1 89 BOOT1

However, the DOVDDTDAIP01 power domain is also used by UART1, BOOT [0:1] and I²C Master, which can be used by other devices. When a voltage level shifter is required, the following references are recommended.

3.2.2 UART1 level shifter The TDAIP01 UART1 uses the DOVDDTDAIP01 power domain interface. If DOVDDTDAIP01 is connected to CISDOVDD and is less than 3.3V, a level shifter must be used if user’s application is using a 3.3V UART interface. The GTL2002D level shifter can be used, for more information please refers to the component datasheet.

Figure 6. UART1 level shift reference circuit

3.2.3 I2C level shifter The TDAIP01 I²C interface uses the same DOVDDTDAIP01 power domain interface too. If DOVDDTDAIP01 is connected to CISDOVDD and is less than 3.3V, a level shifter must be used if user’s application is using a 3.3V I²C interface. The PCA9517 level shifter can be used, for more information please refers to the component datasheet.

TDAIP01



Figure 7. I²C level shift reference circuit

3.2.4 CMOS parallel interface level shifter The TDAIP01 CMOS parallel interface uses the DOVDDTDAIP01 power domain interface. Generally, if the camera DOVDD is less than 3.3V, it is recommended to connect DOVDDTDAIP01 to CISDOVDD. In this case, UART1 and I²C level shifters must be considered. On the other hand, if DOVDDTDAIP01 is connected to 3.3V, a level shifter may be used if the user application is using a camera with a DOVDD lower than 3.3V. The SN74AVCB164245 level shifter can be used, for more information please refer to the component datasheet.

Figure 8. CMOS parallel level shift reference circu it

TDAIP01



4 Recommended design

Note that all schematics examples are only for you reference and are subject to change without notice.

4.1 TDAIP01 Power Supply TDAP01 module is supplied by VDD and DOVDDTDAIP01.

- VDD must be 3.3V +/-10% - DOVDDTDAIP01 must be connected only to VDD or CISDOVDD

The TDAIP01 can drain high currents, thus it is strongly recommended to make power traces (VDD, CISAVDD, CISDVDD) as wide as possible.

Figure 9. Recommended power schematic

Note that if CIS DOVDD is connected to DOVDD TDAIP01, CISDOVDD LDO must remain active. The TDAIP01 module provides three power supplies for an external camera, whose voltage level values can be customized using pull-down resistor. To determinate the resistor value according to the desired voltage supply, see “Supply voltages for external camera” section in “3.1” on page 20. Table 17 provides a non-exhaustive list of recommended power supply configurations according to TD sensor module used. Regardless of the configuration and camera used, DOVDDTDAIP01, RAVDD, RDOVDD and RDVDD must always be mounted. Table 17. Power supply recommended configurations

TD camera

AVDD

(V) DOVDD

(V) DVDD

(V) CISAVDD CISDOVDD CISDVDD Connection of DOVDDTDAIP011 RAVDD RDOVDD RDVDD

TD77402 3.3 3.3 1.5 (internally)

Used Used Not used

VDD 17.8kΩ 17.8kΩ OPEN

TD5640 2.8 2.8 1.6 Used Used Used CISDOVDD 23.2kΩ 23.2kΩ 82kΩ

TDM114 2.8 2.8 1.8 Used Used Used CISDOVDD 23.2kΩ 23.2kΩ 53.2kΩ

Notes:

TDAIP01



1. TDAIP01 AVDD, DOVDD and DVDD are used to supply an external camera 2. TD7740 DVDD is internally regulated. It is recommended to keep the camera’s DVDD not connected

4.2 Camera interface

4.2.1 Internal camera interface If a camera is plugged into the TDAOP01’s DF30RB-30DP-0.4V connector, the camera interface is directly integrated into the module. Nevertheless, the following recommendations apply:

- The camera must use a ‘DF30RB-30DS-0.4V’ connector and follow the defined pinout - The internal power management (CISAVDD, CISDOVDD, CISDVDD) is used to power the camera. Thus, RAVDD,

RDOVDD and RDVDD must be mounted externally

4.2.2 CMOS parallel recommended design In CMOS parallel output mode, it is recommend to use damping resistors in order to reduce ringing, resonance and noise. The resistor value providing the best result depends on the customer’s layout. Nevertheless, 0 to 100Ω is a good starting value range.

Pin name

8-bit External camera

10-bit External camera

DIN0 Low D0

DIN1 Low D1

DIN2 D0 D2

DIN3 D1 D3

DIN4 D2 D4

DIN5 D3 D5

DIN6 D4 D6

DIN7 D5 D7

DIN8 D6 D8

DIN9 D7 D9

Figure 10. Parallel input recommended design

CIS_GPIO[0:7] are dedicated to the camera interface. These GPIO use the DOVDDTDAIP01 power domain. The TDAIP01 has internal pull-up resistors of 1.5kΩ on the I²C interface, connected to the DOVDDTDAIP01 power domain. The STROBE signal is only available if the camera is plugged on the integrated mezzanine connector (cf. 1.5).

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4.2.3 MiPi recommended design Signal traces (MRXDNx and MRXDPx, MRXCN and MRXCP) must be matched with a controlled differential impedance of 100Ω. We recommend to use tuned delay traces like depicted in section 55.2. Ground plane must be placed all around MiPi traces.

Pin

name 1 Lane 2 Lane

MRXDN0 Lane0/N Lane0/N

MRXDP0 Lane0/P Lane0/P

MRXCN Clock/N Clock/N

MRXCP Clock/P Clock/P

MRXDN1 Hi-Z Lane1/N

MRXDP1 Hi-Z Lane1/P

Figure 11. MiPi input recommended design

4.3 Peripheral interfaces

4.3.1 USB Host interface The USBH_VBUS signal can be used to detect an USB device insertion. The detection voltage threshold is between 2.5V and 3.5V (3.3V typ.). If it is not used, USBH_VUS may be left floating. The TDAIP01 does not provide the 5V power supply for USB, an external 5V power is thus required. ESD/EMI components should be fitted to protect the TDAIP01 USBH_xx pins. It is recommended to mount serial resistors on USBH_DP and USBH_DM traces. The resistor value may be changed according to the layout.

Figure 12. USB Host interface recommended circuit

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4.3.2 USB Device interface Like for the USB host interface, ESD/EMI components should be fitted to protect USB TDAIP01 USBD_xx pins. It is recommended to mount serial resistors on USBD_DP and USBD_DM traces. The resistor value may be changed according to the layout. It is possible to use the detection of the USB host insertion, but, the input level on TDAIP01 cannot exceed 3.3V.

Figure 13. USB Device interface recommended circuit

4.3.3 SDCard interface External 3.3V is required, as the TDAIP01 module cannot provide power for the SD card internally. Data lines should be pulled up to 3.3V by 10kΩ resistors, and ESD/EMI components should be fitted as close as possible to the SD card socket, please refer to the following application circuit. Most SDCard sockets feature a normally open ‘NO ‘detection switch that can be used for the SDCard insertion detection as in the following application circuit. For detection, only USR_GPIO [0:7] should be used.

Figure 14. SD card interface recommended circuit

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4.3.4 TV interface As of version 1, the TDAIP1 module firmware does not support TV output.

4.3.5 I2S interface The TDAIP01 module supports an external mono / stereo audio codec, an audio Digital to Analog Converter (DAC) or an audio Analog to Digital Converter (ADC). Note : As of version 1, the TDAIP01 module firmware only supports the WM8960 I2S audio codec.

Figure 15. I 2S interface circuit

4.3.6 SDIO interface

As of version 1, the TDAIP01 module firmware does not support the SDIO interface.

TDAIP01



5 High speed design guidelines

The TDAIP01 module uses several high speed interface signals, up to 800 Mbps: - MiPi signals - CMOS parallel interface signals - USB 2.0 high speed signals

5.1 PCB definition The PCB layout must be correctly designed to allow high speed wires connection while achieving good signal integrity. In fact, when considering high speed signals, PCB traces are not ideal and feature losses, best expressed by an RLCG transmission line model (cf. Figure 16)

Figure 16. RLCG transmission line schematic

The design depends on the PCB stack-up that is used, which influence the RLCG model and thus losses. Before starting any high speed design, the PCB must be defined. A good PCB definition is critical for high speed signals and good reliability. The PCB should be selected according to the following requirements:

- High CAF (Conductive Anodic Filament) resistance PCB is preferable - High glass transition temperature (TG): >160°C (DSC method) - High decomposition temperature (TD): >330°C - Permittivity: < 4.5 @ 1GHz - Loss tangent: <0.02 at 1GHz

A PCB with a minimum number of 4 metal layers is recommended in order to use the internal layers for Power supply and ground plane, like depicted in Figure 17 :

Figure 17. Recommended PCB stack-up

5.2 Controlled impedance of high speed differential traces Following the USB specifications, a 90Ω differential signal trace impedance should be used. Like for MiPi, a 100Ω differential signal trace impedance should be used to comply with the MiPi D-PHY specifications. The PCB layout should keep the signal trace impedance constant whenever possible. When a signal trace on a PCB is long relative to the highest frequency component of the signal, transmission line effects must be taken into account. The transition between when a trace should be modeled as a transmission line is gradual, but common practice is to apply transmission line models when trace length is greater than 10% of the wavelength of

TDAIP01



the highest frequency component on the trace. For traces shorter than this, it is safe to assume that the voltage level is the same over the entire trace. For digital signals, the shortest wavelength is dependent on the signal bandwidth which again depends on the shortest rise and fall times. Faster rise times equals higher frequency content. The following approximation can be used:

rtBW

35.0≈ EQ. 5

Where tr is the minimum rise time from 10-90% It is possible to compute the signal wavelength relative to the substrate permittivity (er~4.5) as follows:

rBW

C

ελ

×≈ EQ. 6

Where: - C is the speed of light (m/s) = 299792458 ≈ 3x108 - εr is the substrate permittivity .

Table 18. High speed signal characteristics

Signal type Rise time Bandwidth Wavelength Maximal Distance before impedance

consideration

USB 4 ns 87.5 MHz 1.7 m 17 cm

MIPI 150 ps 2.33 GHz 6 cm 6 mm

Regarding USB, we can observe that if the traces are shorter than 17 cm, the controlled impedance is not really a bottleneck. However, good design practice is to route USB signals as an impedance matched differential pair according to the specifications. As for MiPi, the signals require strong attention regarding their controlled impedance. A 6 mm distance is sufficient to raise problems if the differential pair is not perfectly matched according to the specifications. The PCB stack-up and characteristics must be considered carefully to layout controlled differential impedance traces. It is recommended to use a differential coplanar waveguide with lower ground topology (cf. Figure 18 ) in order to layout both USB and MiPi interfaces in the best conditions. Table 19 and Table 20 present the recommended trace dimensions relative to the Epoxy thickness between signal and GND plane with εr=4.5 and Loss tangent=0.02.

Figure 18. Differential coplanar waveguide with low er ground plane

TDAIP01



Table 19. 90Ω differential lines characteristic s according to substrate thickness

H (µm)

W (mm)

S (mm)

G (mm)

150 0.21 0.15 0.15

250 0.25 0.12 0.12

350 0.26 0.12 0.12

450 0.27 0.12 0.12

550 0.28 0.12 0.12

1200 0.29 0.12 0.12

1600 0.29 0.12 0.12

Table 20. 100Ω differential lines characteristic s according to substrate thickness

H (µm)

W (mm)

S (mm)

G (mm)

150 0.21 0.21 0.21

250 0.22 0.15 0.15

350 0.25 0.15 0.15

450 0.26 0.15 0.15

550 0.26 0.15 0.15

1200 0.26 0.15 0.15

1600 0.26 0.15 0.15

5.3 Controlled delay of differential wire We recommend tuning delay wiring for differential high speed signals, Data and strobe signal length should be controlled by using meander wiring (cf. Figure 19 ). Trace turning point angle should be greater or equal to 90°. Obtuse angles are recommended. Meander pattern should be placed as close to the module as possible.

Figure 19. Example of tuned delay routing with mean ders

For the MiPi interface, trace length also needs to be matched between the clock lane and the date lanes in order to minimize the data-clock skew.

5.4 Via considerations for high speed signal design

5.4.1 Parasitic Any physical attribute of the board affects the performance of the circuit. It can be seen that a long signal trace will have inductance associated with it, while a pad over an area of ground plane or power plane will have an associated capacitance. An often overlooked PCB parasitic component is the via used to connect one PCB layer to another. Consider a standard PCB through-hole via, as illustrated in Figure 20 .

TDAIP01



Figure 20. PCB Via parasites

Where: - H is the diameter of clearance hole (cm) - D is the pad diameter surrounding the via (cm) - d is the via diameter (cm) - T is the PCB thickness (cm) - εr is the substrate permittivity

The via hole will have an associated parasitic parallel capacitance and inductance, which will form a parallel resonant circuit. As a rule of thumb, these parasitic components can be computed as follows:

Inductance:

+

×××= 14

ln2d

TTL (nH) EQ. 7

Capacitance, DH

DTC r

−×××= ε55.0

(pF) EQ. 8

Typically for a 1.6mm thickness PCB material, a single via can add 1.2nH of inductance and 0.5pF of capacitance, depending upon the via dimensions and PCB dielectric material, although the effects can be minimized by ensuring that

the inter-via spacing is in the order of λ /30. Sometimes the knowledge of the physical properties of the PCB can be used to the advantage of the design engineer. For example, an inductance derived from a PCB trace will offer much greater repeatability than a commercially available component.

5.4.2 Signal reflection When high speed signals are routed from one layer to another, care should also be taken to provide a path for the return signals (cf. Figure 21 ). This rule must be taken into account in order to avoid signal reflections.

TDAIP01



Figure 21. Recommended layout to change layers on P CB

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6 Mechanical Information

6.1 Package Outline

Figure 22. TDAIP01 dimensions

TDAIP01



6.2 Recommended PCB Land Pattern

Figure 23. Recommended Land Pattern Notes :

1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. This land pattern is for reference purpose only. Consult your manufacturing group to ensure your company’s

manufacturing guidelines are met

TDAIP01



7 Production Information’s

7.1 Ordering Information Part number Description Package Type Operating Temperature

TDAIP01-RP-SOFTxxxx 2-Lanes MiPi / 10-bits CMOS Parallel

/ without CIS_xxx and ADJ_xxx supplies power option


TDAIP01-LE-SOFTxxxx 2-Lanes MiPi / 10-bits CMOS Parallel LGA128 Pb-free

-25° to +75°C

TDAIP01-SOFTxxxx 2-Lanes MiPi / 10-bits CMOS Parallel / 8-bits CMOS Parallel Mezzanine connector

LGA128 Pb-free -25° to +75°C

The TDAIP01 module is available in several conditionings. Please contact TDnext for more information.

7.2 Related Products A corresponding TDAIP01 Evaluation Board (EVB) is available.

TD next EVB Part number Ordering Code

TDNx007 TDAIP01-EVB PROD0913

TDAIP01



7.3 Soldering Profile The TDAIP01 module is designed for RoHS reflow process surface mounting. For proper module assembly, the solder paste must be applied on the receiving PCB using a metallic stencil with a recommended 0.150 µm thickness (1).

Figure 24. Recommended reflow soldering profile

Table 21. Reflow soldering profile characteristics 1

Symbol Parameter Conditions Min Typ Max Units

Ramp-up Reflow Ramp-up - - 3 °C/s

Ramp-down Reflow Ramp-down - - 6 °C/s

TS Pre-Heating temperature Solid phase of solder paste 125 - 200 °C

ts Pre-Heating time Solid phase of solder paste 60 - 180 s

TL(2) Phase temperature Liquid phase temperature transition - 217 - °C

tL Reflow time Liquid phase of solder paste 60 - 150 s

Tp Peak temperature - - 255 °C

tp Peak temperature time Close to Tp

Upper at 225°C 20 60

- -

40 90 °C

Notes :

1. This reflow soldering profile is for reference purpose only because it is strongly dependent of process used. Consult your manufacturing group to ensure your company’s manufacturing guidelines are met

2. Liquid phase temperature of SnAgCu solder paste

TDAIP01



7.4 Shipping Packaging

7.5 Product Label

Item Function

1 TD Model

2 Product Description

3 TD PO

4 Manufactured Year and Week

5 / 6 Packed Quantity

7 Customer Name

8 Country Of Origin

9 RoHS Compliant

TDAIP01



DOCUMENT CHANGE L IST

Revision 1.0 First public release

TDAIP01



NOTES

TDAIP01



CONTACT INFORMATION TDnext.

Zone Actipolis II 2 bis rue Nully de Harcourt 33610 CANEJAN, France Tel: +33 5 57 35 63 70 Fax: +33 5 57 35 63 71 Please visit the TDnext web page: http://rfmodules.td-next.com/

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Telecom Design assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Telecom Design assumes no responsibility for the functioning of undescribed features or parameters. Telecom Design reserves the right to make changes without further notice. Telecom Design makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Telecom Design assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Telecom Design products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Telecom Design product could create a situation where personal injury or death may occur. Should Buyer purchase or use Telecom Design products for any such unintended or unauthorized application, Buyer shall indemnify and hold Telecom Design harmless against all claims and damages.

TDnext is a division of Telecom Design S.A. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.

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