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The top documents tagged [nm gate oxide]
® Logic Process Development at Intel PhD Fellowship Forum October 21, 2004 Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration
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1 Sachs et. al. IEEE Trans. Nuclear Science NS-31, 1249 (1984) Threshold Shift vs Gate Oxide Thickness Hole removal process by tunneling in thin-oxide
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Circuit design with a commercial 0.13 m CMOS technology for high energy physics applications K. Hänsler, S. Bonacini, P. Moreira CERN, EP/MIC
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