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The top documents tagged [logic level simulation]
May 14, 2009 1ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani
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Copyright Agrawal, 2009ELEC5270-001/6270-001 Spr 09, Lecture 61 ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Power Analysis and Process
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Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
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Dynamic Power Estimation With Process Variation Modeled as Min–Max Delay
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Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering
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February 6, 2009 Verilog 1 - Fundamentals 6.375 Complex Digital Systems Arvind February 6, 2009 FA module adder( input
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Verilog 1 - Fundamentals
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