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The top documents tagged [hpwl slide]
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks Tan Yan*, Shuting Li Yasuhiro Takashima, Hiroshi Murata The University
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MIP-based Detailed Placer for Mixed-size Circuits Shuai Li, Cheng-Kok Koh ECE, Purdue University {li263, chengkok}@purdue.edu
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Placer Suboptimality Evaluation Using Zero-Change Transformations Andrew B. Kahng Sherief Reda VLSI CAD lab UCSD ECE and CSE Departments
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