T. Hirono, T. Ohata, and T. Kudo JASRI/SPring-8, 1-1-1 Koto, Sayo, Hyogo 678-5198, Japan

Knoxville, TennesseeOctober 15 – 19, 2007

Software on CPU + Simple AI/AOs and DIOs

We adopted three main design concepts. These are (1) flexible I/O selection, (2) real-time and fast control, and (3) sequence reconfigurability.

Flexible I/O SelectionI/O parts physically separated from the base board. They are connected with 64-pin connector

sI/O is simple module such as AI/AO, DIO. Logic of the sequence are on the base board.Data from I/O transferred to the base board and processed there.

Real-time and Fast ControlThe base board is mounted with FPGA (field-programmable gate arrays ) chips

Sequence ReconfigurabilityThe sequence are on a FPGA that is reprogrammable.The logic is modified by the user.

The user can edit VHDL source files and recompile FPGA configuration file.The VME CPU upload the configuration file FPGA to the board

VME-busVME system, because of the existing system in the SPring-8

Two FPGAOne for the user logic and the other for the bus controlThe user’s logic does not includes logic for the VME-bus control.

DDR memory User logic can use the DDR memory as temporary data storageLogic for memory access are in the bus-control FPGA.

→User logic dose not affect to the logic for the memory access.

And also…

○　 Adjustment of sequences (ex. Adding low-pass filter)× 　 Fast control that requires microsecond-order response

Hardware in form of hard-wired circuit (ex. ASIC, Analog circuit)× 　 Adjustments of sequences 　→ A lot of time and cost

○　 Fast control that requires microsecond-order response

○　 Adjustments of sequences○　 Fast control that requires microsecond-order response

I/O Flexible and Logic-reconfigurable Board

We developed…

→ FPGA enables the real-time and fast control

→ Users of this board can select appropriate I/O boards for their own system or develop only I/O module not whole device.

→ The modification of the sequence is quick and easy.

CameraLink(I/O)

DIO(I/O)

AI/AO(I/O)

FPGA

Appropriate I/Os

Fast Feedback System Pattern Driving Image Processing etc.

The board is suite for a control system with complex sequence that requires fast response.

For example,

Base board

User FPGA Xilinx Spartan3 XC3S1500

Number of I/O boards 2

Memory 256 MB DDR memory

Bus VME revision C.3

Development environment Xilinx ISE WebPACK(Windows/Linux)

Application 1Synchronous Data-taking System

Application 2 Feedback System

Screen Monitor

Camera(Camera Link)

User’s ExperimentalSetups

Analog Data

SynchrotronRadiation

I/O board (Camera link grabber)

Number of channels Camera link : 1 chExternal trigger : 1 chNTSC output : 1 ch

Configuration type Base configuration

Supported camera IPX-VGA210-LMCN (Imperx Inc.)

Block Diagram

Detailed Specification

I/O board (DIO)

Number of channels DIO 96 ch

Signal level TTL

We developed a base board and three types of I/O boards, which are AI/AO,DIO and camera link* grabber.

* Communication protocol for video products. http://www.machinevisiononline.org/

We developed a flexible and logic-reconfigurable VME board in cooperation with ARKUS Inc*. All the design concepts were implemented.

* http://www.arkus.co.jp/index.html

The system will be installed with a new screen monitor in March 2008.

DIO

Camera Link

User FPGA

Bus-control FPGA

A system for a new screen monitor that transmits SR beam capture the beam image during user’s experiment. (cf. The existing monitor stops the beam)

A replacement system for the existing monochromator stabilizer (MOSTAB) of a beamline of the SPring-8

Base Board with Logic of Image Processing

The required system is built with

AI/AO Board and Camera Link Grabber Board

andBase Board with Logic of PID Feedback

The required system is built with

AI/AO Board *

and

* We tested the feedback system with PWM output instead of analog output. The test was possible because of the flexibility of the boardWe JUST added PWM-convert logic and a DIO board.

I/O board (AI/AO)

Number of channels AD: 8 ch, DA: 8 ch

Bit resolution 16 bits

Sampling rate 200 kHz

AI/AO(I/O)

FPGA

CameraLink(I/O)

VMEBus

UserFPGA

FPGAfor

I/O control

LocalBus

FPGAfor

VME controlVME Bus

Connector

Connectors

AI/AOConnector

Flash ROM

DDR Memory

Isolator

A/D

D/A

Base Board

I/O Board (AI/AO) Configurator

Configuration Data

DDR Interface

Buffer

VMECPU

Outside of the board

Image Data

Author's e-mail address : hirono@spring8.or.jp

VME system

We designed and developed a new VME board that is characterized by flexible I/O selection, real-time and fast control, and sequence reconfigurability.

e

The board is/will be applied to control systems with complex sequence and fast response. No hardware change was required to applied to the systems.

640 x 480 pixels12bits/pix200fps

8 channelSynchronized w/ camera

→ Position of the monochromator (an analog input) is feedbacked to stabilize a signal from detector (an analog outputs) that monitors the beam intensity. The sequence is a PID feedback sequence with 10 Hz response.

→The information about beam , such as beam position and relative intensity, and the data from experiment setups are collected same time.