systemverilog_07 [verification] threads and interprocess communication {v05!01!2013}

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8/13/2019 SystemVerilog_07 [Verification] Threads and Interprocess Communication {v05!01!2013}

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Threads and Inter

-

Process Communication

Verilog Divisor

Example implementation

–

Module Declaration

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////////////////////////////////////////////////////////////// // William L. Bahn// // FILE: division32.v // // DESCRIPTION: This module divides one integer by another// producing an integer quotient and integer remainder.// It works with 32-bit unsigned integers.//////////////////////////////////////////////////////////////

module division32 ( input wire [ 31 : 0 ] dividend,input wire [ 31 : 0 ] divisor ,output reg [ 31 : 0 ] quotient ,output reg [ 31 : 0 ] modulus ,input wire go ,output reg done,input wire clk , rst );

parameter S_LO = 1 'd 0 , S_HI = 1'd1 ;reg state, next_state;reg [ 31:0 ] q, next_q ; // Working Quotientreg [ 31:0 ] t, next_t ; // Working Term reg [ 62:0 ] r, next_r ; // Working Remainder reg [ 62:0 ] p, next_p ; // Working Productreg [ 31:0 ] next_quotient, next_modulus ;reg next_done;

parameter S_IDLE = 1'd0,S_RUN = 1'd1;

I N P U T -

O U T P U T

MEMORY

CONTROL

DATAPATH

http://www.dragonwins.com/domains/getteched/de248/binary_division.htm

Advanced Hardware Design & VerificationSystemVerilog [Verification]





Threads and Inter

-


Verilog Divisor


-

Memory

//--------------------------------------------------------// FSM Registers//--------------------------------------------------------always @(posedge clk or posedge rst ) begin

if ( rst ) beginq <= 32 'd 0;r <= 63 'd 0;p <= 63'd0;

t <= 32'd0;quotient <= 32'd0;modulus <= 32'd0;done <= HI ;state <= S_IDLE ;

end else begin

q <= next_q;r <= next_r;p <= next_p;

t <= next_t;quotient <= next_quotient;modulus <= next_modulus;done <= next_done;state <= next_state ;

end end

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I N P U T -

O U T P U T

MEMORY

CONTROL

DATAPATH







Threads and Inter

-


Verilog Divisor


–

Control and Data

-

Path

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always @* // FSM Next State Logic begin

case( state)S_IDLE : begin

next_t = 32 'h 80000000 ; // t = 2^31next_p = { divisor,31'd0 }; // p = divisor*2^31next_q = 32'd0; // q = 0next_r = { 31'd0, dividend }; // r = dividend next_quotient = quotient;nex t_ modu lus = modu lus ;if ( go ) begin

next_done = LO;next_state = S_RUN ;

end else beginnex t_ do ne = do ne;nex t_ st at e = S_IDLE ;

end end S_RUN: begin

next_t = { LO,t[31:1 ]}; // t = t/2 next_p = { LO,p[62:1 ]}; // p = p/2 if ( p <= r ) begin

next_q = q + t;n ex t_ r = r - p ;

end else begin

next_q = q;

next_r = r ;end if ( t[0 ]) begin // Term == 1

next_quotient = q + ((p <= r)? t:0);next_modulus = r - ( (p <= r)? p:0);next_done = HI;next_state = S_IDLE ;

end else begin

next_quotient = quotient;next_modulus = modulus;next_done = done;next_state = S_RUN;

end end

endcaseend endmodule

I N P U T -

O U T P U T

MEMORY

CONTROL

DATAPATH







Threads and Inter

-


Verilog Divisor

program

and

testbench

task compute_div_task ( input integer a ,input integer b ,output integer q ,output integer r );begin

q = 0 ;r = 0 ; //for i = n-1...0 do where n is number of bits

for (int i = 31 ; i >= 0 ; i --) begin@(posedge clk ); // Clock 1r = r << 1 ; // R := R << 1 left-shift R by 1 bit@(posedge clk ); // Clock 2 r = r + a [ i ]; // R(0) := A(i)if ( r >= b ) begin // if R >= B then

@(posedge clk ); // Clock 4r = r – b ; // R = R - B q [ i ] = 1 ; // Q(i) := 1

end end

end endtask : compute_div_task

program test_pi_machine (input wire clk , reset_n );integer a, b, r_gold, q_gold, r_dut, q_dut ;

divisioni_dut (. clk ( clk ), // I Clock

. rst ( rst) ), // I Reset

.dividend ( a ), // I [31:00]

. divisor ( b ), // I [31:00]

. quotient (q_dut ), // O [31:00]

. modulus ( r_dut ), // O [31:00]

. go ( go ), // I

. done ( done )); // O

initial beginfor (int j = 0 ; j < 8; j = j + 1 ) begin

a = $random( );

b = $random( );@(poesedge clk ) go = 1 ;@(poesedge clk ) go = 0 ;compute_div_task ( a , b , q , r );while( done ) (poesedge clk );if ( q_gold != q_dut )

$display(“Error: Result was incorrect”);else if ( r_gold != r_dut )

$display(“Error: Remainder was incorrect”);end

end endprogram;

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Threads and Inter - Process Communication

ThreadsSpawning Threads

---------------

---------------

---------------

fork

join [all] join_any

---------------

---------------

---------------

fork

join_none

---------------

---------------

---------------

fork

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join_any


Threadsfork / join_any

---------------

---------------

---------------

fork initialbegin

clk = 0 ;# 5fork

# 5 a = 0 ;# 10 b = 0 ;

join_any

clk = 1 ;end

clk becomes 1 at t = 10

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Threadsfork / join_none

initialbegin

clk = 0 ;# 5fork

# 5 a = 0 ;# 10 b = 0 ;

join_none

clk = 1 ;end

clk becomes 1 at $time = 5join_none

---------------

---------------

---------------

fork

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ThreadsSpawning function s/ task s


q = 0 ;

r = 0 ;//for i = n-1...0 do where n is number of bitsfor (int i = 31 ; i >= 0 ; i --) begin

@(posedge clk ); // Clock 1r = r << 1 ; // R := R << 1 left-shift R by 1 bit@(posedge clk ); // Clock 2 r = r + a [ i ]; // R(0) := A(i)if ( r >= b ) begin // if R >= B then


end end


...

...initial begin

for (int j = 0 ; j < NUM_DIV; j = j + 1 ) beginfork

begin

@(poesedge clk ) go [ i ] = 1 ;a [ j ] = $random( );b [ j ] = $random( );compute_div ( a [ j ], b [ j ], q [ j ], r [j]);while(~ done [ i ]) @(poesedge clk );...

end join_none ;

end endprogram;

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W hat’s the problem here? What happenswhen multiple processes are in the sametask at the same time?





a b

i_dut[NUM_DIV-1]

a b

i_dut[0]

a b

i_dut[1] i_dut[NUM_DIV-2]

a b

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...genvar i;generate

for (int i = 0 ; i < NUM_DIV; i = i + 1 )my_div_implementation

i_dut (.clk ( clk ),.reset_n ( reset_n ) ,.a ( a[i] ),.b ( b[i] ));

endgenerate...initial begin

for (int j = 0 ; j < NUM_DIV; j = j + 1 ) beginfork

begin@(poesedge clk ) go [ i ] = 1 ;a [ j ] = $random( );b [ j ] = $random( );compute_div ( a [ j ], b [ j ], q [ j ], r [j]);while(~ done [ i ]) @(poesedge clk );...

end join_none ;

end endprogram;

compute_div_tasks

a b q r

d d d fl [ f ]




q = 0 ;r = 0 ;//for i = n-1...0 do where n is number of bitsfor (int i = 31 ; i >= 0 ; i --) begin



end end



ThreadsLocal Variables in Threads

join_none

fork

I t turns out that each instance of the function calldoesn’t get it’s on variables. They are really just atdifferent places in the same task.

2 nd Thread

I f we stop the simulator after threeclock cycles, we would see the following:

3 rd Thread

1 st

Thread

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Ad d H d D i & V ifi iS V il [V ifi i ]







end end end

endtask : compute_div_task



c o

m p u t e _ d

i v

( 7 ,

3 )

1 st Thread

@(posedge clk ); // Clock 1

r = r << 1 ; // R := R << 1 left-shift R by 1 bit

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a b q

7 3 0

r

0

Ad d H d D i & V ifi iS V il [V ifi i ]







end end end




c o

m p u t e _ d

i v

( 7 ,

3 )

1 st Thread

c o

m p u t e _ d

i v

( 4

,

2 )

2 nd Thread

@(posedge clk ); // Clock 1r = r << 1 ; // R := R << 1 left-shift R by 1 bit


r = r + a [ i ]; // R(0) := A(i)

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a b q

4 2 0

r

2

Ad d H d D ig & V ifi tiS t V il g [V ifi ti ]







end end end




c o

m p u t e _ d

i v

( 7 ,

3 )

1 st Thread

c o

m p u t e _ d

i v

( 4

,

2 )

2 nd Thread

c o

m p u t e _ d

i v

( 6 ,

3 )

@(posedge clk ); // Clock 2 r <= r + a [ i ]; // R(0) := A(i)

3 nd Thread


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a b q

6 3 0

r

4


tmp <= r – b; // negative check


r = r << 1 ; // R := R << 1 left-shift R by 1 bit





Threadslocal copy of specific variables: a utomatic

Data declared in an automatic task, function, or block have the lifetime ofthe call or activation and a local scope. This is roughly equivalent to a Cautomatic variable. [SVLRM]

W hat’s the problem here? What if we want to expand this concept to a taskbut don’t want to explicitly call ALL variables automatic (gets to be a pain)?

initial

for(int j = 1 ; j <= 3 ; ++ j )fork

automatic int k = j ; // local copy, k, for each value of j# k $write(" %0d", k );

beginautomatic int m = j ; // the value of m is undetermined ...

end join_none


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task automatic compute_div_task ( input integer a ,input integer b ,output integer q ,output integer r );begin

q = 0 ;r = 0 ;

//for i = n-1...0 do where n is number of bitsfor (int i = 31 ; i >= 0 ; i --) begin@(posedge clk ); // Clock 1r = r << 1 ; // R := R << 1 left-shift R by 1 bit@(posedge clk ); // Clock 2 r = r + a [ i ]; // R(0) := A(i)if ( r >= b ) begin // if R >= B then


end end



Threadslocal copy of all variables : automatic

task_declaration ::= task [ lifetime ]

SystemVerilog adds an optional qualifierto specify the default lifetime of allvariables declared in a task, function, orblock defined within a module, interface,or program (see Clause 16). The lifetimequalifier is automatic or static . Thedefault lifetime is static . [SVLRM]

Verilog allows tasks to be declared as automatic so that allformal arguments and local variables are stored on the stack.SystemVerilog extends this capability by allowing specificformal arguments and local variables to be declared as automatic

within a static task or by declaring specific formal argumentsand local variables as static within an automatic task. [SVLRM]

lifetime ::= static | automaticdefault lifetime is static


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a b

i_dut[NUM_DIV-1]

a b

i_dut[0]

a b

i_dut[1] i_dut[NUM_DIV-2]

a b


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compute_div_tasks

a b q r

compute_div_tasks

a b q r

compute_div_tasks

a b q r

compute_div_tasks

a b q r ...

genvar i;

generatefor (int i = 0 ; i < NUM_DIV; i = i + 1 )my_div_implementation

i_dut (.clk ( clk ),.reset_n ( reset_n ) ,.a ( a[i] ),.b ( b[i] ));

endgenerate...initial begin

for (int j = 0 ; j < NUM_DIV; j = j + 1 ) beginforkbegin

@(poesedge clk ) go [ i ] = 1 ;a [ j ] = $random( );b [ j ] = $random( );compute_div ( a [ j ], b [ j ], q [ j ], r [ j ]);while(~ done [ i ]) @(poesedge clk );...

end

join_none ;end endprogram;4





Multiple Tasks accessing the same DUT

a b

i_dut


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compute_div_tasks

a b q r

compute_div_tasks

a b q r

compute_div_tasks

a b q r

compute_div_tasks

a b q r

...my_div_implementation

i_dut (. clk ( clk ),.reset_n ( reset_n ) ,.a ( a ),.b ( b ));

...initial begin

for (int j = 0 ; j < NUM_TESTS; j = j + 1 ) begin

forkbegin@(poesedge clk ) go = 1 ;a = $random( );b = $random( );compute_div ( a , b , q , r );while(~ done ) @(poesedge clk );...

end join_none ;

end endprogram;





semaphoreOverview

smTx = new( 1 );

W e like to visualize a semaphore as a bucket.

semaphore smTx ;

O nce allocated, that bucket will contain one or more keys.


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semaphoreBasic utility functions to use semaphores

T o take a semaphore from the bucket : get()

P lace the semaphore in the bucket: put()

L ook into the bucket to see if there is a semaphore available: try_get ()


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semaphoreUpdated compute_div task


task automatic compute_div_task ( input integer a , input integer b ,output integer q , output integer r );begin

smTx .get( )q = 0 ;r = 0 ;//for i = n-1...0 do where n is number of bitsfor (int i = 31 ; i >= 0 ; i --) begin



end end

smTx .put( )end


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eventOverview

event done; // declare a new event called doneevent done_too = done ; // declare done_too as alias to doneevent empty = null ; // event variable with no synchronization object

SystemVerilog events

I f the event is assigned null, the event becomes non-blocking, as if it were permanently triggered.

event variable_name [= initial_value];

p rovides a handle to a synchronization object.

h ave a persistent triggered state that lasts for the duration of the entire time step.

c an be assigned another event variable or the special value null

c an be passed as arguments to tasks.

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event e1 , e2 ;

initial : run_first ;begin

$display(“ run_first: before event1 triggered ”);-> e1 ; // trigger event 1

@e2 ; // start waiting for e2 to be triggered $display(“ run_first: after event1 triggered ”);end

initial : run_second ;begin

$ display(“ run_second: before event2 triggered ”);-> e2 ; // trigger event 2 @e1 ; // start waiting for event 1

$display(“ run_second: after event2 triggered ”)end

event_trigger ::= - > hierarchical_event_identifier ; |- >> [ delay_or_event_control ] hierarchical_event_identifier ;

Threads and Inter-Process Communication

eventTriggering of Events ( - > or - >> )

N amed events are triggered via the - > operator.

N on-Blocking events are triggered via the - >> operator.T he big change over Verilog events is that SystemVerilog events can remain visible for a specified duration.

U pon triggering an event, all other processes waiting on that event becomeunblocked.

run_first: before event1 triggeredrun_second: before event2 triggered

run_first: after event1 [email protected]

gy g [ ]

W e are blocking until event e2 is triggered.

W e miss event e1 . How can we fix this?

A fter triggering e1 , run_first blocks and does not execute any further





eventnon - blocking after triggering of an event ( - >> )

event e1 , e2 ;

task run_first ;$display(“ run_first: before event1 triggered ”);->> e1 ; // trigger event 1@e2 ; // start waiting for e2 to be 1$display(“ run_first: after event1 triggered ”);

endtask : run_first

task run_second ;$display(“ run_second: before event2 triggered ”);

->> e2 ; // trigger event 2 @e1 ; // start waiting for e1 to be 1$display(“ run_second: after event2 triggered ”)

endtask : run_second

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gy g [ ]

run_first: before event1 triggeredrun_second: before event2 triggered

run_first: after event1 triggeredrun_second: after event2 triggered

E vents e1 and e2 will be updated in the non-blocking region of the scheduler.

event_trigger ::= - > hierarchical_event_identifier ; |- >> [ delay_or_event_control ] hierarchical_event_identifier ;

N amed events are triggered via the - > operator.

N on-Blocking events are triggered via the - >> operator.





eventVariable Declaration ( event )

T he event data type is an enhancement over Verilog named events.SystemVerilog events provide a handle to a synchronization object.

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gy g

class Driver ;event input_sent ;event output_taken ;

//==================================== // Constructor //==================================== function new (event _input_sent ,

_output_taken );this. input_sent = _input_sent ;this. output_taken = _output_taken ;

endfunction

task start ( );while(1);

sendInput ( );-> input_sent ;@output_taken;

end

endtask : startendclass : Driver

class Reciever ;event input_sent ;event output_taken ;

//=================================== // Constructor //=================================== function new (event _input_sent ,

_output_taken );this. input_sent = _input_sent ;this. output_taken = _output_taken ;

endfunction

task start ( );while( 1 ) begin

@input_sent;takeOutput ( );-> output_taken ;

end

endtask : startendclass : Receiver

T he general idea is to create a synchronizationmechanism that can be passed to other tasks.





eventWaiting on the level of the event

event e1 , e2 ;

task run_first ;$display(“ run_first: before event1 triggered ”);-> e1 ; // trigger event 1wait ( e2 .triggered); // start waiting for e2 to be 1$display(“ run_first: after event1 triggered ”);

endtask : run_first

task run_second ;$display(“ run_second: before event2 triggered ”);

-> e2 ; // trigger event 2 wait ( e1. triggered); // start waiting for e1 to be 1$display(“ run_second: after event2 triggered ”)

endtask : run_second

run_first: before event1 triggeredrun_second: before event2 triggeredrun_first: after event1 triggeredrun_second: after event2 triggered

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T his now looking at the state of the event, i.e. it is level triggered.





eventevent Synchronization Utilities

$wait_order( event_identifier { , event_identifier } )

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T he $ wait_order system task suspends the calling process until all of the specified events are triggered(similar to $ wait_all ), but the events must be triggered in the given order (left to right). If an event isreceived out of order, the process unblocks and generates a run-time error.

$wait_any( event_identifier { , event_identifier } )

T he $ wait_any system tasks suspends the calling process until any of the specified events are triggered

$wait_order ( a, b, c);

$wait_any ( a, b, c); suspends the current process until either event a, or event b, or event c is triggered.

suspends the current process until events trigger in the order a b c.

$wait_all( event_identifier { , event_identifier } )

T he $ wait_all system tasks suspends the calling process until all of the specified events are triggered.

$wait_all ( a, b, c); suspends the current process until the 3 events a, b, and c are triggered.





mailbox

• I nter-Process-Communication (Mailboxes) • H ow the can be used in the verification environment • E xamples • B ounded vs. Un-Bounded Mailboxes

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31


mailboxMailboxes as a Software Concept

I n software, we use a message passing system to allow processes to communicate with each other withoutneeding to resort to using some sort of shared data. For example, we could have two processes P and Q,who would like to send messages to each other. They do so, using a communication link as illustratedbelow:

T here are several mechanisms that this communication link can use for sending and receiving data between the processes.

- D irect Communication - Must Explicitly name the recipient - Indirect Communication - messages are sent to mailboxes or ports

- S ymmetric Communication - Both Sender and Receiver must name each other to communicate - Asymmetric Communication - Only the sender names the recipient

- Automatic Buffering – The link has potentially an infinite number of outstanding or un-read communiqué's (default) - E xplicit Buffering - The queue has a finite length, it can be zero or more. But it is fixed.

- Send by Copy – Send a complete copy of the data to the recipient - S end by Reference – Send a pointer or handle to the recipient

- F ixed Size Messages – The message can only be a predefined number of bytes or structure.- Variable Size Messages – The message can be of varying length (default) [email protected]





mailboxHow to use them in Verification Environment

receiver(s)receiver(s)receiver(s)

Scoreboard

Device U nder T est

receiver(s)

Generator &Driver

MailboxMailbox

reset()cfg_dut()

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mailboxExamples

M ailbox is a built-in class that provides the following methods:

C reate a mailbox: new()

P lace a message in a mailbox: put()

W hat happens when our mailbox is full?

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mailboxExamples

M ailbox is a built-in class that provides the following methods:

T o look at a message in the mailbox without taking it out: peek()

T o take a message from the mailbox : get()

W hat happens when our mailbox is empty?

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mailboxHow does it work when I ...?

• T ry to place a message in a mailbox without blocking: try_put ()• T ry to retrieve a message from a mailbox without blocking: try_get () or try_peek ()• R etrieve the number of messages in the mailbox: num()

Question: Whathappens when ourmailbox is empty andwe try to get or peek ?

Question: What happenswhen our mailbox is full andwe try to put ?

Answer: We stand aroundwaiting for a the mailbox tobecome a little less full orhave at least one message.

Note: When a process is waiting onsome event to occur, it is blocked, i.e.no other statements in that processwill be executed until the last callbecomes “un - blocked”.

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mailbox( Put’in and Get’in in a UnBounded World)

get ( ) put ( )

• M ust use a variable in argument list to receive data.• I f the mailbox is empty, the process will wait until amessage gets put in the mailbox.• Y ou must use the correct data-type when put ’ing message into the mailbox, or your simulation will die.

class Transmitter; mailbox #(int) mb;

function new ();mb = new( ); // Unbounded Mail-Box

endfunction

task run ;for (int i = 0 ; i < 20 ; i ++)

mb.put( i );endtask

endclass

class Reciever; mailbox #(int) mb;

function new ();mb = new( ); // Unbounded Mail-Box

endfunction

task run ;int i = 0 ;begin

while( 1 ) beginmb.get(i);$display(“ Item %i ”, i );i ++ ;

end end

endtask endclass

• A mailbox is a Queue, i.e. the first item in is the firstitem out.•

I f a bounded mailbox has been specified, the processwaits until there is sufficient room such that themessage can be placed onto the Queue.

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mailboxUn - Bounded Example

module tb_mailbox ;// kick off the test.mailbox_test test ( );

endmodule

class Receiver; mailbox mb;

int rx_val ;

function new (mailbox mb);this. mb = mb;

endfunction

task run;for(int i = 0 ; i < 20 ; i ++) begin

mb.get( rx_val );$display(" rx val = %d ", rx_val );

end

endtask endclass

class Transmitter; mailbox mb;

function new (mailbox mb);this. mb = mb;

endfunction


mb.put( i );endtask

endclass

program mailbox_test ( ); mailbox mb; // mailbox used for communication.

Transmitter t1; // Transmitter.Receiver r1; // Receiver.

initialbegin

mb = new ( ); // Create new objects.t1 = new(mb );r1 = new(mb );fork // Fork off the processes.

t1.run ();r1.run ();

joinend

endprogram

Reminder: O bjects are passed byreference, e.g. a mailbox is an object.

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Th d d I P C i i




Threads and Inter-Process Communication

mailbox( Put’in and Get’in in a Bounded World)

t ry_get ( ) try_put ( )

• R eturns 1 if the mailbox is not empty and the messagetype matches the type of the message variable.• R eturns 0 if the mailbox is empty • R eturns -1 if the variable type specified does not match(and a message is available)

class Receiver; mailbox #(int) mb;

function new ();mb = new( 10 ); // Unbounded Mail-Box

endfunction

task run ;int i ;begin

while( 1 ) beginwhile(~mb.try_get( i )) # 10 ;$display(“ Item %i ”, i );

end end

endtask endclass : Reciever

class Transmitter; mailbox #(int) mb;

function new ();mb = new( 10 ); // Bounded Mail-Box

endfunction


while ( mb.try_put( i ) !== 0 );endtask

endclass : Transmitter

• I f the mailbox is not full, the message is placed onthe queue and the method returns a 1 (for true) •

I f the mailbox is full, the method returns a 0

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Th d d I

P

C i i





A complete Example ( and gate)The big picture

D river Receiver

S ignal C ommand

S ignal C ommand

F unctional F unctional S coreboard

AND

bit [ ] data ;

PacketIn (int Number of Inputs)

function new (bit [ ] data );function void display ( );function bit [ ] pack ( );function void unpack (input [] data );

bit c;

PacketOut

function new (bit _c );function void display ( );function bit pack ( );function void unpack (input bit data );

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Th d d I

P

C i i





A complete Example ( and gate)test.sv – PacketIn class

class PacketIn #(parameter number_of_inputs = 2);bit [ number_of_inputs ] data;//================================================================================ // new( ) – Objects Allocated and Initialized via call to the new// Constructor Method. Set the fields to values passed from argument default = 0.//================================================================================ function new (bit [ number_of_inputs ] _data = 0 );

this. data = _data;endfunction

//================================================================================ // display( ) - Display the contents of the packet in a formatted way.//================================================================================ function void display ( );

endfunction : display

//================================================================================ // pack the contents into a frame of 2bits.//================================================================================ function bit [ number_of_inputs ] pack ( );

pack = data ;endfunction

//================================================================================ // unpack the contents of a frame into a given Packet.//================================================================================ function void unpack (input bit [number_of_inputs] _data);

this. data = _data;endfunction : unpack

endclass : PacketIn

bit [ ] data ;

PacketIn (int Number of Inputs)

function new (bit [ ] data );

function void display ( );function bit [ ] pack ( );function void unpack (input [] data );

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Th d d I t

P

C i ti





A complete Example ( and gate)class.sv – Driver class

class Driver ;//========================================== // Attributes//========================================== virtual and_if.IN INif ;// Packet to be writtenPacketIn #( 2 ) sentPkt ;// mailbox handle

mailbox #( PacketIn #( 2 )) driver_mb ;

//========================================== // Constructor //========================================== function new (virtual and_if.IN _INif ,

mailbox #( PacketIn #( 2 )) _driver_mb );$display(" %t [Driver] new( ) ", $time);this. INif = _INif ;this. driver_mb = _driver_mb ;

endfunctiontask write ( );

sentPkt = new($random( ));$display(" %t [Driver] write(%b) ", $time, sentPkt.data );// Apply the randomly generated packet to the interfacethis. INif.in = sentPkt.pack ( );// Send a copy of the packet, just sent, to the score-board this. driver_mb .put( sentPkt );# 10 ;

endtask : writeendclass : Driver

D river

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A complete Example ( and gate)class.sv – PacketOut class

class PacketOut ;bit c ;//================================================================================ // new( ) – Objects Allocated and Initialized via call to the new// Constructor Method. Set the fields to values passed from argument default = 0.//================================================================================ function new (bit _c = 1 'b 0 );

this. c = _c ;endfunction

//=============================================================================== // display the contents of the packet in a formatted way.//=============================================================================== function void display ( );

$display("C[%b]", c);endfunction : display

//=============================================================================== // pack the contents into a frame of 2bits.//============================================================================= function bit pack ( );

pack = this. c ;endfunction : pack

//=============================================================================== // unpack the contents of a frame into a given Packet.//=============================================================================== function void unpack (input bit data );

this.c = data ;endfunction : unpack

endclass : PacketOut

bit c ;

PacketOut

function new (bit _c );function void display ( );

function bit [ ] pack ( );function void unpack (input bit data );

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A complete Example ( and gate)class.sv – Receiver class

class Receiver ;// Interfacesvirtual and_if.OUT OUTif ;PacketOut rcvdPkt ;// mailbox handle

mailbox #( PacketOut ) receiver_mb ;

function new (virtual and_if.OUT _OUTif , mailbox #( PacketOut ) _receiver_mb );$display(" %t [Receiver] new( ) ", $time);this. OUTif = _OUTif ;this. receiver_mb = _receiver_mb ;

endfunction

task read ( );// Create a new packet that will be filled with the results from the

// device under testrcvdPkt = new ( );// Take the data from the output interface of the device under test$display(" %t [Receiver] read(%b) ", $time, this.OUTif.out );rcvdPkt .unpack( this.OUTif.out );// Push the packet to the Scoreboard's receiver mailbox this. receiver_mb .put( rcvdPkt );# 10 ;

endtask : readendclass : Receiver

Receiver

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A complete Example ( and gate)class.sv – Scoreboard class

class ScoreBoard ;//===================================================================== // mailbox instantiations//====================================================================

mailbox #( PacketIn #( 2 )) driver_mb ; mailbox #( PacketOut ) receiver_mb ;

PacketOut rcvdPkt ;PacketIn #( 2 ) sentPkt ;

function new (mailbox #( PacketIn #( 2 )) _driver_mb , mailbox #( PacketOut ) _receiver_mb );this. driver_mb = _driver_mb ;this. receiver_mb = _receiver_mb ;

endfunction : new

//===================================================================== // Start Monitoring the receiver and driver mailboxes and then compare//===================================================================== task start ( );

while( 1 ) beginthis. driver_mb .get( sentPkt );this.receiver_mb.get( rcvdPkt );# 5 ;

if ((& sentPkt . pack ( )) != rcvdPkt.pack ( ))$display(" Scoreboard: Packet Failed ");

else$display(" Scoreboard: Packet Passed" );

end endtask

endclass : ScoreBoard

F unctional F unctional S coreboard

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A complete Example ( and gate)class.sv – Environment class

class Environment;// Mailbox Instantiation

mailbox #( PacketIn #(2)) driver_mb ; mailbox #( PacketOut ) receiver_mb ;

virtual and_if.IN INif ;virtual and_if.OUT OUTif ;

// Testbench components handlesReceiver receiver_cl ;Driver driver_cl ;ScoreBoard scoreboard_cl ;

//================================================= // constructor - to assign virtual interfaces//================================================= function new (virtual and_if.IN _INif ,

virtual and_if.OUT _OUTif );this. INif = _INif ;this. OUTif = _OUTif ;

endfunction//================================================= // Instantiate the Driver, Receiver, Scoreboard // and the 2 mailboxes.//================================================= task build ( ); // Create the driver and receiver mailbox

driver_mb = new ( );receiver_mb = new ( );receiver_cl = new (this. OUTif , this. receiver_mb );driver_cl = new (this. INif , this. driver_mb );scoreboard_cl = new (this. driver_mb , this. receiver_mb );

endtask : build

//==================================================== // Reset the DUT by driving all input signals low// for 10 clocks and de-assert reset signal.//==================================================== task reset ( );

this. INif.in = 0;endtask : reset

//==========================================

// Start the Scoreboard.//========================================== task start ( );

scoreboard_cl . start ( );endtask

//================================================= // Run//================================================= task run (input integer NUM_OF_TESTS = 10 );

this. build ( );this. reset ( );fork this. start ( );

for (int i = 0 ; i < NUM_OF_TESTS ; i = i ++) begindriver_cl.write ( );receiver_cl.read ( );

end join_any

endtask endclass : Environment

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A complete Example ( and gate)test.sv and interface.sv

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program automatic test ( and_if.IN _INif , and_if.OUT _OUTif );Environment env;

initialbegin

env = new( _INif , _OUTif );

env . run ( 20 );$finish;end

endprogram : test interface and_if #( NUM_INPUTS = 2 );logic [ NUM_INPUTS - 1 : 0 ] in ;wire out ;

modport IN (output in ); modport OUT (input out );

endinterface

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A complete Example ( and gate)tb_top.sv

module tb_top ( );// Testbench parameters assets

parameter NUM_OF_INPUTS_FOR_AND_GATE = 2 ;

//=========================================================== // We instantiate the and_if interface without clock (why?)//=========================================================== and_if #( 2 ) AndIfInst ( );

//============================================================// This is our test that creates all of the objects necessary// for driving and receiving data from our DUT.//============================================================ test i_test ( AndIfInst.IN , AndIfInst.OUT );

//============================================================ // Module being tested //============================================================ my_and #( NUM_OF_INPUTS_FOR_AND_GATE )

i_dut (.a( AndIfInst.IN.in ),.c( AndIfInst.OUT.out ));

systemverilog_07 [verification] threads and interprocess communication {v05!01!2013}

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