System VerilogTestbench Language

David W. SmithSynopsys Scientist

Synopsys, Inc.

5 December 2003 David W. Smith

External Memory

Serial Ports

Parallel Ports

Bluetoothcontroller

RS232 model

1284model

Bluetooth model

IR devicemodel

10GbEthernet

CPUCore

PCIController

MemoryController

Testbench

ControlLogic

PCI Model

EthernetMAC

EthernetMAC

EthernetMAC

1GbEthernet

10/100MEthernet

Proprietary Bus Controller

Infraredcontroller

Proprietarymodel

USBUSB model

Sample SOC and Testbench

Protocol Checkersfor Interface

DUT

SynchronousInterface Boundaries

AHB APB

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System with Multiple SOC’s

• At System Level Problem is Exacerbated• Abstractions and Re-use are Necessary!

Packet Switched Bus

SOC 1DUT

FPUFPU

CacheCache

MemMem

CPUCPU

AMBAAMBA

SOC 2 SOC 3

FPUFPU

CacheCache

MemMem

CPUCPU

AMBAAMBA

FPUFPU

CacheCache

MemMem

CPUCPU

AMBAAMBA

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Testbench Requirements • Stimulus Generation

• Directed, Random, ATPG, ...• Checkers

• Data• Protocols

• Structured Connection to Multiple Independent Interfaces• Interconnect• Clocking Domain• Protocol

• Abstract Modeling• High-level data structures• Dynamic Memory

> Memory Management• Re-entrant Processes

> Inter-process Synchronization, Control, and Communication• Re-usability

• Single language for design (HDL) and verification (HVL) HDVL

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Basic Types• Strings

• arbitrary and dynamic length• methods to manipulate and convert strings• operators for comparison, concatenation and replication

• Associative arrays• Indexed by integer, string, or class• first(index), last(index), next(index), prev(index), delete(index), and

exist(index) methods• Dynamic arrays

• integer mem[*];• mem.size();

• Linked Lists• doubly linked list of any data type• iterator, modification, access methods

• Classes, Objects and Methods• Object Oriented

> Encapsulation, Inheritance, and Polymorphism• Objects referenced with handles (Safe Pointers)

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Random Variables and Constraints

Design

ConstraintsConstraints

Test Scenarios

ConstraintsConstraints

Input SpaceInput Space

ValidValid

Constraint Solver

• Find solutions

Constraint Solver

• Find solutions

• Valid Inputs Specified as Constraints

• Declarative

• Valid Inputs Specified as Constraints

• Declarative

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Random Variables and Constraints

• rand, randc, and constraint added to class definition

class Bus; rand bit[15:0] addr; rand bit[31:0] data;

constraint word_align { addr[1:0] == 2’b0; } endclass

• Generate 50 data and quad-aligned addresses

Bus bus = new;repeat(50) begin

integer result = bus.randomize(); end

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Basic Additions• Wild card operators (=?= and !?=)• Pass by reference

• Argument default values and pass by name

• Alias for nets• Short nets in a module

• Dynamic Memory• Objects, threads, strings, dynamic and associative arrays• Automatically Managed

Declaration: task foo( int j = 5, int k = 8 );

Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9));

Declaration: task tk( var int[1000:1] ar );

Use: tk( my_array ); // no & needed

5 December 2003 David W. Smith 9

Process Control/Synchronization• Verilog thread support from fork…join with continuation

when all threads complete• SV threads use fork…join with continuation control

• all• any• none

• Threads execute until a blocking statement• wait for event, mailbox, semaphore, variable change, ...

• Enhanced events (value and duration, passed as arguments)• Threads are controlled by

• $terminate• $wait_child• $suspend_thread• $exit

all anypriority

none 3.0 process

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Clocking Domain

• A clocking domain defines a synchronous interface for testbench and properties• Every clocking domain has only one clock event• Sample and drive timing specified with respect to clock• A signal may appear in multiple clocking domains

• Input - multiple samples• Output – default bus resolution

• Clocking domain creates a scope

5 December 2003 David W. Smith 11

Synchronous Interfaces: Clocking

device busenablefull

clk

emptydata[7:0]

SynchronousInterface

clocking bus @(posedge clk);

default input #1ns output #2ns;

input enable, full;

inout data;

output empty;

output #6ns reset = top.u1.reset;

endclocking

Testbench Uses: bus.enable bus.data ...

Clocking Event “clock”

Default I/O skew

Hierarchical signal

Override Output skew

Race-free cycle and transaction level abstraction

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Testbench Program Block

• Purpose: contains testbench verification code• program is similar to a module

• Only one implicit initial block• Special semantics

Execute in verification phase design clocking verification read_only

program name ( port_list );declarations (class, type, function, clocking...)statements

endprogram

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System Verilog Testbench

Testbench

Verification Extensions

Basic Types

Random Constraints

References

Aliases

Process Control/Synchronization

Testbench Specific

Clocking Domains

Program Block