system level design with embedded platforms

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1 System Level Design with Embedded Platforms Tutorial Session 3. Friday June 9 DAC 2000 Intro What will we learn today Problem definition What is System Level Design Productivity Gap in new Designs • Terminology Embedded Systems – Platform Models of Computation & Models of Architecture Y-chart methodology

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Page 1: System Level Design with Embedded Platforms

1

System Level Designwith Embedded Platforms

Tutorial Session 3.Friday June 9

DAC 2000

IntroWhat will we learn today

• Problem definition– What is System Level Design– Productivity Gap in new Designs

• Terminology– Embedded Systems– Platform– Models of Computation & Models of Architecture– Y-chart methodology

Page 2: System Level Design with Embedded Platforms

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IntroWhat will we learn today(2)

• Exploration in Wireless Design.• Separation of concerns

– Function versus Architecture– Communication versus Computation– Exploration of design alternatives

• Current System Level Design in an industrialsetting– Video application characteristics– Modern CPU design– Multi-media platform

IntroWhat will we learn today(3)

• The way applications are written have anprofound impact on the system levelperformance and power consumption.

Page 3: System Level Design with Embedded Platforms

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Alberto SangiovanniVincentelli

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Bart KienhuisApplicationsApplicationsArchitecture

Instance

Mapping

Applications

PerformanceAnalysis

PerformanceNumbers Design Methodology

Page 4: System Level Design with Embedded Platforms

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Jan Rabaey

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ReconfigurableDataPath

ReconfigurableState Machines

Embedded uP+ DSPs

FPGA

DedicatedDSP

Kees Vissers(part 1)

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Mapping

PerformanceAnalysis

10 20 30 40 50 60 70 80 90 100 110 0

50

100

150

Field number

cpu

load

(%

)

90%

16%

tm1000 @ 125MHz

cpu64 @ 300MHz

Page 5: System Level Design with Embedded Platforms

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Kees Vissers(part 2)

datacache16KB

datacache16KB

mmummu

mmummu

64-bitmemory

bus multi-port 128 words x 64 bits register filemulti-port 128 words x 64 bits register file

FUFU FUFU FUFU FUFUFUFU

instructioncache32 KB

instructioncache32 KB

mmummu

bypass networkbypass network

PCPCexceptions exceptions

32-bitperipheral

bus

VLIW instruction decode and launch

Diederik Verkestfor (i=0;i<n;i++) for (j=0; j<3; j++) for (k=1; k<7; k++) … = A[i*4+k];

Memory Bottleneck

VLIWcpu

I$

video-in

video-out

audio-in

SDRAM

audio-out

PCI bridge

Serial I/O

timers I2C I/O

D$

Page 6: System Level Design with Embedded Platforms

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Schedule Morning

• 09:10 - 10:00, Alberto Sangiovanni Vincentelli– “System Design Paradigms”

• 10:00 - 11:00, Bart Kienhuis– “Y-chart methodology and Models of Computation

and Architecture”

• 11:00 - 12:00, Jan Rabaey– “Embedded System Design for Wireless

Applications”

• 12:00 - 13:00 Lunch

Schedule Afternoon

• 13:00 - 13:30, Alberto Sangiovanni Vincentelli– “Platform-based Design: an Automotive Example”

• 13:30 - 15:30, Kees Vissers– “Video Algorithms and Architectures”– “TriMedia CPU64”– “MPEG decoder Case”

• 15:30 - 16:30, Diederik Verkest– “Memory Organization in Embedded Multimedia

Platforms”

• Wrap-upSpecial thanks to Mary Stewart (UC Berkeley) for the Artwork