system components
DESCRIPTION
System components. Timing diagrams. Memory. Busses and interconnect. Timing diagrams. A timing diagram shows a trace through the operation of a system. Generally used for asynchronous machines with timing constraints. enq. ack. Timing diagram syntax. Constant value: Stable: Changing: - PowerPoint PPT PresentationTRANSCRIPT
© 2000 Morgan Kaufman
Overheads for Computers as Components
System components
Timing diagrams.Memory.Busses and interconnect.
© 2000 Morgan Kaufman
Overheads for Computers as Components
Timing diagrams
A timing diagram shows a trace through the operation of a system. Generally used for asynchronous machines with timing
constraints.
enq
ack
© 2000 Morgan Kaufman
Overheads for Computers as Components
Timing diagram syntax
Constant value:
Stable:
Changing:
Unknown:
0
1
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Timing constraints
Minimum time between two events:
enq
ack
20 ns
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Origin of timing constraints
Control signals are passed on the bus:
a
20 ns
c
D Q
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Memory device organization
Memory arrayn r
c
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Memory parameters
Size. Address width.
Aspect ratio. Data width.
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Types of memory
ROM: Mask-programmable. Flash programmable.
RAM: DRAM. SRAM.
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SRAM vs. DRAM
SRAM: Faster. Easier to integrate with logic. Higher power consumption.
DRAM: Denser. Must be refreshed.
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Typical generic SRAM
SRAM
CE’
R/W’
Adrs
Data
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Generic SRAM timing
time
CE’
R/W’
Adrs
Data
read write
From SRAM From CPU
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Generic DRAM device
DRAM
CE’
R/W’
Adrs
Data
RAS’
CAS’
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Generic DRAM timing
time
CE’
R/W’
RAS’
CAS’
Adrs
Data
rowadrs
coladrs
data
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Page mode access
time
CE’
R/W’
RAS’
CAS’
Adrs
Data
rowadrs
coladrs
data
coladrs
coladrs
data data
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RAM refresh
Value decays in approx. 1 ms.Refresh value by reading it.
Can’t access memory during refresh.CAS-before-RAS refresh.Hidden refresh.
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Other types of memory
Extended data out (EDO): improved page mode access.
Synchronous DRAM: clocked access for pipelining.
Rambus: highly pipelined DRAM.
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Flash issues
Flash is programmed at system voltages.
Erasure time is long.Must be erased in blocks.
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Generic bus structure
Address:
Data:
Control:
m
c
n
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Electrical bus design
Bus signals are usually tri-stated.Address and data lines may be
multiplexed.Every device on the bus must be able to
drive the maximum bus load: Bus wires. Other bus devices.
Bus may include clock signal. Timing is relative to clock.
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Four-cycle handshake
enq
ack
4
1
data
2
3
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Busses as communicating machines
enq = 1
enq = 0
0
1
1
0
M1
ack = 0
ack = 1
0
1
1
0
M2
ack
ack
enq
enq
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When should you handshake?
When response time cannot be guaranteed in advance: Data-dependent delay. Component variations.
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Fixed-delay memory access
CPU
memory
R/W
data = mem[adrs]
R
Wmem[adrs] =data
R/W
data
adrs
read = 1adrs = A
reg = data
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Variable-delay memory access
CPU
memory
read = 1adrs = A
reg = data
R/W
done = 0
data = mem[adrs]done = 1
mem[adrs] =data
done = 1R
W
R/W
data
adrsdone
y
n
done
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Typical bus access
time
clock
R/W’
Addressenable
adrs
DataReady’
data
read write
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Bus mastership
Bus master controls operations on the bus.
CPU is default bus master.Other devices may request bus
mastership. Separate set of handshaking lines. CPU can’t use bus when it is not master.
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Direct memory access (DMA)
DMA provides parallelism on bus by controlling transfers without CPU.
CPU
memory I/O
DMA
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DMA operation
CPU sets up DMA transfer: Start address. Length. Transfer block length. Style of transfer.
DMA controller performs transfer, signals when done: Cycle-stealing. Priority.
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ARM busses
AMBA: Open standard. Many external
devices.Two varieties:
AMBA High-Performance Bus (AHB).
AMBA Peripherals Bus (APB).
CPU
brid
ge
memory I/O
AHB APB