system aware chip level power integrity analysis using ... · pdf file1 © 2015 ansys,...

1 © 2015 ANSYS, Inc. October 14, 2016 ANSYS Confidential

System Aware Chip Level Power Integrity Analysis Using Redhawk-CPA


• Supply noise due to power delivery network composed of chip, package and board is represented by

Power Supply Noise

)(*)()( fZfIdt

diLRtIV

Current Spectrum at frequency: I(f) domain Impedance: Z(f)


PDN(Power Delivery Network) vs. Frequency

1 MHz 10 MHz 100 MHz 1 GHz 10 GHz

Board Only

Board+Package Package+Chip Chip Only

0 MHz frequency

Managing Impedance

sourced by Power Integrity Modeling and Design for Semiconductors and Systems, p65, Madhavan Swaminathan and A.Ege Engin


• Assumption: Chip Bandwidth is from 27MHz to 1GHz

• Critical I(f) is overlaid with package and board dominant frequency

• Noise suppression method like adding decoupling capacitors on package or board PDN can make unexpected harmonic with dominant frequency of chip

Pitfalls in Separated Development Environment

f(MHz)

Current(A)

27 50 100 200 400 1000

I(f)

Voltage drop at chip bump will be larger due to 4X increased impedance at 200MHz

50 200

Target Impedance

Resonant Point shift right by adding decoupling cap on board near to package

f(MHz)

Z(f)

Impedance is up from 50mΩ to 200mΩ


Voltage Drop at On-Chip Bump vs. PDN Scope

Power & Ground bumps on Chip

Without package & board, easy to bring wrong result !!

Assumption

• Supply voltage at PMIC: 1.5V

• Allowable voltage at bump: 1.5V+/-10% => +/- 150mV

• Voltage tolerance spec at bump: - undershoot: 1.35V - overshoot: 1.65V

Voltage level at bump with package: 1.28V~1.62V= > Slightly over the spec

Voltage level at bump with package & board: 0.87V ~1.09V => Over the spec


Voltage Drop at On-chip Cell Instance vs. PDN Scope

• Cell instance’s timing is related to voltage level at power and ground rail

• If voltage drop at rail of standard cell does not meet rule, it means standard cell does not have stable voltage level to meet target frequency

Will cause function failure or not meet target frequency

Assumption

• Allowable voltage level at chip bump: 1.35~1.65V

• Allowable voltage level at power and ground rail of standard cell: 1.25 ~ 1.5V

Voltage level at cell instance’s rail with package: 1.23V~1.6V = > Slightly over the spec

Voltage level at cell instance’s rail with package & board 0.83V~1.07V = > Over the spec


• Chip level dynamic voltage drop analysis including board as well as package

• ANSYS Solution: SIwave-CPA, RH-CPA

• Advantages: Prevent under/over-design due to package/board absence

• Applications

– High speed(over 100’s MHz) design multiple frequency signatures

– Low or mid frequency(KHz to 100’s MHz) target design

ex) IoT, Image processing, Automotive etc

– SCAN mode(shift & capture) analysis

ANSYS System Aware Chip Level Power Integrity Solution

Chip level sign-off(Static/Dynamic voltage drop analysis) with package/board on RH-CPA

• Power integrity Sign-off Analysis

• Dynamic voltage aware function failure check due to glitch noise

• Dynamic voltage aware timing analysisBoard’s parasitic extraction on

SIwave-CPA

RH-CPA Product Seminar.pptx


PDN Parasitic Extraction of Board PDN from SIwave-CPA

Result Check

Open Project or import Board design

Specify Package ball part on board

Make group of VRM part

Check input and execute RLCG netlist creation

with Siwave-CPA

Specify target P/G domain

Specify VRM part on board

Set options for SIWave-CPA execution

Demonstration Video

Board_CPA_extraction.mp4

Board_CPA_extraction.mp4


Integrated RH-CPA Flow Overview

Import package layout with CPA_FILES keywords in GSR file:

CPA_FILES

PACKAGE ./fccsp.mcm

MODEL ./fccsp

RHCPA Model

VS

S

Bum

p

s

VD

D

Bum

p

s

Generate high resolution RLCK model with RHCPA

RHCPA Model

VS

S

Bum

p

s

VD

D

Bum

p

s

DiePackag

eRHCPA automatically connects package model and die to perform package aware static, dynamic and rampup chip analyses

• View package pin RL results in color maps.

• Visualize chip and pkg bump voltage and inductance maps in same GUI

• Perform static co-simulation on the pkg layout

• View results statistics and design weakness in RHCPA Explorer


Integrated RH-CPA GUI Overview

Design Layout

Property Editor

Layout Manager Configuration Buttons

Result Color Maps

Extraction Setup Dialog

Setup Tabs


CPA Performance

Accuracy PDN accuracy typically < 10% of

Q3D. Ground bounce preserved

Performance/Capacity Very high capacity – full package and

PCB structures – 1000’s of sources/sinks

Fast extraction (minutes to a few hours – even for extremely large packages with 10K bumps and boards)

Technology Based on 3D FEM Similar technology as PSI solver Extracts RLCG netlist

Applications Packages, PCBs Handles decaps,

and other embedded components


Analyze Chip Level SimulationResult

System(Package & board) Aware Chip Level Power Integrity Analysis on RH-CPA

Setup Design

Chip Power Calculation

Package PDN Parasitic Extraction

Chip Level Dynamic VoltageDrop Simulation

Demonstration Video Import Board Netlist

Connect Package and Board

Chip PG Parasitic Extraction

run_vcd.mp4

run_vcd.mp4


• Up to 4GHz extraction bandwidth

• Linked to SIwave-CPA

• 3DIC Feature Support

• Totem-CPA is available

Upcoming CPA 18.0 Features

.xfl and Extraction Result from SIwave-CPA

Specifying .xfl and result directory in gsr

./adsCPA

• Chip designer can have the same configuration set by package designer as well as

co-visualization analysis without package parasitic re-extraction

system aware chip level power integrity analysis using ... · pdf file1 © 2015 ansys,...

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