synthesis report
TRANSCRIPT
Synthesis report:Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.44 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.44 secs
--> Reading design: vend.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "vend.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "vend"
Output Format : NGC
Target Device : xc3s50-5-pq208
---- Source Options
Top Module Name : vend
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "VEND_new_2.V" in library work
Module <vend> compiled
No errors in compilation
Analysis of file <"vend.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <vend> in library <work> with parameters.
s0 = "000"
s1 = "001"
s2 = "010"
s3 = "011"
s4 = "100"
s5 = "101"
sc = "110"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <vend>.
s0 = 3'b000
s1 = 3'b001
s2 = 3'b010
s3 = 3'b011
s4 = 3'b100
s5 = 3'b101
sc = 3'b110
Calling function <fsm>.
Module <vend> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <vend>.
Related source file is "VEND_new_2.V".
WARNING:Xst:646 - Signal <fsm/1/fsm<5:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 1-bit latch for signal <$old_fsm/1/fsm_newspaper_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 3-bit latch for signal <$old_fsm/1/fsm_NEXT_STATE_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:737 - Found 1-bit latch for signal <fsm_newspaper_1$mux0000>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
Found 1-bit 7-to-1 multiplexer for signal <fsm_newspaper_1$mux0001>.
Found 3-bit 7-to-1 multiplexer for signal <fsm_NEXT_STATE_2$mux0000>.
Found 3-bit register for signal <PRES_STATE>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 4 Multiplexer(s).
Unit <vend> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 1
3-bit register : 1
# Latches : 3
1-bit latch : 2
3-bit latch : 1
# Multiplexers : 2
1-bit 7-to-1 multiplexer : 1
3-bit 7-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <0> (without init value) has a constant value of 0 in block <fsm_newspaper_1_mux0000>. This FF/Latch will be trimmed during the optimization process.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 3
Flip-Flops : 3
# Latches : 3
1-bit latch : 2
3-bit latch : 1
# Multiplexers : 2
1-bit 7-to-1 multiplexer : 1
3-bit 7-to-1 multiplexer : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <fsm_newspaper_1_mux0000> (without init value) has a constant value of 0 in block <vend>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <vend> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vend, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 3
Flip-Flops : 3
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : vend.ngr
Top Level Output File Name : vend
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 6
Cell Usage :
# BELS : 16
# LUT2 : 1
# LUT3 : 6
# LUT4 : 6
# MUXF5 : 3
# FlipFlops/Latches : 7
# FDR : 3
# LD_1 : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 4
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-5
Number of Slices: 7 out of 768 0%
Number of Slice Flip Flops: 6 out of 1536 0%
Number of 4 input LUTs: 13 out of 1536 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 124 4%
IOB Flip Flops: 1
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
---------------------------------------------------------+------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
---------------------------------------------------------+------------------------------------+-------+
clock | BUFGP | 3 |
fsm_newspaper_1_cmp_eq0000(fsm_newspaper_1_cmp_eq00001:O)| NONE(*)(_old_fsm_1_fsm_newspaper_1)| 4 |
---------------------------------------------------------+------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 4.215ns
Maximum output required time after clock: 6.141ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 2.378ns (Levels of Logic = 1)
Source: reset (PAD)
Destination: PRES_STATE_0 (FF)
Destination Clock: clock rising
Data Path: reset to PRES_STATE_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 0.715 0.771 reset_IBUF (reset_IBUF)
FDR:R 0.892 PRES_STATE_0
----------------------------------------
Total 2.378ns (1.607ns logic, 0.771ns route)
(67.6% logic, 32.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fsm_newspaper_1_cmp_eq0000'
Total number of paths / destination ports: 21 / 3
-------------------------------------------------------------------------
Offset: 4.215ns (Levels of Logic = 4)
Source: tk<1> (PAD)
Destination: _old_fsm_1_fsm_NEXT_STATE_2_0 (LATCH)
Destination Clock: fsm_newspaper_1_cmp_eq0000 rising
Data Path: tk<1> to _old_fsm_1_fsm_NEXT_STATE_2_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 0.715 1.201 tk_1_IBUF (tk_1_IBUF)
LUT3:I0->O 1 0.479 0.851 fsm_NEXT_STATE_2_mux0001<2>1 (fsm_NEXT_STATE_2_mux0001<2>)
LUT3:I1->O 1 0.479 0.000 Mmux_fsm_NEXT_STATE_2_mux0000_31 (Mmux_fsm_NEXT_STATE_2_mux0000_3)
MUXF5:I1->O 1 0.314 0.000 Mmux_fsm_NEXT_STATE_2_mux0000_2_f5 (fsm_NEXT_STATE_2_mux0000<0>)
LD_1:D 0.176 _old_fsm_1_fsm_NEXT_STATE_2_0
----------------------------------------
Total 4.215ns (2.163ns logic, 2.052ns route)
(51.3% logic, 48.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fsm_newspaper_1_cmp_eq0000'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 6.141ns (Levels of Logic = 1)
Source: _old_fsm_1_fsm_newspaper_1 (LATCH)
Destination: newspaper (PAD)
Source Clock: fsm_newspaper_1_cmp_eq0000 rising
Data Path: _old_fsm_1_fsm_newspaper_1 to newspaper
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD_1:G->Q 1 0.551 0.681 _old_fsm_1_fsm_newspaper_1 (_old_fsm_1_fsm_newspaper_1)
OBUF:I->O 4.909 newspaper_OBUF (newspaper)
----------------------------------------
Total 6.141ns (5.460ns logic, 0.681ns route)
(88.9% logic, 11.1% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.76 secs
-->
Total memory usage is 189632 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 6 ( 0 filtered)
Number of infos : 4 ( 0 filtered)
Bitgen report:
Release 12.2 - Bitgen M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '3s50.nph' in environment
C:\Xilinx\12.2\ISE_DS\ISE\.
"vend" is an NCD, version 3.2, device xc3s50, package pq208, speed -5
Opened constraints file vend.pcf.
Wed Aug 24 21:09:41 2011
C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g
GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No vend.ncd
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most
commonly, bitgen has determined and will use a specific value instead of the
generic command-line value of "Auto". Alternately, this message appears if
the same option is specified multiple times on the command-line. In this
case, the option listed last will be used.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 6** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DCMShutdown | Disable** |
+----------------------+----------------------+
| DCIUpdateMode | AsRequired** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup** |
+----------------------+----------------------+
| HswapenPin | Pullup** |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| Match_cycle | NoWait |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActivateGclk | No* |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| PartialMask0 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask1 | (Not Specified)* |
+----------------------+----------------------+
| PartialMask2 | (Not Specified)* |
+----------------------+----------------------+
| PartialGclk | (Not Specified)* |
+----------------------+----------------------+
| PartialLeft | (Not Specified)* |
+----------------------+----------------------+
| PartialRight | (Not Specified)* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from vend.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net fsm_newspaper_1_cmp_eq0000
is sourced by a combinatorial pin. This is not good design practice. Use the
CE pin to control the loading of data into the flip-flop.
DRC detected 0 errors and 1 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "vend.bit".
Bitstream generation is complete.