synthesis - creating web pages in your...
TRANSCRIPT
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PIPELINE DESIGN
DATA PATH AND
CONTROL SYNTHESIS
c Giovanni De Micheli
Stanford University
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Outline
c GDM
� Synthesis of pipelined circuits:
{ Scheduling.
{ Binding.
� Data-path synthesis.
� Control-unit synthesis.
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High-level synthesis
of pipelined circuits
c GDM
� Pipeline circuits:
{ Concurrent execution of operations
on di�erent data sets.
{ Increase throughput:
� I/O data rate.
{ Preserve latency.
� Applicable to:
{ General purpose processors.
{ Digital signal processors.
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Example
c GDM
* * * * +
<+**
−
−
1 2
3
4
5
6
7
8
9
10
11
TIME 1
TIME 2
TIME 2
TIME 1
ST
AG
E 1
ST
AG
E 2
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Synthesis of pipelined circuits
c GDM
� DSP applications:
{ Mainly data-path pipelining.
{ Few exceptions/interrupts.
{ Mature area.
� Microprocessors:
{ Advanced features:
� Stalls, ush, bypass, hazard avoidance.
{ Synthesis tools not ready yet.
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Issues in synthesis of pipelined circuits
c GDM
� Partitioning:
{ Pipe-stage formation.
� Scheduling:
{ Source vertex of the sequencing graph
�red at constant rate.
� Sharing:
{ More concurrency.
{ Binding and scheduling are a�ected.
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Scheduling of pipelined circuits
c GDM
� Scheduling of non-pipelined circuit
using pipelined resources.
� Scheduling of pipelined circuit
using non-pipelined resources.
{ Functional pipelining.
� Both problems can be modeled by ILP.
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Scheduling for functional pipelining
c GDM
� Choose:
{ cycle-time.
{ data-introduction interval �0.
� Determine (area,latency) spectrum.
� Key fact:
{ Simultaneous operations at steps:
� l+ p�0
{ Reduced sharing.
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Scheduling for functional pipelining
ILP model
c GDM
d�=�0e�1X
p=0
X
i:T (vi)=k
l+p�0X
m=l�di+1+p�0
xim � ak 8k;8l
� Used in conjunction with other constraints.
� Use regular ILP solvers.
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Scheduling for functional pipelining
Heuristic algorithms
c GDM
� List scheduling:
{ Compute resource usage at each step.
{ Determine candidates.
� Force-directed scheduling.
{ Operation-type distribution:
� Account for overlapping.
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Example
c GDM
* * * * +
<+**
−
−
1 2
3
4
5
6
7
8
9
10
11
TIME 1
TIME 2
TIME 2
TIME 1
ST
AG
E 1
ST
AG
E 2
12
0 1 2 3
12
0 1 2 3
� Distribution graphs for multiplier and ALU.
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Loop folding
c GDM
� Reduce execution delay of a loop.
� Pipeline operations inside a loop.
{ Overlap execution of operations.
{ Need a prologue and epilogue.
� Use pipeline scheduling for loop graph model.
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Example
c GDM
1 2
3
4
5
NOP
NOP
1 2
3
NOP
NOP
4
5
NOP
NOP
(a) (b)
TIME 1
TIME 2
TIME 3
TIME 4
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Resource sharing
for pipelined circuits
c GDM
� Scheduled graphs:
{ Determine compatibility (or con ict) graphs.
� The lower the �0 (the higher the throughput):
{ The lower the compatibility.
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Example: �0 = 2
c GDM
* * * +
<**
−
−
1 2
3
4
5
6
7 8*
+9
10
11
TIME 1
TIME 2
TIME 2
TIME 1
ST
AG
E 1
ST
AG
E 2
1
2
3 4
5 6 7
8
9
11
10
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Resource sharing
for pipelined circuits
c GDM
� Branching constructs:
{ Special care to avoid deadlocks.
� Twisted pairs:
{ Two mutually compatible operation pairs
with twisted dependencies.
� Sharing operations in twisted pairs
must be avoided.
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Example
c GDM
* +
*
1 2
3 4
+
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Data path synthesis
c GDM
� Resource binding.
� Connectivity synthesis:
{ Connection of resources to:
multiplexers busses and registers.
{ Control unit interface.
{ I/O ports.
� Physical data-path synthesis.
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Example
c GDM
* ALU
REGISTERS
xyu
a3
dxenable
mux control
ALU control (+,−,<)
c
DATA−PATH CONTROL−UNIT
r1r2
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Control synthesis
c GDM
� Synthesis of the control unit.
� Logic model:
{ Synchronous FSM.
� Physical implementation:
{ Microcode (ROM,PLA).
{ Hard-wired FSM.
{ Distributed FSM.
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Control synthesis
c GDM
� Synthesize circuit that:
{ Executes scheduled operations.
{ Provides synchronization.
{ Supports:
� Iteration.
� Branching.
� Hierarchy.
� Interfaces.
� Assumption:
{ Synchronous implementation.
{ Control unit is a FSM (or connection of
FSMs).
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Controlling scheduled operations
c GDM
� Simple model:
{ No branching, iteration, hierarchy.
{ No data-dependent delays.
� Implementation:
{ FSM-oriented design:
� Hardware: PLAs, gates, registers.
� One FSM state per schedule level.
{ Microcode-oriented design:
� Hardware: ROM, PLA, counter.
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FSM-based implementation
c GDM
� Simple model:
{ next-state function: unconditional.
{ output function: activate operations.
� Extended model:
{ Branching and iteration:
� Conditional next-state function.
{ Hierarchy:
� Hierarchical FSM connection.
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Example
c GDM
* * * * +
<+**
−
−
1 2
3
4
5
6
7
8
9
10
11
0NOP
NOP
TIME 1
TIME 2
TIME 3
TIME 4
n
s s
ss
1 2
4 3
1,2,6,8,103,7,9,11
45
reset
reset
reset
reset’
reset’
reset’
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Microcode implementation
c GDM
� Horizontal microcode:
{ One bit per activation signal.
{ One microcode word per schedule level.
{ Maximum performance.
{ Wide words.
� Vertical microcode:
{ Encode each resource activation signal.
{ Shorter words.
{ One (or more) words per schedule level.
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Example of horizontal microcode
c GDM
* * * * +
<+**
−
−
1 2
3
4
5
6
7
8
9
10
11
0NOP
NOP
TIME 1
TIME 2
TIME 3
TIME 4
n
1 1 0 0 0 1 0 1 0 1 00 0 1 0 0 0 1 0 1 0 10 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 00 11 01 1
Counter Activation signals
Address Microwords
Reset
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Example of vertical microcode
c GDM
Activation signals
Microwords
0 0 0 10 0 1 00 1 1 0 1 0 0 01 0 1 0
0 0 1 10 1 1 11 0 0 11 0 1 1
0 1 0 0
0 1 0 1
Decoder
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Microcode compaction problem
c GDM
� Partition ROM word into �elds.
� Encode signals in each �eld.
� Allow for a code for NOP.
� Activation signals in each �eld must not be
concurrent.
� Problems:
{ Minimize number of �elds.
{ Minimize total ROM width.
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Microcode optimization
c GDM
� Con ict graph:
{ Concurrent operations.
{ Optimum vertex coloring
yields minimum number of �elds.
� Compatibility graph:
{ Non-concurrent operations.
{ Optimum clique partitioning
yields minimum number of �elds.
{ Minimum weighted clique partitioning
yields minimum number of bits.
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Example
c GDM
�eld op code
A 1 01
A 3 10
A 4 11
B 2 1
C 6 01
C 7 10
C 5 11
D 8 01
D 9 10
E 10 01
E 11 10
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Example
c GDM
Activation signals
Microwords
A B C D E
Microword format
1 1 0 0 0 0 0 0 00 0 0 1 1 0 0 0 0
0 1 1 0 1 0 1 0 11 0 0 1 0 1 0 1 0
D1 D2 D3 D4
1,3,4 2 6,7,5 8,9 10,11
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Hierarchical control
c GDM
� Exploit the hierarchical structure of sequencing
graphs.
� One controller per entity.
� Interconnected �nite state machines.
� Handshake:
{ activate signals.
{ condition signals.
{ reset signals.
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Example
c GDM
CONTROL
CONTROL
actact
act
act
reset
reset
CONTROL−UNIT
BLOCK
BLOCK
DATA−PATH
act
reset
act
reset
act
reset
act
BLOCK
BLOCK
BLOCK
CONTROL
CONTROL
CONTROL
CONTOL−UNIT DATA−PATH
condition
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Control synthesis for
unbounded-latency sequencing graphs
c GDM
� Data-dependent delay operations.
{ activate signals.
{ completion signals.
� Synchronization problem:
{ Wait on completion signals.
{ Wait on external synchronization.
� Several strategies.
{ Clustering.
{ Adaptive Control.
{ Relative Scheduling.
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Summary
Control synthesis
c GDM
� Di�erent approaches.
� Implementations:
{ FSM, connection of FSMs or ROM.
� Techniques:
{ Bounded delays only:
� FSM { microcode.
{ Unbounded delays:
� Di�erent methods to provide synchronization.