symmetric circuits and fixed-point logicsad260/talks/aachen3.pdf · 2013. 11. 11. · symmetric...

Symmetric Circuits and Fixed-Point Logics

Anuj Dawar

University of Cambridge Computer Laboratoryvisiting RWTH Aachen

joint work with Matthew Anderson

Aachen, 8 November 2013

Is There a Logic for P?

The question of whether or not there is a logic expressing exactly the Pproperties of (unordered) relational structures is the central problem inDescriptive Complexity.

If we assume structures are ordered, then FP, the extension of first-orderlogic with least fixed points suffices. (Immerman; Vardi 1982)

In the absence of order FP fails to express simple cardinality propertiessuch as evenness.

Anuj Dawar November 2013

Fixed-point Logic with Counting

Immerman had proposed FPC—the extension of FP with a mechanismfor counting

Two sorts of variables:

• x1, x2, . . . range over |A|—the domain of the structure;

• ν1, ν2, . . . which range over numbers in the range 0, . . . , |A|If φ(x) is a formula with free variable x , then ν = #xφ denotes that ν isthe number of elements of A that satisfy the formula φ.

We also have the order ν1 < ν2, which allows us (using recursion) todefine arithmetic operations.


Expressive Power of FPC

Most “obviously” polynomial-time algorithms can be expressed in FPC.

This includes P-complete problems such as

CVP—the Circuit Value ProblemInput: a circuit, i.e. a labelled DAG with source labels from{0, 1}, internal node labels from {∨,∧,¬}.Decide: what is the value at the output gate.

CVP is expressible in FP.

It is expressible in FPC for circuits that may include threshold or countinggates.


Expressive Power of FPC

Many non-trivial polynomial-time algorithms can be expressed in FPC:

• FPC captures all of P over any proper minor-closed class of graphs(Grohe 2012)

• FPC can express linear programming problems; max-flow andmaximum matching on graphs. (Anderson, D., Holm 2013)

But some cannot be expressed:

• There are polynomial-time decidable properties of graphs that arenot definable in FPC. (Cai, Furer, Immerman, 1992)

• Solvability of a system of linear equations over a finite field cannotbe expressed in FPC. (Atserias, Bulatov, D. 2009)


Circuit Complexity

A language L ⊆ {0, 1}∗ can be described by a family of Booleanfunctions:

(fn)n∈ω : {0, 1}n → {0, 1}.

Each fn may be given by a circuit Cn made up of Boolean gates, with nBoolean inputs and one output.

If the size of Cn is bounded by a polynomial in n, the language L is in theclass P/poly.

If, in addition, the function n 7→ Cn is computable in polynomial time L isin P.

Note: it makes no difference if the circuits only use {AND,OR,NOT} or a

richer basis with ubounded fan-in or threshold gates.


Circuit Lower Bounds

It is conjectured that NP 6⊆ P/poly.

Lower bound results have been obtained by putting further restrictions onthe circuits:

• No constant-depth (unbounded fan-in), polynomial-size family ofcircuits decides parity. (Furst, Saxe, Sipser 1983).

• No polynomial-size family of monotone circuits decides clique.(Razborov 1985).

• No constant-depth, O(nk4 )-size family of circuits decides k-clique.

(Rossman 2008).

No result separates NP from constant-depth, polynomial-size families ofcircuits with threshold gates.


Circuits for Graph Properties

A property of graphs (or other relational structures) in P is recognised bya family of Boolean circuits Cn:

• inputs to Cn are n2 potential edges, each taking value 0 or 1;

• the size of Cn is bounded by a polynomial p(n);

• the family is uniform, so the function n 7→ Cn is in P (orDLogTime).

Cn is invariant if the output is unchanged under a permutation of theinputs induced by a permutation of [n].


Symmetric Circuits

Say Cn is symmetric if any permutation of [n] applied to its inputs can beextended to an automorphism of Cn.

• Any symmetric circuit is invariant, but not conversely.

Consider the obvious circuit for deciding if the number ofedges in an n-vertex graph is even.

• Any formula of first-order logic translates into a uniformfamily of constant-depth, polynomial-size symmetric Boolean circuits.

For each subformula ψ(x) and each assignment a of valuesto the free variables, we have a gate.Existential quantifiers translate to big disjunctions, etc.


Symmetric Circuits

• Any formula φ of FP translates into a uniform family ofpolynomial-size symmetric Boolean circuits.

For each n, φ translates into a first-order formula of depthpolynomial in n and with a constant bound k on thenumber of free variables in a sub-formula.

• Any formula of FPC translates into a uniform family ofpolynomial-size symmetric threshold (or majority) circuits.


Symmetric Circuits

• There is trivially a polynomial-size family of symmetric circuits Cn

deciding whether n is even.

• Is there a polynomial-size family of symmetric Boolean circuitsdeciding if an n vertex graph has an even number of edges? No – aswe shall see.

• Are polynomial-size families of uniform symmetric threshold circuitsmore powerful than Boolean circuits? Yes – follows from above.

• Can every invariant circuit be translated into an equivalentsymmetric threshold circuit, with only polynomial blow-up? No – aswe shall see.


Main Results

TheoremA class of graphs is accepted by a P-uniform, polynomial-size, symmetricfamily of Boolean circuits if, and only if, it is definable by an FP formulainterpreted in G ] ([n], <).

TheoremA class of graphs is accepted by a P-uniform, polynomial-size, symmetricfamily of threshold circuits if, and only if, it is definable in FPC.


Some Consequences

We get a natural and purely circuit-based characterisation of FPCdefinability.

Inexpressiblity results for FPC are also lower bound results against anatural circuit class.


Technical Tools – Support

For a symmetric circuit Cn we assume w.l.o.g. that the automorphismgroup is Sn acting in the natural way.

For a gate g in Cn, Stab(g) denotes the stabilizer group of g , i.e.

Stab(g) = {π ∈ Sn | π(g) = g}

Say a set X ⊆ [n] supports g if

Stab•(X ) ⊆ Stab(g)

where Stab•(X ) := {π ∈ Sn | π(x) = x for all x ∈ X}, is the pointwisestabilizer of X .

Note: For the family of circuits (Cn)n∈ω obtained from an FP(C) formulathere is a constant k such that all gates have a support of size at most k.


Technical Tools—Supporting Partitions

We want to to show that in a symmetric circuit of polynomial size, eachgate has support of bounded size. To this end, we introduce supportingpartitions.

For a gate g in a symmetric circuit Cn, say that a partition P of [n]supports g if every permutation that fixes each P ∈ P also fixes g :

Lemma: There is a coarsest partition (denote it Sup(g)) that supports g .

Proof sketch: For two partitions P and P ′, let E(P,P ′) denote the finestpartition that is coarser than P and P ′.Then, any permutation that fixes each part in E(P,P ′) can be expressedas a composition of permutations fixing all parts in P and P ′ respectively.


Technical Tools – Supporting Partitions

Writing Stab•(Sup(g)) for the the group of permutations that fix eachpart in Sup(g) and Stab(Sup(g)) for the group of permutations that fixthe partition Sup(g) setwise, we have:

Stab•(Sup(g)) ⊆ Stab(g) ⊆ Stab(Sup(g))

The first inclusion is by definition. The second follows from the fact thatfor any permutation π ∈ Sn, Sup(π(g)) = π(Sup(g)).

By the orbit-stabilizer theorem, the size of the orbit of g is n!|Stab(g)| .

So, an upper bound on Stab(g) gives us a lower bound on the orbit of g

Conversely, knowing that the orbit of g is at most polynomial in n givesus bounds on Sup(g).


Support Theorem

For a circuit C , Sup(C ) denotes the maximum over all gates g in C ofthe size of the union of all but the largest part in Sup(g).

TheoremFor any 1 > ε ≥ 2

3 , let C be a symmetric s-gate circuit over [n] with

n ≥ 256ε2 , and s ≤ 2n1−ε

. Then

Sup(C ) ≤ 33

ε

log s

log n.

CorollaryPolynomial-size symmetric circuits have constant support.


Proof Sketch of Support Theorem – 1

Claim: If k is the number of parts in Sup(g), then min{k, n−k} ≤ 8εlog slog n .

This is a computation of the number of permutations that setwise fix apartition P with k parts.

We can show that, unless min{k, n − k} ≤ 8εlog slog n ,

n!

|Stab(P)|> s.

so, |Orb(g)| = n!|Stab(g)| ≥

n!|Stab(Sup(g))| > s.

Say that Sup(g) is small if it has at most 8εlog slog n parts and big otherwise.



Claim: If Sup(g) is small then the largest part has size at least n− 33ε

log slog n

This is again proved by showing that if P has fewer than 8εlog slog n parts and

all of them are smaller than n − 33ε

log slog n , then there are too few

permutations in Stab(P), i.e.

n!

|Stab(P)|> s



Claim: Sup(g) is small.

Suppose that g is a minimal gate (in the DAG-order of the circuit) withSup(g) large.

We can show that this implies that g has a large number of immediatepredecessors which (by assumption) have small support.

Using the bounds from the previous claims, we can find a large enoughsubset of these, and independently combine automorphisms that movethem.

This is used to show that Orb(g) must be bigger than s.


Translating Symmetric Circuits to Formulas

Given a polynomial-time function n 7→ Cn that generates symmetriccircuits:

1. There are formulas of FP interpreted on ([n], <) that defines thestructure Cn.

2. We can also compute in polynomial time, Orb(g) and Sup(g) foreach gate g .

3. These can be turned into tuples of elements labelling the gates, withsome duplication.

4. With these as labels for gates, the edge relation of Cn can beexpressed in terms of just equality.

5. Evaluate circuit on unordered universe (in FP for a Boolean circuit,in FPC for one with threshold gates.)


FP with Rank Operators

FPrk is fixed-pont logic with an operator for matrix rank over finite fields.(D., Grohe, Holm, Laubner, 2009)

We have, as with FPC, terms of element sort and numeric sort.

We interpret η(x , y)—a term of numeric sort—in G = (V ,E )as defining a matrix with rows and columns indexed by elementsof V with entries η[a, b].rkx,yη is a term denoting the number that is the rank of thematrix defined by η(x , y).

To be precise, we have, for each finite field Fq (q prime), an operator rkq

which defines the rank of the matrix with entries η[a, b](modq).


Choiceless Polynomial Time

Choiceless Polynomial Time with counting (CPT(Card)) is a class ofcomputational problems defined by (Blass, Gurevich and Shelah 1999).

It is based on a machine model (Gurevich Abstract State Machines) thatworks directly on a graph or relational structure (rather than on a stringrepresentation).

The machine can access the collection of hereditarily finite sets with thevertices of the graph as atoms, and can perform counting operations.

CPT(Card) is the polynomial time and space restriction of the machines.


Beyond FPC

FPrk can express the CFI property and solvability of systems of linearequations on finite fields. (D., Grohe, Holm, Laubner, 2009)

CPT(Card) can express the CFI property (but requires sets of unboundedrank). (D.,Richerby, Rossman, 2008)

The relationship between the two (and their relationship to P) remainsopen.


Big Picture

Logic Circuits

FP on structures with a disjointnumber sort ([n], <).

Poly-size symmetric Boolean cir-cuits.

Additional predicates on numbersort.

Non-uniformity(of function n 7→ Cn).

Connections between element sortand number sort(FPC and FPrk).

Additional gates(counting and rank).

CPT(Card). Breaking symmetry (how?).


symmetric circuits and fixed-point logicsad260/talks/aachen3.pdf · 2013. 11. 11. · symmetric...

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