switching lab manual

8/10/2019 Switching Lab Manual

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Digital Logic & Design Lab

ECE dept, Kalasalingam University

1

KALASALINGAM

UNIVERSITY(AAAA AA A A

A)

A : 20112012

: 291

:

//B : //

: 003

: 2

: .

: .

.

1. Pre-requisite:

B

.

2. Objectives:

3. Learning outcome and end use:

. & .


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2

4. Lesson Plan:

1 3 3

2 A 3 6

3 3 9

4 3 12

5 3 15

6 2 3 18

3 21

7 3 24

8 3 27

9 10 3 30

10 3 33

11 4 A 3 36

12 B 3 39

3 42

5. Portions for Model exams I, II:

6. Evaluation Plan:

20 %

20 %

50 %

B 10 %

. /

(..)


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3

EX.NO:1 Realization of Logic Gates

Aim:

To Realize the Logic gates (AND, OR, NOT, NAND, NOR and EX-OR gate

using 74XX ICs.

Apparatus Required:

Sl.No Component Type Quantity

1 Trainer Kit - 1

2 AND Gate IC 7408 13 OR Gate IC 7432 1

4 NOT Gate IC 7404 1

5 NAND Gate IC 7400 1

6 NOR Gate IC 7402 1

7 EX-OR IC7486 1

8 Connecting wires - Required

Theory:

Logic Gates:

The logic gate is the basic building block in digital systems. Logic gates

operate with binary numbers. Gates are therefore referred to as binary logic gates. All

voltages used with logic gates will be either HIGH or LOW. A HIGH voltage will mean abinary 1. A LOW voltage will mean a binary 0. Remember that logic gates are electronic

circuits. These circuits will respond only to HIGH voltages (called 1s) or LOW (ground)

voltages (called Os).

AND Gate:

A basic AND gate consists of two inputs and an output. If the inputs are A, BX,

the output (often called Y) is on only if all the inputs A, BX are also on.

Y= AANDBANDCANDX

Where A, B, N are the input variables and Y is the output variable. The

variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1.

For example, for anANDoperation the gate opens (Y = 1) only, when all the inputs are

present.

OR Gate:

A basic OR gate consists of two inputs and an output. If the inputs are A, BX,the output (often called Y) is on, if one the inputs A, BX is on.


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4

Y= A ORB ORC ORX = A+B+C +N

Where A, B, N are the input variables and Y is the output variable. The

variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1.For example, for an OR operation the gate opens (Y = 1), when one of the input is

present.

NOT Gate:

A NOT gate is also called an inverter. A NOT gate, or inverter, is an unusual gate.

The NOT gate has only one input and one output.

Y =NOTA. =A

The process of inverting is simple. The input is always changed to its opposite. If the

input is 0, the NOT gate will give its complement, or opposite, which is 1. If the input tothe NOT gate is a 1, the circuit will complement it to give a 0.

NANDGate:

NANDGate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operationsNOT andAND, namely theNANDoperation.

________

Y = A B N

Digital signals are applied at the input terminals A, B, CN. The output is

obtained at the output terminal marked Y. The NANDoperation is defined as: the output

of an NAND gate is 0 if and only if all the inputs are 1. It is the inverse of the ANDoperation. TheNAND gate is known to be one of the Universal gates.

NOR Gate:

NOR Gate is a circuit which performs, the logic or Boolean operation derived

from the basic logic operationsNOT and OR, namely theNORoperation.

___________

Y = A +B+ +N

Digital signals are applied at the input terminals A, B, CN. The output isobtained at the output terminal marked Y. TheNORoperation is defined as: the output of

anNORgate is 1 if and only if all the inputs are 0. It is the inverse of the OR operation.

TheNOR gate is known to be one of the Universal gates.

EX-OR Gate:

The exclusive-OR gate is referred to as the any but not all gate or "one or the

other but not both". The exclusive-OR term is often shortened to read as XOR. The

XOR gate is enabled only when an odd number of 1s appear at the inputs. The XOR gate

could be referred to as an odd-bits check circuit.

Y = AEX-NOR B

= A BX


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5

Design:

AND Gate:

Truth Table:

Logic Diagram: Pin Diagram:

OR Gate:

Truth Table:

Logic Diagram:

Pin Diagram:

INPUT OUTPUT

A B Y0

0

1

1

0

1

0

1

0

0

0

1

INPUT OUTPUT

A B Y0

0

1

1

0

1

0

1

0

1

1

1


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6

NOT Gate:

Truth Table:


NAND Gate:

Truth Table:


INPUT OUTPUT

X Y

01

10

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

1

1

0


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7

NOR Gate:

Truth Table:

Logic diagram: Pin Diagram:

EX-OR Gate:

Truth Table:

INPUT OUTPUT

A B Y

0

0

1

1

0

1

0

1

1

0

0

0

INPUT OUTPUT

A B Y

0

0

11

0

1

01

0

1

10


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8


Procedure:1. Connections are made as per the circuit given.

2.

The Low level input is grounded.3.

The HIGH level input is connected to the +5V supply.

4. Observe the output various combination of inputs.

Result:


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9

EX.NO:2 Adders and Subtractors

Aim:

To realize the adder and Subtractor using logic gates and to verify the truth table.

Apparatus Required:

Theory:

Half Adder:

A combinational circuit that performs the addition of two bits is called a half-

adder. This circuit needs two binary inputs and produces two binary outputs. One of theinput variables designates the augend and other designates the addend. The output

variables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:

Sum S = BABA + = BA

Carry C = AB

Where A and B are the two input variables.

Truth Table:

Logic Expression:

Sum S = BABA +

Carry C = AB


1 Trainer Kit - 1

2 AND Gate IC 7408 2

3 OR Gate IC 7432 1

4 EX-OR IC7486 2

5 NOT IC 7404 1


INPUT OUTPUT

A B SUM CARRY

0

0

11

0

1

01

0

1

10

0

0

01


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10

Logic Diagram:

A

B

SUM

CARRY

74LS86A

1

2

3

74LS08

1

2

3

Full Adder:

A combinational circuit that performs the addition of three bits is called a half-

adder. This circuit needs three binary inputs and produces two binary outputs. One of the

input variables designates the augend and other designates the addend. Mostly, the third

input represents the carry from the previous lower significant position. The outputvariables produce the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:

Sum = CBA

Carry Cout= AB + BC+ CA

Where a,b & cin are the three input variables.

Truth Table:

Logic Expression:

Sum S = CBA

Carry C = AB + AC + BC

INPUT OUTPUT

A B C SUM CARRY0

00

01

1

1

1

0

01

10

0

1

1

0

10

10

1

0

1

0

11

01

0

0

1

0

00

10

1

1

1


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11

Logic Diagram:

C

A

B SUM

CARRY

74LS86A

4

5

6

74LS08

1

2

3

74LS86A

1

2

3

74LS32

4

5

6

74LS08

10

9

8

74LS08

4

5

6

74LS32

1

2

3

Half subtractor:

A half subtractor is a combinational circuit that subtracts two binary inputs and

produces their difference. It also has an output to specify if a 1 has been borrowed. Thecircuit has two inputs, one representing the Minuend bit and the other Subtrahend bit. The

circuits produces two outputs, then difference and borrow. The Boolean functions for the

tow outputs can be written as

D = YXYX + B = YX

Truth Table:

Logic Expression:

D = YXYX +

B = YX Logic Diagram:

INPUT OUTPUT

x Y Difference Borrow

00

1

1

01

0

1

01

1

0

01

0

0


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12

FULL SUBTRACTOR

A full subtractor is a combinational circuit that subtraction between two binary

inputs, taking into account that a 1 may have been borrowed by a lower significant sage.The circuit has three inputs, representing the minuend bit, the Subtrahend bit and the

previous borrow bit respectively. The two outputs, d and b represent the difference &

output borrows. The Boolean functions for the tow outputs can be written as

D = XYZZYXZYXYZX +++

B = YZZXYX ++

Truth Table:

Logic Expression:

D = XYZZYXZYXYZX +++

B = YZZXYX ++

Logic Diagram:

INPUT OUTPUT

x y z Difference Borrow0

0

001

1

1

1

0

0

110

0

1

1

0

1

010

1

0

1

0

1

101

0

0

1

0

1

110

0

0

1


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13

Procedure:

1. The adder and subtractor circuits are designed using the Boolean function whichis found out from the truth tables.

2. Connections are made as per the circuit given.

3. The Low level input is Grounded and the HIGH level input is connected to the

+5V supply.4. Observe the output various combination of inputs.

Result:


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14

EX.NO:3 Multiplexer and Demultiplexer

Aim:

To realize the multiplexer and demultiplexer circuit using logic gates and to verify

the truth table.

Apparatus Required:

4:1 Multiplexer:

Theory:A multiplexer or mux is a device that performs multiplexing; it selects one of

many analog or digital input signals and forwards the selected input into a single line. A

multiplexer of 2n inputs has n select lines, which are used to select which input line to

send to the output.

Truth table:

InputsSelect Lines Output

S0 S1 Y

I0 0 0 I0

I1 0 1 I1

I2 1 0 I2

I3 1 1 I3

Logic Expression:

=Y103102101100 SSISSISSISSI +++


1 Trainer Kit - 1

2 AND Gate( 3 input) IC 7411 3

3 OR Gate IC 7432 1

4 NOT Gate IC7404 1



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15

Logic Diagram:

S0 S1

I0

I1

I2

I3

Y

74LS11

11

810

9

74LS11

3

64

5

74LS04

3

4

1

2

74LS11

1122

13

74LS11

1

122

13

74LS32

10

9

8

74LS32

4

5

6

74LS32

1

2

3

1:4 Demultiplexer:

Theory:

The de-multiplexer performs the reverse operation of a multiplexer. It is acombinational circuit which accepts a single input and distributes it over several outputs.

The number of output lines is n and the number of select lines is 2n lines. De-

multiplexer ICs may have an enable input to control the operation of the unit. When theenable input is in a given binary state (the disable state), the outputs are disabled, and

when it is in the other state (the enable state), the circuit functions as normal de-

multiplexer. The size of the de-multiplexer is specified by the single input line and the

number 2nof its output lines.

Truth table:

Select Lines Output

S0 S1 Y1 Y2 Y3 Y4

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 01 1 0 0 0 1

Logic Expression:

=0Y 10 SSI

=1Y 10 SSI

=2Y 10 SSI

=3Y 10SSI


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Logic Diagram:

S1S0II

Y1

Y2

Y3

Y4

74LS04

3

4

74LS04

1

2

74LS11

11

810

9

74LS11

3

64

5

74LS11

1

122

13

74LS11

1

122

13

Procedure:

1. The Multiplexer and demultiplexer circuit is designed and the Boolean

function is found out.


+5V supply.

3. The inputs and selection lines are given from the input switches.

4. Connections are made as per the circuit given

5. Observe the output for various combinations of inputs.

RESULT:


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17

EX.NO:4 Decoders and Encoders

Aim:

To realize the Encoder and Decoder circuit using logic gates and to verify the

truth table.

Apparatus Required:

ENCODER:(8:3)

Theory:

An encoder has 2n (or fewer) input lines and n output lines. The output lines

generate the binary code corresponding to the input value. In encoders, it is assumed thatonly one input has a value of 1 at any given time. The encoders are specified as m-to-n

encoders where m 2n.

Truth Table:

D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1


1 Trainer Kit - 1

2 OR Gate IC 7432 3

3 AND gate(3 input) IC7411 24 NOT gate IC 7404 1



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18

Logic Diagram:

B

A

C

D0D1D2D3D4D5D6D7

74LS32

13

12

11

74LS32

10

9

8

74LS32

13

12

11

74LS32

4

5

6

74LS32

1

2

3

74LS32

1

2

3

74LS32

4

5

6

74LS32

10

9

8

74LS32

1

2

3

DECODER :( 2:4)

Theory:

A decoder is a combinational circuit that converts binary information from ninput lines to a maximum of 2nunique output lines. It performs the reverse operation of

the encoder. If the n-bit decoded information has unused or dont-care combinations, the

decoder output will have fewer than 2noutputs. The decoders are represented as n-to-m

line decoders, where m 2n. Their purpose is to generate the 2

n(or fewer) minterms of n

input variables. The name decoder is also used in conjunction with some code converterssuch as BCD-to-seven-segment decoders. Most, if not all, IC decoders include one or

more enable inputs to control the circuit operation. A decoder with an enable input can

function as a de-multiplexer.

Truth Table:

INPUTS OUTPUTS

DIN X Y D0 D1 D2 D31

1

1

1

0

0

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1


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Logic diagram:

X YDIN

D0

D1

D2

D3

74LS11

10

89

11

74LS11

3

64

5

74LS04

1

2

74LS11

1

122

13

74LS11

1

122

13

74LS04

1

2

Procedure:

1. The Encoder and Decoder circuit is designed and the Boolean function is found

out.


+5V supply.3. Connections are made as per the circuit given.


Result:


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EX.NO:5 Code Converters

Aim:

To realize the code converterusing logic gates and to verify the truth table.

Apparatus Required:

Theory:

The availability of a large variety of codes for the same discrete elements of

information results in the use of different codes by different digital system. It is

sometimes necessary to use the output of one system as the input to another. A

conversion circuit must be inserted between the two systems if each uses different codesfor the same information. Thus, a code converter is a circuit that makes the two systemscompatible even though each uses a different binary code. To convert from binary code A

to binary code B, the input lines must supply the bit combination of elements as specified

by code A and the output lines must generate the corresponding bit combination of codeB. A combinational circuit which performs this transformation by means of logic gates is

known to be Code Converter. Some of the examples for the code converters are,

BCD to XS3 Converter

XS3 to BCD Converter


1 Trainer Kit - 1

2 AND Gate IC 7408 2

3 3-i/p AND Gate IC 7411 14 OR Gate IC 7432 2

5 EX-OR IC7486 1

5 NOT gate IC 7404 2



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21

Logic Diagram:

BCD to XS3 Converter:

Truth Table:

BCD CODE EXCESS 3 CODE

B3 B2 B1 B0 E3 E2 E1 E0

0

00

0

0

00

0

1

1

0

00

0

1

11

1

0

0

0

01

1

0

01

1

0

0

0

10

1

0

10

1

0

1

0

00

0

0

11

1

1

1

0

11

1

1

00

0

0

1

1

00

1

1

00

1

1

0

1

01

0

1

01

0

1

0

Logic Diagram:

B3 B2 B0B1

E0

E1

E2

E3

74LS04

3

4

74LS04

1

2

74LS08

13

12

11

74LS08

10

9

8

74LS08

4

5

6

74LS04

11 10

74LS04

9

8

74LS04

5

6

74LS08

1

2

3

74LS32

10

9

8

74LS32

4

56

74LS32

1

2

3

74LS86A

1

2

3


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XS3 to BCD Converter

Truth Table:

EXCESS 3 CODE BCD CODE

E3 E2 E1 E0 B3 B2 B1 B0

0

00

0

0

1

1

11

1

0

11

1

1

0

0

00

1

1

00

1

1

0

0

11

0

1

01

0

1

0

1

01

0

0

00

0

0

0

0

01

1

0

00

0

1

1

1

10

0

0

01

1

0

0

1

10

0

0

10

1

0

1

0

10

1

Logic Diagram:

E3 E2 E1 E0

B0

B2

B3

B1

74LS04

3

4

74LS04

1

2

74LS04

9

8

74LS04

5

6

74LS08

4

5

6

74LS11

3

645

74LS11

1

122

13

74LS08

1

2

3

74LS86A

1

2

3

74LS11

11

810

9

74LS32

10

9

8

74LS32

4

5

6

74LS32

1

2

3


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23

Procedure:

1. The code converters circuits are designed using the Boolean function which isfound out from the truth tables.



+5V supply.4. Observe the output for various combinations of inputs.

Result:


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24

EX.NO:6 2 bit Magnitude comparator

Aim:

To design a magnitude comparator using basic logic gates and verify the truthtable.

Apparatus Required:

Theory:

A magnitude comparator is a combinational circuit that compares the magnitude

of two numbers (A,B) and generates one of the following outputs.

1. A=B

2. A>B

3. AB

2. If A1 is less than B1 then AB

5. If A0 is less than B0 then A


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25

Truth table:

Inputs Outputs

A1 A0 B1 B0 A>B A=B A


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26

Logic diagram:

A0A1 B0B1

A>B

A=B

A


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27

EX.NO.7 Parity Checkers and Generators

Aim:To implement the odd and even parity checkers using the logic gates and also to

generate the odd parity and even parity numbers using the generators.

Apparatus required:

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checker:

Theory:

It counts the number of 1s in the given input and produces a 1 in the output when

the number of 1s is odd.

Logic Diagram:

A

B

C

DODD PARITY

74LS86A

10

9

8

74LS86A

4

5

674LS86A

1

2

3

Even parity checker:

Theory:

It counts the number of 1s in the given input and produces a 1 in the output whenthe number of 1s is even.

Logic Diagram:

A

B

C

DODD PARITY EVEN PARITY

74LS86A

10

9

8

74LS86A

4

5

674LS86A

1

2

3

74LS04

1 2


1 Trainer Kit - 1

5 EX-OR IC7486 1

5 NOT gate IC 7404 1



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28

Odd parity generator:

Theory:

It generates an odd parity number. The odd parity checker circuit is used with theinverted output and also the input bits. So when the input is a 4-bit number then the

output of the generator circuit will have 5 bits which is an odd parity number.

Logic Diagram:

A

AB

B

C

C

D

D

PARITY BIT

74LS86A

10

9

8

74LS86A

4

5

6

74LS86A

1

2

3

74LS04

1 2

Even parity generator

Theory:

It generates an even parity number. The even parity checker circuit is used withthe inverted output and also the input bits. So when the input is a 4-bit number then the

output of the generator circuit will have 5 bits which is an even parity number.

Logic Diagram:

A

B

B

A

C

C

D

D

PARITY BIT74LS86A

1

2

3

74LS86A

4

5

6

74LS86A

10

9

8

Procedure:1. The circuit is implemented using logic gates.2. The inputs are given as per the truth table.

3. The corresponding outputs are noted.

4. The theoretical and practical values were verified.


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29

TRUTH TABLE:

Input Checker output Generator output

A B C D odd even odd even

0 0 0 0 0 1 00001 00000

0 0 1 1 0 00010 00011

0 0 1 0 1 0 00100 00101

0 0 1 1 0 1 00111 00110

0 1 0 0 1 0 01000 01001

0 1 0 1 0 1 01011 01010

0 1 1 0 0 1 01101 01100

0 1 1 1 1 0 01110 01111

1 0 0 0 1 0 10000 10001

1 0 0 1 0 1 10011 100101 0 1 0 0 1 10101 10100

1 0 1 1 1 0 10110 10111

1 1 0 0 0 1 11001 11000

1 1 0 1 1 0 11010 11011

1 1 1 0 1 0 11100 11101

1 1 1 1 0 1 11111 11110

Result:


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30

EX.NO:8 Ripple Counters and MOD 10

countersAim:

To Realize the Ripple Counter and MOD 10 counter using IC 74XXs and toverify the truth table.

Apparatus required:

Ripple Counter:

Theory:

In a ripple counter, the flip-flop output transition serves as a source for triggering

other flip-flops. In other words, the Clock Pulse inputs of all flip-flops (except the first)

are triggered not by the incoming pulses, but rather by the transition that occurs in other

flip-flops. A binary ripple counter consists of a series connection of complementing flip-

flops (JK or T type), with the output of each flip-flop connected to the Clock Pulse input

of the next higher-order flip-flop. The flip-flop holding the LSB receives the incomingcount pulses. All J and K inputs are equal to 1. The small circle in the Clock Pulse /Count

Pulse indicates that the flip-flop complements during a negative-going transition or when

the output to which it is connected goes from 1 to 0. The flip-flops change one at a timein rapid succession, and the signal propagates through the counter in a ripple fashion. A

binary counter with reverse count is called a binary down-counter. In binary down-

counter, the binary count is decremented by 1 with every input count pulse.

State Table:

Input Output

Clk Reset A B C D

1 1 0 0 0 01 0 0 0 0 1

1 0 0 0 1 0

1 0 0 0 1 1

1 0 0 1 0 0

1 0 0 1 0 1

1 0 0 1 1 0

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 0 0 1


1 Trainer Kit - 1

2 J-K Flip Flop IC 7476 4

3 AND (2 input) IC 7408 24 OR gate IC 7432 1

Connecting wires - Required


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31

1 0 1 0 1 0

1 0 1 0 1 1

1 0 1 1 0 0

1 0 1 1 0 1

1 0 1 1 1 1

Logic Diagram:

Pin diagram:


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32

MOD 10 counter:

Theory:

A decade counter is one that counts in decimal digits, rather than binary. Adecimal counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the 7490 integrated circuit did) or other binary encodings (such as the

bi-quinary encoding of the 7490 integrated circuit). Alternatively, it may have a "fully

decoded" or one-hot output code in which each output goes high in turn; the 4017 was

such a circuit. The latter type of circuit finds applications in multiplexers and

demultiplexers, or wherever a scanning type of behavior is useful. Similar counters with

different numbers of outputs are also common. The decade counter is also known as amod-10 counter.

Truth Table:

COUNT OUTPUTS

Q0 Q1 Q2 Q3

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

Logic diagram:


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33

Procedure:

1. The Ripple counter and mod 10 Counter circuit is designed.2. The Low level input is Grounded and the HIGH level input is connected to the

+5V supply.

3. The clock Signal is applied from the trainer kit.4. Connections are made as per the circuit given.


Result:


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34

EX.NO:9 Synchronous Counters

Aim:

To Realize the synchronous counter using IC 74XXs and to verify the truth table.

Apparatus required:

Ring counter:

Theory:

A ring counter is a circular shift register with only one flip-flop being set at ay

particular time; all others are cleared. The single bit is shifted from one flip-flop tot the

other to produced the sequence of timing signals.

Logic Diagram:

Truth Table:

Input Output

Clk Reset Qa Qb Qc Qd

1 1 1 0 0 0

1 0 0 1 0 0

1 0 0 0 1 0

1 0 0 0 0 1

1 0 1 0 0 0


1 Trainer Kit - 1

2 D Flip Flop IC 7474 2



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Johnson counter:

Theory:

A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ringcounter, or Moebius counter) is a modified ring counter, where the output from the last

stage is inverted and fed back as input to the first stage.[1][2][3]

A pattern of bits equal inlength to twice the length of the shift register thus circulates indefinitely. These counters

find specialist applications, including those similar to the decade counter, digital toanalogue conversion, etc.

Logic Diagram:

Procedure:

1. The Ring and Johnson Counter circuit is designed.

2. The Low level input is Grounded and the HIGH level input is connected to the+5V supply.



Truth Table:

Input Output

Clk Reset Qa Qb Qc Qd

1 1 1 0 0 01 0 1 1 0 0

1 0 1 1 1 0

1 0 1 1 1 1

1 0 0 1 1 1

1 0 0 0 1 1

Result:


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36

EX.NO:10 Shift Registers

Aim:

To Realize the Shift Registers using IC 74XX Ics and to verify the truth table .

Apparatus required:

Theory:

Introduction

Shift registersare a type of sequential logic circuit, mainly for storage of digitaldata. They are a group of flip-flops connected in a chain so that the output from one flip-

flop becomes the input of the next flip-flop. Most of the registers possess nocharacteristic internal sequence of states. All the flip-flops are driven by a common

clock, and all are set or reset simultaneously.In this chapter, the basic types of shift registers are studied, such as Serial In -

Serial Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and

bidirectional shift registers. A special form of counter - the shift register counter, is also

introduced.

Serial In - Serial Out Shift Registers:

A basic four-bit shift register can be constructed using four D flip-flops, as shown

below. The operation of the circuit is as follows. The register is first cleared, forcing allfour outputs to zero. The input data is then applied sequentially to the D input of the first

flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to

right. Assume a data word to be 1001. The least significant bit of the data has to beshifted through the register from FF0 to FF3.

Serial In - Parallel Out Shift Registers:

For this kind of register, data bits are entered serially in the same manner as

discussed in the last section. The difference is the way in which the data bits are taken

out of the register. Once the data are stored, each bit appears on its respective output line,

and all bits are available simultaneously.


1 Trainer Kit - 1

2 D Flip Flop IC 7474 2



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37

Parallel In - Serial Out Shift Registers:

A four-bit parallel in - serial out shift register is shown below. The circuit uses Dflip-flops and NAND gates for entering data (ie writing) to the register D0, D1, D2 and

D3 are the parallel inputs, where D0 is the most significant bit and D3 is the leastsignificant bit. To write data in, the mode control line is taken to LOW and the data is

clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is

active high. The register performs right shift operation on the application of a clock

pulse, as shown in below.

Parallel In - Parallel Out Shift Registers:

For parallel in - parallel out shift registers, all data bits appear on the parallel

outputs immediately following the simultaneous entry of the data bits. The followingcircuit is a four-bit parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the

register is clocked, all the data at the D inputs appear at the corresponding Q outputssimultaneously.

Serial In - Serial Out Shift Registers:

Truth Table:

Logic Diagram:

CLK PULSE FF0 FF1 FF2 FF3 OUTPUT

0 0 0 0 0 01 1 0 0 0 0

2 0 1 0 0 0

3 0 0 1 0 0

4 0 0 0 1 1


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Serial In - Parallel Out Shift Registers:

Truth Table: input sequence is 1001

Logic Diagram:

Parallel In - Parallel Out Shift Registers:

Truth Table:

INPUT CLK OUTPUT

1 1 0 1 1 1 1 0 1

Logic Diagram:

CLK PULSE FF0 FF1 FF2 FF3 OUTPUT

0 0 0 0 0 0

1 1 0 0 0 0

2 1 0 0 0 0

3 1 0 0 0 0

4 1 0 0 1 1


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PIN DIAGRAM :

Procedure:

1. The Johnson Counter circuit is designed and the Boolean function is found out.2. Connections are made as per the circuit given.


+5V supply.4. Observe the output for various combinations of inputs.

Result:


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40

EX.NO:11 4 bit adder and subtractors

Aim:

To design and implement 4 bit adder/ Subtractor using ic7483 and to verify the

truth table.

Apparatus required:

Theory:The four bit adder / subtractors performs the operation of both addition and

subtraction. The add/sub control connected with Cinof the lowest significant it of fulladder is used to perform the addition and subtraction.

To perform subtraction, the ADD/SUB is kept high. Subtraction is performed by

using 2,s complement method. The inverted input is given through EX-OR gate. To

perform addition, the ADD/SUB line is kept low.

Logic diagram:


1 Trainer Kit - 1

2 4 bit adder IC 7483 1

4 EX-OR Gate IC 7486 2



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41

Pin details of IC 7483:

Truth table:

ADD/SUB A4 A3 A2 A1 B4 B3 B2 B1 C4 4 3 2 1

0

0

0

0

1

1

1

1

1

0

1

1

0

1

1

1

0

0

1

1

1

1

0

1

1

1

1

1

1

1

0

1

0

1

1

1

1

1

1

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

1

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

0

1

0

0

1

1

0

0

1

1

0

0

0

1

1

1

0

1

1

0

1

0

1

0

0

0

0

1

0

0

1

1

1

0

0

0

0

Procedure:1. The circuit is implemented using logic gates.

2. The logic inputs are given as per the truth table.

3. The outputs are observed.

4. Compare the theoretical and practical value and verify it.

Result:


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42

EX.NO:12 BCD ADDERS

Aim:

To design and implement the BCD adder using IC 7483 and to verify the truth

table.

Apparatus required:

Theory:

A BCD adder adds two BCD digits and produces sum also in BCD.BCD number

uses 10 symbols.

1. Add 2 four bit numbers using binary addition.2. If four bit sum is equal to or less than 9, the sum is valid BCD number and no

correction is needed.

3. If sum is greater then 9, add 6 to sum to produce valid BCD symbol.

Logic diagram:


1 Trainer Kit - 1

2 4 bit binary adder IC 7483 2

3 OR Gate IC 7432 1

4 AND Gate IC 7408 15 Connecting wires - Required


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Truth table:

SUM Correction

Required

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 01 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Pin Diagram:

Procedure:

1. Construct the circuit as per logic diagram.2. Set the logic inputs as per the truth table.

3. Observe the outputs.

4. Compare the outputs and verify the truth table.

Result:

switching lab manual

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