switched capacitors converters - bgupel/seminars/apec09.pdf · prof. sam ben-yaakov, switched...

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [1]

Power Electronics LaboratoryDepartment of Electrical and Computer Engineering

Ben-Gurion University of the NegevP.O. Box 653, Beer-Sheva 84105, ISRAEL

Phone: +972-8-646-1561; Fax: +972-8-647-2949;Email: sby@ee. bgu.ac.il; Website: www.ee.bgu.ac.il/~pel

APEC09, February 2009

Sam Ben-Yaakov

Full set of slides: http://www.ee.bgu.ac.il/~pel/seminars/APEC09.pdf

Switched Capacitors Converters


1. Introduction (30min)Switched capacitors versus switched inductors convertersCharge Pumps and Switched Capacitors convertersLosses in switched capacitors converters – overview Examples of SCC and charge pump topologies

OUTLINE

2. Losses in Hard Switched SCC (50 min)Target voltagesEquivalent resistanceEfficiencyInherent power lossEffect of switch resistancesEquivalent-circuit based average models – New ApproachRegulationExamples


3 Losses in Soft Switched SCC - New Results (50 min)TopologiesWaveforms of resonant networksLosses in resonant networksParasitic Equivalent-circuit based average modelsRegulation Examples

4 Self-Adjusting Binary SCC (50 min) - New ConceptThe conceptThe Extended Binary (EXB) numbers representationFeatures of the EXBTranslating the EXB to SCC topologiesProof of solution Examples –simulation – experimental resultsEfficiency – output resistanceRegulation Examples5. Q&A

OUTLINE


Needed in all modern systemsExcept: incandescent lamps, heaters…

Power Conversion Objective


Linear Voltage Regulator

inout II ≅

inin

outout

in

out

IVIV

PPη

⋅⋅

==

since

in

out

VVη =


Switched inductor

Lossless process

Lossy process

Switched capacitor

Types of Switching DC-DC Converters


1QV+=2

CVE2

10

2CVE

22

1 =

( )2ΔVCΔEEE

21

01 ==−

Inherent Energy Loss due to ΔVFor complete charge/discharge

21 VV ≠

12 VVΔV −=

2VC

2VCE

222

211

0 +=

( )2

ΔVCC

CCΔEEE2

21

2101 +

==−

( )21

22211

1 CC2)VCV(CE

++

=

Lossyprocess

112 VVVC )( −=Q

Independent of parasitic resistances

1V 2V

SwC2C1

Rp


Lossless Switching Lossy switching

Types of the Switching DC-DC Converters


Advantages

No magnetic elements Minimal EM interferences Can be fabricated as IC

DisadvantagesDisadvantages

Inherent power losses Relatively large number of switchesHigh inrush current at start-up

Relevancy of the Switched Capacitor Converters (SCC)


Target voltage

⇓

= inTRout VV k

TRout

out

VV

=η

The input voltage is divided or multiplied by k

The losses are emulated by equivalent resistor Req

The concept of Equivalent Circuit


TΔVC

TVVCI 1outin

1avg =−

=

11avgeq Cf

1CT

IΔVR

⋅===

( ) ( )21

eq

2

eq ΔVCfRΔVP ⋅==

The output capacitor is sufficiently largeThe output voltage is averaged to DCThe charge/discharge process is completed

Independent of parasitic resistances

Output Resistance in Charge Transfer(The switched capacitor approximate approach)


Output Resistance- Doubler


Output Resistance- Doubler

What is going on???To be completely deciphered in this seminar


Target VoltagesNo-Load No-Loss

Target Voltages

VinVout

VcVoutVcVcVcVinVout

VcVcVc

41

1321

321

=

=−−−=

==

VinVout

VcVoutVcVcVcVout

VcVcVc

43

1321

321

=

=++=

==

Vin43ageTargetVolt =

Vin41ageTargetVolt =

Solution of algebraic equations


43

VV3;N

41

VV3;N

32

VV2;N

31

VV2;N

21

VV1;N

in

out

in

out

in

out

in

out

in

out

==

==

==

==

==

Number of target voltage ratios is limited

Target voltage ratios are spread apart

N=number of capacitors

Multiple Target Voltage Ratios


Maximum efficiency at the fixed voltage ratios: 2/3 and 1/2

Can it be improved ?

Commercial SC Converters


Soft Switched SCC

Sinusoidal rather than exponential currentsClaimed to be of low lossSoft switching – does it help reduce losses?


Classic Dickson’s charge pump

Using diodes


Dickson’s charge pump

Using MOSFETs as diodes



Using MOSFETsas switches



Operational modes


Charge-pump/Switched-capacitor

The same operation principle


Charge-pump/Switched-capacitor

Many other modern charge pump topologies


2. Losses in Hard Switched SCC

Features of the new model presented here:

Average modelRelating the losses to the output currentGeneric – applicable to practically any SCCCan take into account output capacitorTakes into account diode lossesUnified – applicable to hard and soft switched SCCHas it’s own limitations….


The Generic Charging/Discharging Process

∫ ∫⋅== −1t

0

1t

0

2t/τ2

RR dteR

ΔVdtPE

ReΔVRi(t)P

2t/τ22

R−⋅

=⋅=

( )2β2

R e12

CΔVE −−⋅

= τtβ 1=

RCτ;eRΔVi(t) RC

t

=⋅=−

ΔV≡ Voltage difference before switch closure

ER= Energy dissipated during switch closure time t1

ESR1S RRR +=

1:1 converter



( )τ

β 12β2

R ;e12

CΔVE t=−

⋅= −

2CΔVE1βFor

2R

⋅=→>>

Energy Dissipated in each switching period

12

0βR tRΔVE =→

...x1e0x

x +=→


The Generic Charging/Discharging ProcessRelating the losses to capacitor’s current

Average current through capacitor

∫⋅=−1t

0RC

t

c dteRΔVQ

( )βsout(avg) e1CΔVfI −−⋅⋅=

(avg)Csc 1IfQ =⋅

)e(1Cf

IΔV β

s

(avg)C1−−⋅

=

)e(12

CΔVE 2β2

R−−⋅

⋅=

t0

tτ0 t1

t1

iC

iCΔVR

ΔVR


The Generic Charging/Discharging ProcessEnergy lost per switching period

)e(12C

)e(1Cf

IE 2β

2

βs

C(avg)R

−−

−⋅⋅⎟⎟⎠

⎞⎜⎜⎝

⎛

−⋅=

)2

coth(2C

CfI

)e(1)e(1

2C

CfI

E2

s

(avg)Cβ

β2

s

(avg)CR

11 β⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−

+⋅⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛= −

−

)e(1)e(1

)e)(1e(1)e)(1e(1

)e(1)e(1

β

β

ββ

ββ

2β

2β

−

−

−−

−−

−

−

−

+=

−−

+−=

−

−x

x

e1e1

2xcoth −

−

−

+=⎟

⎠⎞

⎜⎝⎛

RC1DeadTime

2f1β

s⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛−=Taking into account deadtime



Energy lost per switching cycle

)2

coth(2C

CfI

)e(1)e(1

2C

CfI

E2

s

(avg)Cβ

β2

s

(avg)CR

11 β⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−

+⋅⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛= −

−

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

++

−

+⋅⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1IP

2

2

1

1

β

β

β

β

s

2C(avg)R(avg)

S

gdischarginchargingT

EEP

+=

( ) ( ) ( )avgCavgCavgC III21

==

CRtβ1

11 =

CRtβ2

22 =

ESR2s2

ESR1s1RRR

RRR+=

+=

Relating the losses to capacitor’s current


SCC Equivalent Resistance1:1 converter

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛⋅⋅=

2coth

Cf1IPs

2out(avg)R(avg)

β

)e(1)e(1

Cf1

2coth

Cf1R β

β

sseq −

−

−

+⋅=⎟

⎠⎞

⎜⎝⎛⋅=

β

inTRGout VV =

βββ 11 ==Assuming


SCC Equivalent ResistanceLimits β→ ∞

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡

−+

+−+

⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1R

2

2

1

1

β

β

β

β

seq

Cf1Rs1e =>>β

Complete charge/discharge RC<<Ts

RCTD s1

1 =βRCTD s2

2 =β

Independent of RHigh losses (large rms currents)The classical solution

tτ0 t1


SCC Equivalent Resistance

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−−

−+βe1

βe1β

)e1()e1(R2

)e1()e1(

CRf2R2R

se β−

β−

β−

β−

−

+⋅β=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−

+⋅=

For t1= t2=Ts/2

R4R 0e =→β

)e(1)e(1

Cf1R β

β

seq −

−

−+

⋅=

RCTs

2=β

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡

−+

+−+

⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1R

2

2

1

1

β

β

β

β

seq

Why??

Incomplete charge/discharge RC>>Ts; β→0


SCC Equivalent ResistanceBehavior

For t1 = t2=Ts/2R4R 0e =→β

R4)I(R)I*2( 20

2o ⋅=

RCTs

2=β

( ) ( )R

s

s2out

s2out

R T2T2I

2T2I

P+⋅

=

RRe 40

=→β


1

10

2

0.1 1 10f

Re

SCC Equivalent ResistanceFrequency dependence

( )( ) ⎥

⎥

⎦

⎤

⎢⎢

⎣

⎡

−−

−+

s

s

f1e1

f1e1

sf1

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡

−+

+−+

⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1R

2

2

1

1

β

β

β

β

seq

sRCf21

=β

⎭⎬⎫

⎩⎨⎧

⎥⎦

⎤⎢⎣

⎡−+

⋅= −

−

)e(1)e(1

Cf1R β

β

seq

12

1=

RC


SCC Equivalent Resistance

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−−

−+βe1

βe1β

For t1= t2=Ts/2 RCTs

2=β

Incomplete charge/discharge RC>>Ts; β→0

Sizing C

sRf21C >

)e1()e1(R2

)e1()e1(

CRf2R2R

se β−

β−

β−

β−

−

+⋅β=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−

+⋅=

1RC2Ts <=β


10

0.1 1 10

20

f

Re

D=0.5 D=0.4D=0.3

D=0.2

SCC Equivalent ResistanceEffect of Duty Cycle

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡

−+

+−+

⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1R

2

2

1

1

β

β

β

β

seq

⎭⎬⎫

⎩⎨⎧

⎟⎠⎞

⎜⎝⎛+⎟

⎠⎞

⎜⎝⎛⋅=

2coth

2coth

C2f1R 11

seq

ββ⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

−

++

−

+−

−

−

−

s

s

s

s

fD-1

fD-1

fD

fD

s e1

e1

e1

e1f1

12

1=

RC


SCC Equivalent ResistanceEffect of duty cycle β→0

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎦

⎤⎢⎣

⎡

−+

+−+

⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1R

2

2

1

1

β

β

β

β

seq

⎭⎬⎫

⎩⎨⎧

⎟⎠⎞

⎜⎝⎛+⎟

⎠⎞

⎜⎝⎛⋅=

2coth

2coth

C2f1R 11

seq

ββ

RCfD

s

=1βRCfD

s

−=

12β

⎭⎬⎫

⎩⎨⎧

+⋅=21s

eq22

C2f1R

ββ

⎭⎬⎫

⎩⎨⎧

−+=

DR

DR

1Req

( )DD1RR

0eq −=

→β


Re as a function of Duty Cycle

RD)(1D1

IRD

DI

P2

out2

outR ⋅−⋅⎟

⎠

⎞⎜⎝

⎛−

+⋅⋅⎟⎠

⎞⎜⎝

⎛=

Explanation

e2out

2outR RI

D1R

DRIP =⎟

⎠⎞

⎜⎝⎛

−+=

D)D(1R

D1R

DRR e −

=−

+=


Simulation/Experimental Demonstartion

Mosfets S1, S2: IRF840, Rdson = 0.85Ω, C = 1μFVin = 24V; Vout_theoretical = 24V; RL = 100Ω || 1K Ω ~ 91Ω or 1KΩ; Duty Cycle = 0.5;

Power Level: 6.3 Watts (max)



RL =91 Ω200KHz 20KHz

Vout= 15.49V64% Efficiency

Vout= 22.58V94% Efficiency



Vin = 24V; Vout_target = 24VRL ~ 91Ω;

Rs = 3.35Ω; fs = 200KHz;

D = 0.5; Vout = 20.58V;


Simulation/Experimental Demonstration

D = 0.7; Vout = 19.94V; D = 0.9; Vout = 14.456V;


SCC Equivalent ResistanceGeneralization

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

++

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

+⋅⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1IP

2

2

1

1

ii β

β

β

β

s

2(avg)C(avg)C

( )ieCoCi RIP ⋅= 2

∑=

=n

1ieCe i

RR

)(avgoutiC IkIi

=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

++

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

+⋅⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1kR

2

2

1

1

i β

β

β

β

s

2Ce

Ci = flying capacitor iτ = time constant of charge/discharge loop

2,1

2,12,1 τ

βt

=


SCC Equivalent Resistance1/2 converter

)(C2)(C1)(o lll avgavgavgut +=

COut IOut

CVIn

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−

+⋅= β−

β−

)e1()e1(

Cf1kRs

2e

2211

11CRCR

=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−

+⋅= β−

β−

)e1()e1(

Cf1

41R

se

2/12

ll )(o

)(C =→= kavgutavg


SCC Equivalent ResistanceExample

11

11

4/13

ττττ

=≠

==+

practiceIngeneralIn

kIII outCC

Assuming equal size capacitors⎭⎬⎫

⎩⎨⎧

−+

⋅= −

−

)1()1(1

161

β

β

ee

CfR

siCe

⎥⎥⎦

⎤

⎢⎢⎣

⎡

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−

+⋅= β−

β−

)e1()e1(

Cf1

1613R

sTe


Including Finite Output Capacitor

2,1

2,12,1

tτ

β =

( )⎭⎬⎫

⎩⎨⎧

+++=τ

o1

o1oESRESR1S2 CC

CCRRR

( ) 1ESR2S1 CRR +=τ

∑=

=n

1ieCe i

RR

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

++

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

+⋅⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1kR

2

2

1

1

i β

β

β

β

s

2Ce

Including Co (could be neglected in practical cases)

oRoC

oV1C

S2S1

inVESRR

S1R S2Ri(t)

ESR(out)R


Including diodesStep up X3

IC=ID =Iout(avg)



⎥⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+⎟⎟

⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅

++⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅⋅

⋅=

2β

coth22β

coth2β

cothC

CC2β

coth2C2f

1R (4)(3)(2)

out

out(1)

Seq

C/22ESR)(Rtβ

1

2(1) ⋅+

=⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅

⋅++=

CCCC

)ESRESR(R

tβ

out

outout1

2(2)

CESR)(Rtβ

1

1(3) ⋅+

=C/22ESR)(R

tβ1

1(4) ⋅+

=

inTRG V3V ×=


Including diodes/SimulationStep up X3

Rout = 1000Cout = 100uC_init = 23.22Vin = 10C_fly = 1uFR1 = 1mESR = 10mESR_out = 100mV_forward = 1DeadTime = 10nf_s = 100kk_2 = ((Cout + C_fly) / Cout)beta _1 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ 2*ESR) * (C_fly/2)))beta _2 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1 + ESR + ESR_out) * (Cout * C_fly /(C_fly + Cout)) ))beta _3 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ ESR) * C_fly))beta _4 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ 2*ESR) * (C_fly/2)))coth_1 = (1 + exp(-beta_1)) / (1- exp(-beta_1))coth_2 = (1 + exp(-beta_2)) / (1- exp(-beta_2))coth_3 = (1 + exp(-beta_3)) / (1- exp(-beta_3))coth_4 = (1 + exp(-beta_4)) / (1- exp(-beta_4))Req = ((1 / (2 * f_s * C_fly)) * (2 * coth_1+ k_2 * coth_2 + coth_3 + 2 * coth_4))

PSIM Parameters file



100k10n110m10m100m1μ10100μ1000

fS[Hz]

DeadTime[sec]

Vforward[V]

ESRout[Ω]

ESR[Ω]

R1[Ω]

Cfly[F]

Vin[V]

Cout[F]

Rout[Ω]

time


Complications

100k10n110m10m101μ10100μ1000

fS[Hz]

DeadTime[sec]

Vforwa

rd[V]

ESRo

ut[Ω]

ESR[Ω]

R1[Ω]

Cfly[F]

Vin[V]

Cout[F]

Rout[Ω]


Coupled Loops

R1 is shared by two loopsSmall effect in practical cases


Output Voltage Regulation

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

++

⎥⎥⎦

⎤

⎢⎢⎣

⎡

−

+⋅⋅= −

−

−

−

)e(1)e(1

)e(1)e(1

2Cf1kR

2

2

1

1

i β

β

β

β

s

2Ce

Variable frequency control (increases output voltage ripple)Frequency dithering (increases output voltage ripple)Variable loop resistanceDuty Cycle control (high operating frequency)Global PWM (increases output voltage ripple)Switching VTRG (increases complexity)

RCTD s1

1 =βRCTD s2

2 =β


Output Voltage RegulationUp converter: x2, x1.5


Interim Summary

Expressing losses as a function of capacitor's currentGeneric average modelLimitsDuty cycle effectGeneralizationRegulation


3. Losses in Soft Switched SCC

Analysis follows that of hard switched SCCExpressing losses as a function of output currentGeneralizingComparison to hard switched SCC

Model building approach


t)sin(ωeLω

ΔVi(t) dtα

d⋅⋅

⋅= ⋅−

21Q >

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−⋅

⋅=

−dωα2π2

R(res) e12

CΔVE

Rt)(ωsineLω

ΔVRi(t)P d2t2α

2

d

2R ⋅⋅⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=⋅= ⋅−

2LRα =

220

2d αωω −=

LC1ω0 =

∫ ⋅⋅⋅

⋅=∫= ⋅−dπ/ω

0d

2t2α22

d

2dπ/ω

0RR(res) t)dt(ωsine

LωRΔVdtPE

IndESR1S RRRR ++=

ΔV≡ Voltage difference before switch closure

ER(res)= Energy dissipated per switch closure

Generic Resonant Charging/Discharging Process


⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−⋅

⋅=

−dωα2π2

R(res) e12

CΔVE2LRα =

220

2d αωω −=

LC1ω0 =

Energy Dissipated in each switching period

)e(12

CΔVE dζ2π2

R(res)⋅−−⋅

⋅=

RLω

Q dd =

L2ωR

2Q1ζ

ddd ==



Relating the losses to the output current

Average current through a capacitor

∫ ⋅⋅

= ⋅−dπ/ω

0d

tα

dc t)dtsin(ωe

LωΔVQ

)e(1CQΔV

dπζc

−+⋅=

)e(12

CΔVE dζ2π2

R(res)⋅−−⋅

⋅=

(avg)1Csc IfQ =⋅

)e(1Cf

IΔV

dπζs

(avg)1C−+⋅

=

)e(1CΔVfI dπζsout(avg)

−+⋅⋅⋅=


)e(1ΔVCΔVQ dπζc

−+⋅=



)e(12C

)e(1Cf

IE d2π

2

dπζs

(avg)1CR(res)

ζ−−

−⋅⋅⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

+⋅=

⎟⎠

⎞⎜⎝

⎛⋅⋅⎟⎟⎠

⎞⎜⎜⎝

⎛=

+

−⋅⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−

−

2πζ

tanh2C

CfI

)e(1

)e(12C

CfI

E d2

s

out(avg)dπζ

dπζ2

s

out(avg)R

)e(1)e(1

2xtanh x

x

−

−

+

−=⎟

⎠⎞

⎜⎝⎛

)e(1

)e(1

)e)(1e(1

)e)(1e(1

)e(1

)e(1dπζ

dπζ

dπζdπζ

dπζdπζ

2dπζ

dπζ2

−

−

−−

−−

−

−

+

−=

++

+−=

+

−




⎟⎠

⎞⎜⎝

⎛⋅⋅⎟⎟⎠

⎞⎜⎜⎝

⎛=

2πζ

tanh2C

CfI

E d2

s

out(avg)R

S

gdischarginchargingT

EEP

+=

2)2,1(

d(1,2) 21ω ⎟⎟

⎠

⎞⎜⎜⎝

⎛−=

LR

LC ⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

+

−+

+

−⋅⋅=

−

−

−

−

)e(1

)e(1

)e(1

)e(12Cf

1IP)2(

)2(

)1(

)1(

s

2C(avg)R(avg) d

d

d

d

πζ

πζ

πζ

πζ

( ) ( ) ( )avgCavg2Cavg1C III ==Ind

Ind

R

R

++=

++=

ESR2S2

ESR1S1

RRR

RRR

L2ωRζ

d1

1d(1) =

L2ωR

ζd2

2d(2) =



Resonant SCC Equivalent Resistance

)e(1

)e(1Cf

12

tanhCf

1Rss

eq d

ddπζ

πζπζ−

−

+

−⋅=⎟

⎠

⎞⎜⎝

⎛⋅=

⎭⎬⎫

⎩⎨⎧

⎟⎠

⎞⎜⎝

⎛⋅⋅=2πζ

tanhCf

1IP d

s

2out(avg)R(avg)

1:1 converter

gdischargincharging QQ =

In steady state

out(avg)(avg)C(avg)C III21

==

inTRGout VV =

d(2)d(1) ζζ =For


Resonant SCC Equivalent ResistanceDependence on fs

)e(1

)e(1Cf

12

tanhCf

1Rss

eq d

ddπζ

πζπζ−

−

+

−⋅=⎟

⎠⎞

⎜⎝⎛⋅=

1:1 converter

Losses decrease as 1/fs up to the limit: fs=ωd/2 π


Comparing Hard and Soft SCC Losses

⎟⎠⎞

⎜⎝⎛ πζ

⋅=+

−⋅= πζ−

πζ−

2tanh

Cf1

)e(1)e(1

Cf1R d

sseq

d

d

πω

≤2

f ds

⎟⎟⎠

⎞⎜⎜⎝

⎛ α=

sshardeq f2coth

Cf1R

2)2,1(

d(1,2) 21ω ⎟⎟

⎠

⎞⎜⎜⎝

⎛−=

LR

LC

L2ωRζ

d1

1d(1) = L2ω

Rζ

d2

2d(2) =

⎟⎠⎞

⎜⎝⎛ β

⋅=−

+⋅= −

−

2coth

Cf1

)e(1)e(1

Cf1R

sβ

β

seq RCf2

1s

=β

Soft

Hard

Unified

⎟⎟⎠

⎞⎜⎜⎝

⎛ α=

sssofteq f2tanh

Cf1R

L4RSoft =α→

RC21Hard =α→


Comparing Hard and Soft SCC LossesLimits

R4Rhardeq =

( )R5

2R

LCf8RR

2

2s

softeq ≈π

==

( )1d >>ζ

fs→ ∞

0 2 4 61

2

3

4

5

1 e β−+( )1 e β−−( )

β

For high Q soft switched SCC

R52RR

2

softeq ≈π

=

0Rsofteq →

R→ 0

Cf1Rshardeq →



oRoC oVC

S2S1

inV

ESRR

S1R S2Ri(t)

L

IndR

Mosfets S1, S2: IRF840, Rdson = 0.85Ω, C = 1μFVin = 24V; Vout_theoretical = 24V; RL = 100Ω || 1K Ω ~ 91Ω; Duty Cycle = 0.5;Power Level: 5.5 Watts (max)



RL = 91ΩL = 2.3 μHy

Q = 1.8

100 KHz 20 KHz

Vout = 22V Vout = 16.1V

Efficiency = 67%Efficiency = 91.7%



RL = 91ΩL = 0.5 μHy

Q = 0.9

100 KHz 20 KHz

Vout = 21.2V Vout = 15.4V

Efficiency = 88.3% Efficiency = 64.2%


Resonant SCC Equivalent Resistance

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥⎦

⎤

⎢⎢⎣

⎡

+

−+

+

−⋅⋅=

−

−

−

−

)e(1

)e(1

)e(1

)e(12Cf

1IPd(2)πζ

d(2)πζ

d(1)πζ

d(1)πζ

s

2(avg)iC(avg)iC

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

+

−+

+

−⋅⋅=

−

−

−

−

)e(1

)e(1

)e(1

)e(12Cf

1kRd(2)πζ

d(2)πζ

d(1)πζ

d(1)πζ

s

2ieC

L2ωRζ

d(1,2)d(1,2) =

Generalization

ieC2outiC RIP ⋅=

∑=

=n

1ieCe i

RR

Ci = flying capacitor iζd = damping ratio of charge/discharge loop

2)2,1(

d(1,2) 21ω ⎟⎟

⎠

⎞⎜⎜⎝

⎛−=

LR

LC


Including Finite Output Capacitor

oRoCoV

C

S2S1

inV

ESRR

S1R S2Ri(t)

L

IndRESR(out)R

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

+

−+

+

−⋅⋅=

−

−

−

−

)e(1

)e(1

)e(1

)e(12Cf

1kRd(2)πζ

d(2)πζ

d(1)πζ

d(1)πζ

s

2ieCL2ω

Rζd(1,2)

d(1,2) =

2L

RRRR

CCCC

L

12L

RRRRζ

IndESR(out)ESR2S

out

out

IndESR(out)ESR2S(2)

+++−

+⋅

⋅

+++=

2L

RRR

LC12L

RRRζ

IndESR1S

IndESR1S(1)

++−

++=

Including Co (could be neglected in practical cases)


Including DiodesStep up x3

IC=ID =Iout(avg)



IC=ID =Iout(avg)

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛⋅+⎟⎟

⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅

++⎟⎟

⎠

⎞⎜⎜⎝

⎛⋅⋅

⋅=

2πζ

tanh22

πζtanh

2πζ

tanhC

CC2

πζtanh2

C2f1R (4)(3)(2)

out

out(1)

se

2L

R2RR

L(C/2)12L

R2RRζ

IndESR1S

IndESR1S(1)

++−

++=

2L

RRRR

CCCC

L

12L

RRRRζ

IndESR(out)ESR1S

out

out

indESR(out)ESR1S(2)

+++−

+⋅

⋅

+++=

2L

RRR

LC12L

RRRζ

IndESR2S

IndESR2S(3)

++−

++=

2L

2RR

L(C/2)12L

2RRζ

ESR2S

ESR2S(4)

Ind

Ind

R

R

++−

++=

inTRG V3V ×=



100k10n1μ1m1m03m1μ10100μ1K

fS[Hz]

DeadTime[sec]

Lr[Hy]

ESRout[Ω]

ESR[Ω]

Vforward[V]

Rr[Ω]

Cr[F]

Vin[V]

Cout[F]

Rout[Ω]

Q ~ 200


Including Diodes

Step up x3

Q ~ 5

100k10n1μ1m10m0150m2μ10100μ1K

fS[Hz]

DeadTime[sec]

Lr[Hy]

ESRout[Ω]

ESR

[Ω]

Vforward[V]

Rr[Ω]

Cr[F]

Vin[V]

Cout[F]

Rout[Ω]


The case of Coupled Loops

100k10n1μ1m1m011μ10100μ1K

fS[Hz]

DeadTime[sec]

Lr[Hy]

ESRou

t[Ω]

ESR[Ω]

Vforward[V]

R1[Ω]

C[F]

Vin[V]

Cout[F]

Rout[Ω]

Q ~ 1


Output Voltage Regulation

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

+

−+

+

−⋅⋅=

−

−

−

−

)e(1

)e(1

)e(1

)e(12Cf

1kRd(2)πζ

d(2)πζ

d(1)πζ

d(1)πζ

s

2ieC

Variable frequency control Frequency dithering Variable loop resistance Global PWM (increases output voltage ripple)

L2ωRζ

d(1,2)d(1,2) =

Regulation → Losses


2nd Interim Summary

Expressing losses as a function of capacitor's currentGeneric average modelLimitsGeneralizationRegulation


More target voltage ratios with same number of capacitors

Small ΔV between adjacent target voltage ratios

Self Adjusting Binary SCC Objective: To increase the number of target voltage ratios


Developing a novel Extended Binary

(EXB) number representation for

increased resolution

Translating the EXB sequences into

switched capacitor topologies

The Approach


For example Bn = 5/8

Negative powers of two are used

Resolution is defined by the LSB 1·2-n

1 0 1 0 2120 21 20 85 3210 →⋅+⋅+⋅+⋅= −−−

∑=

−=n

0j

jjn 2AB Aj = 0, 1

n – is the resolution

Theoretical Foundation of novel SCCBinary Fractions


5 = 0 + 4 + 0 + 1 → 0 1 0 15 = 0 + 4 + 2 − 1 → 0 1 1-15 = 8 + 0 − 2 − 1 → 1 0-1-15 = 8 − 4 + 0 + 1 → 1-1 0 15 = 8 − 4 + 2 − 1 → 1-1 1-1

For example:

∑=

=n

0j

jjn 2AZ

More than one code for a given ZN

Aj = -1, 0, 1n – is the resolution

Signed Binary Number Representation


A0 = 0, 1Aj = -1, 0, 1n – is the resolution

∑=

−+=n

1j

jj0n 2AAM

For numbers Mn in the range from 0 to 1

More than one code for a given Mn

For example5/8 = 0 1 0 1,

so that n = 3

EXB code

1 - 1- 0 1 22 0 1 85

1 0 1- 1 2 0 2 1 85

1- 1 1 0 22 2 0 85

3-2-

3-1-

-3-2-1

→−−+=

→++−=

→−++=

Number

Extended Binary (EXB) Representationdeveloped in this study


Example: 5/8 ⇒ 0 1 0 1,j = 3

Adding and subtracting 2-j keeps Mn unchanged

binary addition

replace the original 1 with -1

1- 0 1 0 1- 0 01- 0 0 10 1 0 01- 1 0

1-

1

+

+

0 1 1 -11 0 -1 -11 -1 1 -11 -1 0 1

Result:

↓↓ ↓↓

1-

1

1 1 0 1- 0 0 0 0 1 1 0 1 0 0 0

0 1 0

+

+

-3-2-10 2 2 2 2-3-2-10 2 2 2 2

0 1 0 1

Spawning the EXB Representation SequencesThe proposed algorithm


0 1 0 1

0 1 1 -11 0 -1 -11 -1 1 -11 -1 0 1

Example: n= 3, Mn= 5/8

Corollary 1:For any EXB number Mn in the range of 0 to 1 of

resolution n, the minimum number of EXB representations is n+1.

This is because each of the Aj =1 (j>0) in the original binary representation will generate a new representation.

Furthermore, each Aj =0 will turn into Aj =1 that can spawn a new representation.

Properties of the EXB representations


Corollary 2:For each Aj=1 (j>0) in an EXB representations of a

given number Mn , there will be at least one Aj=-1 in another sequence of same Mn.

This is because the generation process involves replacing “1” by a “-1”. 0 1 0 1

0 1 1 -11 0 -1 -11 -1 1 -11 -1 0 1

Example: n= 3, Mn= 5/8

Properties of the EXB representations


Example for n = 3

The number of the EXB representations is at least n+1There are “1” and “-1” placed in the same columns

Sequences of the EXB representations


The EXB representation attributes were used to develop

a new family of SC converters

Capacitors’ interconnections follow the EXB codes

Back to Switched Capacitor DC-DC Converter


Mn represents the desired output target voltage ratioEach EXB sequence of Mn is associated with a switched capacitors topologyA0 is associated with the input voltageEach Aj (j>0) is associated with a flying capacitor Cj

Polarity of Aj (j>0) indicates polarity of Cj connection

∑ −+=n

j

jj0n 2AAM

Translating the EXB to Capacitor Connections


The capacitors are always serially connected to the loadThe source is connected in series with the load (and capacitors) in opposite polarity

A0 – the voltage source1: connected0: disconnected

Aj – capacitor connection-1: charging0: disabled1: discharging

∑ −+=n

j

jj0n 2AAM

Translating the EXB to Capacitor Connections


For VC1=1/2Vin, VC2=1/4Vin, VC3=1/8Vin, the system is in steady state

All Topological Constraints for Vout = 3/8·Vin


There are at least n+1 topologies for each ratio Mn. (Corollary 1) The capacitors are charged and discharged (Corollary 2)

∑ −+=n

j

jj0n 2AAM

n=3

All Topological Constraints for Vout = 3/8·Vin


Is there an unique steady state solution?Convergence from start up (zero voltage across the capacitors)?Recovery from load step transient?

The perpetual EXB sequences of the converter

But…

The Self-Adjusting Property


⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=+++=++=+=++=+

o32

o321

o321in

o31

o31in

VVV 0 0

VVV-V0

VVV-V-V

VV - 0 V 0

VV - 0 V-V

For Mn= 3/8

∑ −+=n

j

jj0n 2AAM

Solution of linear equation by hardware!

The EXB as a System of Linear Equations


⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=++=+=+=+=+

0V-VV 0

0V-V - 0 V

-VV-V - 0 V-

0V-VV-V

-VV-VV-V-

o32

o31

ino31

o321

ino321

For n=34 unknowns: V0, V1, V2, V3

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=⋅⋅+⋅+⋅

=⋅⋅⋅+⋅

=⋅⋅⋅+⋅

=⋅⋅+⋅⋅

=⋅⋅+⋅⋅

0 1-11 0

0 1-1-0 1

-1 1-1- 01-

01- 1 1- 1

-11- 11- 1-

4321

4321

4321

4321

4321

xxxx

xxxx

xxxx

xxxx

xxxx

ino4

in33

in22

in11

VV

VV

VV

VV

x

x

x

x

====

Divide the system by Vin:

From Corollary 1:Number of equations at least n+1Number of unknowns n+1



⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

1- 1 1 0

1- 1- 0 1

1- 1- 0 1-

1- 1 1- 1

1- 1 1- 1-

A

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

4

3

2

1

xxxx

X

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

0

0

1-

0

1-

B

In the matrix form, vector X is the unknown weighted voltagesAX = B, where

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=⋅⋅+⋅+⋅

=⋅⋅⋅+⋅

=⋅⋅⋅+⋅

=⋅⋅+⋅⋅

=⋅⋅+⋅⋅

0 1-11 0

0 1-1-0 1

-1 1-1- 01-

01- 1 1- 1

-11- 11- 1-

4321

4321

4321

4321

4321

xxxx

xxxx

xxxx

xxxx

xxxx



⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

=

0 1- 1 1 0

0 1- 1- 0 1

1- 1- 1- 0 1-

0 1- 1 1- 1

1- 1- 1 1- 1-

A1

the augmented matrix

The Kronecker-Capelli theorem: A system has at least one solutionif and only if rank(A) = rank(A1)

A solution is unique if and only ifrank(A) = rank(A1) = the number of unknowns

Number of unknowns is 4rank(A) = rank(A1) = 4

For the voltage ratio Mn= 3/8

Solvability of the EXB Linear Equations

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

==

83814121

BAX 1-


At the steady state the capacitors keep the binary weighted voltages:

VC1 = 1/2∙Vin

VC2 = 1/4∙Vin

VC3 = 1/8∙Vin

Vout = 3/8∙Vin

The steady state solution follows the EXB sequence

Explicating of the Obtained Solution


The step-down case:

The step-up case:

Step up by replacing the functions of input and output

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=+++=++=+=++=+

in32

in321

in321o

in31

in31o

VVV 0 0

VVV-V0

VVV-V-V

VV - 0 V 0

VV - 0 V-V

⎪⎪⎪

⎩

⎪⎪⎪

⎨

⎧

=+++=++=+=++=+

o32

o321

o321in

o31

o31in

VVV 0 0

VVV-V0

VVV-V-V

VV - 0 V 0

VV - 0 V-V

Step up conversion


The capacitors need to have3 types of connections -1, 0, 1

Implementation


Microcontroller PIC18F452 (MICROCHIP) Quad bilateral CMOS switches MAX4678 (MAXIM)Ceramic Z5U dielectric capacitors 4.7μF (KEMET)

Experimental evaluation board


Ch.1: Output voltageCh.2: Input voltage Vertical scale: 1 V/divHorizontal scale: 10 ms/div

Simulation and Experimental Resultsfor Starting Up Circuit, Vout = 3/8·Vin

Vin=8V, Load resistor: 3.9 kΩ

Simulation Experiment


Mn= 3/8

Mn= 5/8

Efficiency at different Mn vs. Load resistor


ToutV

Tout

out

VV

=η

The losses are determined by an equivalent resistor Req

= Target voltage

Efficiency at target voltage


oeq

Soo RR

VRV

+=

oo

S RVV

eqR−

0yeq xR =−=

eqooo

S RRRVV

+=

bxy +=

Testing the Req concept


Req= 7.35 Ω

Rds(on)=1.2 Ω (each switch)

Supported by theoretical analysis

Experimental results for Mn=3/8

Zoom in


Voltage Ripple Reduction


Voltage ratios outside the target voltages

Two approaches examined

Dithering

Linear regulator (increasing Req)

Output voltage Regulation


Repetitive change of target voltage ratios

The output voltage is given by a “duty cycle” of dither

0.452

84

51

83

54

==⋅+⋅=in

out

VV

Output voltage Regulation by Dithering


Output ripple for Vin = 8V, Load resistor = 437 ΩVertical scale: 10 mV/div, Horizontal scale: 100 μS/div

Dithering between3/8 and 4/8 in 2:1 ratio

Output voltage ripple

Constant 3/8 ratio


Small power loss due to close target voltage ratiosLower output voltage ripple

Using a Linear Regulator for the LSB


Generalization to Other Number Systems

∑=

−+=n

1j

jj

00n rArArN )( r= radix

2722322313230313N 332103 /)( =⋅=⋅+⋅−⋅+⋅= −−−−−Example radix 3, 3 bits

Aj = jth digit Digit values= -(r-1)…-1, 0, 1,…(r-1) r-1 capacitors per digit



1041404/1 10 −− ⋅+⋅=

)4(N1

3143414/1 10 −⋅−⋅= −−

3043404/3 10 −− ⋅+⋅=

1141414/3 10 −⋅−⋅= −−

r= 4, one digit



Applying r=2 (binary) and 2 bits, only 2 capacitors are required (instead of 3)

Last printed slide


3rd Interim Summary

Binary SCCHigh efficiency in wide range of output to input

voltage ratios2n-1 target voltage ratios with n capacitors Binary resolution for the adjacent voltage ratiosRelatively large number of switches

Proposed representation by number systemCould help optimizing SCC topologies


Thanks for your attentionThanks for your attention

Losses in hard-switched SCC

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Proceedings - Electric Power Applications 2006, Vol. 153, Issue 1, pp. 105-115

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