Survey of Existing Survey of Existing Memory DevicesMemory Devices

Renee Gayle M. ChuaRenee Gayle M. Chua

IntroductionIntroduction

Dynamic RAM (DRAM)Dynamic RAM (DRAM) Most commonly used type of system memoryMost commonly used type of system memory Requires refreshing every few millisecondsRequires refreshing every few milliseconds Holds data for a very short timeHolds data for a very short time Less expensive than static RAMLess expensive than static RAM

IntroductionIntroduction These are the steps in order to access a cell in These are the steps in order to access a cell in

DRAM:DRAM:

A row command to latch in Row addressA row command to latch in Row address

A column command to latch in Column address A column command to latch in Column address

A necessary delay between the two commands as A necessary delay between the two commands as well as a delay after the column command for the I/O well as a delay after the column command for the I/O circuit to drive valid data. circuit to drive valid data.

IntroductionIntroduction Fast Page Mode (FPM) DRAMFast Page Mode (FPM) DRAM

Sending the row address just once for many Sending the row address just once for many accesses to memory in locations near each other, accesses to memory in locations near each other, improving access timeimproving access time

takes advantage of the fact that when cells within takes advantage of the fact that when cells within the same row are accessed, the row command the same row are accessed, the row command doesn’t need to be repeated. doesn’t need to be repeated. Page modePage mode - - operation mode where multiple operation mode where multiple

column commands follow a single row column commands follow a single row commandcommand

Burst mode accessBurst mode access - memory is not read one - memory is not read one byte at a time (32 or 64 bits at a time), but in byte at a time (32 or 64 bits at a time), but in several consecutive chunks of memoryseveral consecutive chunks of memory

FPM/EDO MemoryFPM/EDO Memory

Read Timing & Memory Access DiagramsRead Timing & Memory Access Diagrams

Synchronous DRAMSynchronous DRAM

SDRAM is designed to synchronize itself SDRAM is designed to synchronize itself with the timing of the CPU with the timing of the CPU

take advantage of interleaving and burst take advantage of interleaving and burst mode functions, which make memory mode functions, which make memory retrieval even faster. retrieval even faster.

SDRAM modules come in several different SDRAM modules come in several different speeds so as to synchronize to the clock speeds so as to synchronize to the clock speeds of the systems they'll be used in. speeds of the systems they'll be used in.

E.g. PC66 SDRAM runs at 66MHz; PC100 E.g. PC66 SDRAM runs at 66MHz; PC100 SDRAM runs at 100MHzSDRAM runs at 100MHz

Burst Mode FeatureBurst Mode Feature

Burst ModeBurst Mode Bursting is a rapid data-transfer technique Bursting is a rapid data-transfer technique

that automatically generates a block of data (a that automatically generates a block of data (a series of consecutive addresses) every time series of consecutive addresses) every time the processor requests a single address. the processor requests a single address.

The assumption is that the next data-address The assumption is that the next data-address the processor will request will be sequential to the processor will request will be sequential to the previous one. the previous one.

Important Timing TermsImportant Timing Terms

1.1. ttRPRP - The time required to switch internal memory banks. (RAS Precharge) - The time required to switch internal memory banks. (RAS Precharge) 2.2. ttRCDRCD - The time required between /RAS (Row Address Select) and /CAS - The time required between /RAS (Row Address Select) and /CAS

(Column Address Select) access. (Column Address Select) access. 3.3. ttACAC - The amount of time necessary to "prepare" for the next output in burst - The amount of time necessary to "prepare" for the next output in burst

mode. mode. 4.4. ttCACCAC - The Column Access Time. - The Column Access Time. 5.5. ttCLCL - (or CL) CAS Latency. - (or CL) CAS Latency. 6.6. ttCLKCLK - The Length of a Clock Cycle. - The Length of a Clock Cycle. 7.7. RASRAS - Row Address Strobe or Row Address Select. - Row Address Strobe or Row Address Select. 8.8. CASCAS - Column Address Strobe or Column Address Select. - Column Address Strobe or Column Address Select. 9.9. Read Cycle Time - The time required to make data ready by the next clock Read Cycle Time - The time required to make data ready by the next clock

cycle in burst mode. cycle in burst mode. Note #1: Note #1:  ttRACRAC (Random Access Time) is calculated as (Random Access Time) is calculated as ttRCDRCD + + ttCACCAC = =

ttRACRACNote #2:Note #2:    RASRAS and and CASCAS normally appear in technical manuals with an over- normally appear in technical manuals with an over-line as in line as in RASRAS or  or  CASCAS..

SDRAM Read CycleSDRAM Read CycleClock 1Clock 1: ACTIVATE the row by : ACTIVATE the row by

turning on /CS and /RAS. turning on /CS and /RAS. (place the proper row address (place the proper row address on the address bus – chip will on the address bus – chip will know which row you want to know which row you want to ACTIVATE.ACTIVATE.

Clock 3Clock 3: READ the column you : READ the column you want from the row you've want from the row you've ACTIVATED by turning on /CAS ACTIVATED by turning on /CAS while placing the column's while placing the column's address on the address bus.address on the address bus.

Clocks 5-10Clocks 5-10: The data from the : The data from the row and column that you gave row and column that you gave the chip goes out onto the the chip goes out onto the Data Bus, followed by a BURST Data Bus, followed by a BURST of other columns, the order of of other columns, the order of which depends on which which depends on which BURST MODE you've set. BURST MODE you've set. (More on BURST in a second).(More on BURST in a second).

ttCACCAC - The Column Access Time - The Column Access Time

ttRACRAC (Random Access Time) (Random Access Time)

Double Data Rate DRAMDouble Data Rate DRAM

the next generation SDRAM. the next generation SDRAM. DDR reads data on both the rising and falling DDR reads data on both the rising and falling

edges of the clock signal (SDRAM only carries edges of the clock signal (SDRAM only carries information on the rising edge of a signal)information on the rising edge of a signal)

Data transfer is then twice as fast: i.e. instead of Data transfer is then twice as fast: i.e. instead of a data rate of 133MHz, DDR memory transfers a data rate of 133MHz, DDR memory transfers data at 266MHz. data at 266MHz.

DDR is not backward compatible with SDRAM-DDR is not backward compatible with SDRAM-designed motherboardsdesigned motherboards

DDR DRAMDDR DRAM

Added circuitry: produces a data output strobe Added circuitry: produces a data output strobe (DQS) (DQS) syncs data output to the external clock syncs data output to the external clock allows DDR to transfer the results of a read on both clock edges. allows DDR to transfer the results of a read on both clock edges. Writes: DQS signal generated by the chipset's memory interface Writes: DQS signal generated by the chipset's memory interface

to sync the write data to both edges of the clockto sync the write data to both edges of the clock

Rambus DRAMRambus DRAM

A revolutionary step from SDRAMA revolutionary step from SDRAM Has changes to the bus structure and how signals Has changes to the bus structure and how signals

are carriedare carried Rambus memory sends less information on the Rambus memory sends less information on the

data bus (which is 18 bits wide as opposed to the data bus (which is 18 bits wide as opposed to the standard 32 or 64 bits) but it sends data more standard 32 or 64 bits) but it sends data more frequently. frequently.

It also reads data on both the rising and falling It also reads data on both the rising and falling edges of the clock signal, as DDR does. As a edges of the clock signal, as DDR does. As a result, Rambus memory is able to achieve effective result, Rambus memory is able to achieve effective data transfer speeds of 800MHz and higher. data transfer speeds of 800MHz and higher.

Rambus DRAMRambus DRAM

Each RAMBUS chip has only 16 data pins Each RAMBUS chip has only 16 data pins on it, just like an SDRAM chip, which is on it, just like an SDRAM chip, which is enough to spit out only two bytes at a time. enough to spit out only two bytes at a time.

How, then, does an RDRAM provide full How, then, does an RDRAM provide full system bandwidth with only 16 data pins? system bandwidth with only 16 data pins?

Multiplexing is the key to RAMBUS' Multiplexing is the key to RAMBUS' excellent granularity and low pin count excellent granularity and low pin count

• Multiplexor: sits in between the DRAM core's 16-byte internal data bus and the two, single-byte Data A and Data B buses that make up the two-byte wide RAMBUS data channel. • These muxes take data in 8-byte wide chunks off of the two internal buses and stream them a byte at a time down the 1-byte wide Data A and Data B buses.

RDRAMRDRAM

RDRAM READ:

The data from the banks travels over the two, 8-byte core buses, is multiplexed onto the Data A and Data B buses, and then travels out the 16 data pins and onto the 16-bit data bus towards the CPU.