summary of data handling meeting: daq and controls lhcb plenary meeting 17 september 1998 beat jost...
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Summary of Data Handling Meeting:DAQ and Controls
LHCb Plenary Meeting17 September 1998Beat JostCern/EP
Contents
Introduction Summary of DAQ activities
Readout Unit Project Event Building Project TFC Project Event Filter Farm
Controls
Introduction:DAQ Architecture
Trigger Level 2 & 3Event Filter
Read-out Network (RN)
RU RU
SFC
Control &
Monitoring
SFC
CPU
CPU
RU
CPU
CPU
2-4 GB/s
4 GB/s
20 MB/sVariable latency
L2 ~10 msL3 ~200 ms
LA
N
Sub-Farm Controllers (SFC)
Read-out units (RU)
Timing&
FastControl
Front-End Electronics
VDET TRACK ECAL HCAL MUON RICH
LHC-B Detector
L0
L1
Level 0Trigger
Level 1Trigger
40 MHz
1 MHz
40 kHz
Fixed latency 3.2 ms
Variable latency <256 ms
Datarates
40 TB/s
1 TB/s
Front-End Multiplexers (FEM)1 MHz
Front End Links
Storage
Introduction:Hardware Components
Hardware Components Timing and Fast Control (TFC) Front-End Multiplexers (FEM) Readout Units (RU) Event Building Network Sub-Farm Controllers Filter Farm
}Event Building Strategy
Trigger Level 2 & 3Event Filter
Read-out Network (RN)
RU RU
SFC
Control &
Monitoring
SFC
CPU
CPU
RU
CPU
CPU
2-4 GB/s
4 GB/s
20 MB/sVariable latency
L2 ~10 msL3 ~200 ms
LA
N
Sub-Farm Controllers (SFC)
Read-out units (RU)
Timing&
FastControl
Front-E nd Electronics
VDE T TRACK ECAL HCAL MUON RICH
LHC-B Detector
L0
L1
Level 0Trigger
Level 1Trigger
40 MHz
1 MHz
40 kHz
Fixed latency 3.2 ms
Variable latency <256 ms
Datarates
40 TB/s
1 TB/s
Front-E nd Multiplexers (FEM)1 MHz
Front End Links
Storage
Readout Unit Project
PCI bus
embeddedCPU
D ata Merger DM
Sub-event Buffer
Subevent Builder SEB LA N
CPU memorybus
DPM
DM-FPG A
Readout Netw ork Interface
Network Link
SEB-FPGA
Input Links
Output Link
Throttle Full
Architecture
CPU
PCI bus
inputconnectors
ReadoutNetworkInterface
outputconnector
DPM
Sub-
even
tbu
ilder
Memorybus
FPG
A
LAN
DPM_Full
64
64
64
64
64
32
D ata M erger
32
32
32
64-bit
The architectureis scalable
8 or 16FPGA
4*16 bit
16
1
8+32
32
Mux 8>32
RN
PCI-Lan chip
Readout Unit
Input Stage blowup
Readout Unit
Data Formats
Event Number
Data Size
Source Id
Data 1
Data 2
...
Data n
Status CRC
32 Bits
Status CRC
Event Number
Data Size
Source Id
Data 1
Data 2
...
Data m
32 Bits
Event Number
Data Size
Source Id
Data 1
Data 2
...
Data n
Data 1
Data 2
...
Data m
Status CRC
It is assumed that the data is self-describing
Event-Building Project
Aim is to devise an event building strategy for LHCb Activities
Evaluation of Myrinet 2 PCI Interfaces and one switch ordered
• Material received 2 PCs ordered
• 1 received
Modeling of Myrinet (Finnish Students) Reproduced Results (obtained using Ptolemy) with Foresight Small systems (4x4) for the time being
Other technologies will also be evaluated if necessary
Timing and Fast Control (TFC)
Technical note in preparation (ready end of the month?)
General Architecture Readout Supervisor Block Diagram
We need to find manpower to put into the TFC sub-system
General TFC Architecture
ODE
TTCrx ADC
DSP
FEchipFEchipL1buffCtrl
L1
FEchip
LHCb trig
L-1
TTCtx
Switch
LHCClock
DAQthrottle
FEE
TTCrx
L0 trigger data
L1 trigger data
DAQ system
Det
ecto
r si
gnal
s
Con
trol
sys
tem
Slow Contr ol F low
Clock, Tr igger Flow
Data Flow
FEchipFEchipFEchip
Clk,L0,RST
Readout SupervisorFan-out
ReadoutSupervisor
L-0
L0
L1
Switch
ReadoutSupervisor
Subdett rig.
L0
L1
gL0gL1
TTC opt icalf an-out
FEchipFEE
TTCrx
ODE
TTCrx ADC
DSP
FEchipFEchipFEchip
FEchipFEchipL1buff
Clk,L0,RST
Ctrl
L1
TTCtx
Fanout TT
Ctx
ReadoutSupervisor
Subdett rig.
L0
L1
gL0gL1
Readout Supervisor Block Diagram
ControlInterface
Counters
TTC EncodingTTCrxTTC
OR OR
Self Triggers,Resets
Clk
gL1gL0
AND AND
L1L0
L1 Inhibit
L0 Inhibit
to TTCtx
CTRL
Front-EndModel,Rules
L0 Pipeline
L1 Buffer
to DAQ
Resets
Event Filter Farm
Common project between LHC experiments being set up
LHCb participation is currently very minor (~0), we are just following the activities. More active participation would probably be welcome….
Controls
Joint Project between LHC Experiments and IT/CO Finished or currently active of sub-projects
Technology Market Survey of available commercial Control Systems
• Supervisory Control And Data Acquisition (SCADA) tools Choice of Test Stand facilities for in-depth evaluation
Architecture Design for Experiment Control Systems (including DAQ Controls)
Level 3 Alarm Transmission at CERN
Small Hands-On Projects ATLAS TRT gas system test setup : WAGO + I/O modules via Profibus ALICE HPMID Cooling System: Siemens PLCs and Bridgeview
CANbus evaluation (especially in view of preferences inside Atlas - LMBs)
Eye on Fieldbuses in General Continuing Study of Use of PLCs (contacts with Working group on PLCs, which
has issued recommandations for 3 brands of PLCs for CERN)
Controls
Identified future sub-projects Standardization of High Voltage Controls Evaluation of the OPC (OLE for Process Control)
Standard Feasibility Study for ComponentWare Magnet Controls Rack Controls Communication with LHC
pre-alarms (things leading to emergencies) environment parameters (temperatures, leaks, opacity
(=smoke),…) machine parameters
Controls
General State of Health of Joint Project Project is gaining momentum and real work is being done. Cause
for (guarded) optimism that a joint Control System can be done. What is required from the LHCb collaboration?
Quite some experience from LEP experiments available in the JCOP project, so the standard control questions for an LHC exp. well answered. The URD that was produced for ALICE/LHCb serves as a basis.
BUT: in case of specific control needs or specific hardware equipment that you expect to use, please keep in contact with Pere or Wolfgang. Please do NOT postpone this issue until later … and later…
and…any participation in joint project and its sub-projects very welcome
Conclusion
DAQ Hardware good progress in RU project starting activity on event building
need manpower for TFC more participation in Filter Farm project welcome
Software, I.e. Controls Joint project seems to be in good shape LHCb involved in a number of sub-projects new sub-projects being launched external participation welcome
Plan to organize a DAQ/Controls Workshop in near future