1

WelcometothisMScLabExperiment.AllmyteachingmaterialsforthisLab-basedmodulearealsoavailableonthewebpage:

www.ee.ic.ac.uk/pcheung/teaching/MSc_Experiment/

TheQRcodehereprovidesashortcuttogotothecoursewebpage.

2

ThisLabExperimentiscompulsoryanditsgoalistoensurethatALLstudentsonthiscoursegettoalevelofcompetenceindigitaldesign,VerilogandFPGAsasexpectedwithourMScgraduates.IfyouarealreadyexperiencedwithVerilogand/orFPGAs,youwillfindthisexperimentquiteeasy.However,ifyouhavenotdoneeitherinyourUGdegreeprogramme,thisisagreatchanceforyoutocatchup.ThisLaboratoryservedasa“levelling”purpose– makesurethatallstudentsonthecoursereachacommonlevelandstandardindigitaldesign.Thelearningoutcomesforeachofthefourpartsare:Part1: BasiccompetenceinusingIntel/Altera’sQuartusdesignsystemsforCyclone-VFPGA;appreciatethesuperiorityofhardwaredescriptionlanguageoverschematiccapturefordigitaldesign;useofcasestatementtospecifycombinatorialcircuit;usehigherlevelconstructsinVerilogtospecifycomplexcombinatorialcircuits;developcompetenceintakingadesignfromdescriptiontohardware.Part2: UseVerilogtospecifysequentialcircuits;designofbasicbuildingblocksincluding:counters,linear-feedbackshift-registerstogeneratepseudo-randomnumbers,basicstatemachines;usingenablesignalstoimplementgloballysynchronisation.Part3: Understandhowdigitalcomponentscommunicatethroughsynchronousserialinterface;interfacingdigitalcircuitstoanaloguecomponentssuchasADCandDAC;useofblockmemoryinFPGAs;numbersystemandarithmeticoperationssuchasaddersandmultipliers;digitalsignalgeneration.Part4: UnderstandhowtoimplementaFIFOusingcountersaspointerregistersandBlockRAMasstorage;implementarelativelycomplexdigitalcircuitusingdifferentbuildingblocksincluding:counters,finitestatemachines,registers,encoder/decoder,addresscomputationunit,memoryblocks,digitaldelayelements,synchronisersetc.;learnhowtodebugmoderatelycomplexdigitalcircuits.

3

Youwouldhavebeentaughtatleasthowtoimplementdigitalcircuitsusinggatessuchastheoneshownhere.YoucanstillbuythischipwithFOURNANDgatesinonepackageandthisisknownasdiscretelogic.Wegenerallydonotusetheseanymore.Itisslow,expensive,consumeslotsofenergyandveryhardtouse.

Nevertheless,itisgoodtolearnaboutNANDandNORgatesbecause,usingDeMorgan’stheorem,youcouldintheorydesignandimplementaPentiummicroprocessorusingusetwoinputNANDorNORgatesalone.Itisthereforecouldberegardedasthebuildingblockofalldigitalcircuits.Similarly,youcouldintheorybuildacarusingonlybasicLegoblocks.Unfortunatelysuchacarwouldnotbeverygood.

4

Inearlydaysofintegratedcircuits,designersstartedusingrowsofbasicgates(shownasthedarkstuffherearrangedinrows).Theseareeithercompletelycustomised(full-custom)oritismadewithstandardrowsofgatesbutleavingthegatesunconnected.Foraspecificdesign,thegatesareconnectthroughwiresinthewiringchannels.Thereforethecustomisationisonlyinthewiringmetallayersandnotthelayerswithtransistors.Thisisknownas“semi-custom” application-specificintegratedcircuits(ASICs).

5

Ofcourseyoucanalsocustomiseeverything– eachtransistorandeachwiringconnectinafull-custommanner.HereisthelayoutofInteli7microprocessor(with4cores).Designingsuchacircuitisveryexpensive,highlyrisky,andoncedesigned,itcannotbechanged.

Mostapplicationsinelectronicindustrycannotaffordtoembarkonsuchadesign.ThisdrivestheriseoftheFieldProgrammableGateArray.

6

SowhatisanFPGA?YoucameacrosstheideaofProgrammableLogicDeviceinthefirstyear,wheretheusercanprogramwhatthelogicgatedoes(beitaNANDorNORorsomeformofSUM-of-PRODUCTimplementation)oranadder,youasauser,can“program” thechiptoperformthatlogicfunction.Nowwecanaddanotherlayerofuserprogrammability– youcanprogramhowtheselogicgatesareconnectedtogether!Inthatway,wehaveageneralprogrammablelogicchip.Unlikethemicroprocessorwheretheprogramisjusttheinstructiontofixdigitalhardware,hereyoucanprogramthehardwareitself!

ThefirstFPGAwasintroducedbyXilinxin1985.Ithasarraysoflogicblockswhichareprogrammable.ItissurroundedbyPROGRAMMABLEROUTINGRESOURCES,whichallowstheusertodefinetheinterconnectionsbetweenthelogicblocks.Italsohaslotsofveryflexibleinputandoutputcircuits(programmableforTTL,CMOSandotherinterfacestandards).

Nowadays,therearetwomajorplayersintheFPGAdomain:XilinxandAltera(nowpartofIntel).Thesetwodomains90%oftheFPGAmarketwithroughlyequalshare.

7

LetuslookinsideanFPGA.Considerthelogicblockshowninblueinthelastslide(AlteracallstheirlogicblockaLogicElement(LE)).TypicallyanLEconsistsofa4-inputLook-upTable(LUT)andaD-flipflop.LetusfornowNOTtoworryabouthowthe4-LUTisimplementedinternally.Justtreatthisasa4-inputcombinatorialcircuitwhichproducesoneoutputsignalasshownhere.TheIMPORTANTcharacteristicisthatthe4-LUTcanbeuserdefined(orprogrammable)toimplementANY4-inputBooleanfunction.Aswewillseelater,thelookuptableisactuallyimplementedwithabunchofmultiplexers.

8

TheLogicElementsaresurroundedbylotsofroutingwiresandinterconnectionswitches.TypicallyasignalwiretotheLogicBlockorLogicElementcanbeconnectedtoanyofthesewiringchannelsthroughaprogrammableconnection(essentiallyadigitalswitch).XilinxFPGAsalsohavededicatedswitchblocksshownhere.Horizontalandverticalwirescanbeconnectedthroughsuchasswitchblockwithprogrammableswitches(don’tworryfornowhowthat’sdone).

FPGAshavehugeamountoftheseprogrammableresourcesandswitches.Typicallyaverysmallpercentageofthesearebeingconnected(i.e.ON)foragivenapplication.

Themainadvantageand“power” ofFPGAcomesfromtheprogrammableinterconnect– moresothantheprogrammablelogic.

9

ProgramminganFPGAiscalled“configuration”.Inprogrammingacomputerormicroprocessor,wesendtothecomputerinstructioncodesas‘1’sand‘0’’s.Theseareinterpreted(ordecoded)bythecomputerwhichwillfollowtheinstructiontoperformtasks.Themicroprocessorneedstobefedtheseprogramcodescontinuouslyforittofunction.

InFPGAs,youonlyneedtoconfigure thechipONCEonpower-up.YoudownloadtothechipaBITSTREAM (alsobitsin‘1’sand‘0’s),whichdeterminesthelogicfunctionsperformedbytheLogicElements,andtheinterconnectingswitchesinordertoconnectthedifferentLEstogethertomakeupyourcircuit.Oncethebitstreamisreceived,theFPGAnolongerneedstoreadthe1’sand0’sagain,veryunlikeamicroprocessorwhichhastocontinuallydecodingthemachineinstructions.That’swhywesometimessaythatweconfigure anFPGA(insteadofprogramminganFPGA,althoughthetwowordsareusedinterchangeably).

WhathappenswhenyouconfigureanFPGA?Letusconsiderthe4-inputLUTscircuit.Thisistypicallyimplementusingatreeoffourlayersof2-inputto1-outputmultiplexers.Theentirecircuitisbehavinglikea16-to-1multiplexerusingthe4inputsABCDasthecontroloftheMUXtree.Forexample,ifABCD=0000,thenthetopmostinputoftheMUXisroutedtoYoutput.

Inthisway,ABCDformstheinputcolumnsofatruthtable.For4-inputs,thetruthtablehas16entries.TheoutputYforeachofthetruthtableentrycorrespondstotheinputoftheMUX.Configurationinvolvesfixingtheinputstothe16-to-1MUXbystoring‘1’ or‘0’ intheregistersR.Changingthe16valuesstored,youcanchangetotruth-tabletoanythingyouwant.

10

Toconfiguretheprogrammablerouting,letuslookathowtheroutingcircuitworks.TakeXilinxSWITCHBLOCKcircuit(greenblocksinslide7).Thisblockcontrolstheconnectionsbetweenfourhorizontalchannelsandfourverticalchannels.Thediamondshapedblockisapotentialinterconnectsite.Insidetheswitchblockcircuit,thereare6transistorswitcheswhichareinitiallyallOFF(oropencircuit).

ThegateinputofEACHswitchiscontrolledbytheoutputofa1-bitregister(e.g.a1-bitD-FF).Iftheregisterstoresa‘1’,theroutingtransistorwillhaveitsgatedrivenhigh.SincethetransistorisannMOStransistor,itwillbecomeconducting.Inthisway,configuringtheroutingresourcessimplymeansthatthecorrect‘1’sand‘0’sarestoredintheregistersthatcontroltheseroutingtransistors.

Asyouwouldexpect,typicallyanFPGAwouldhavehundredsofthousandsoftheseroutingswitches,mostoftheseareOFF.Onceprogrammed,theinterconnectionsaremade.Theboldlinesinthediagramabove(afterprogramming)showstheprogrammedconnections.

Bitsteaminformationusedforconfigurationpurposeareusuallystoredonaflashmemorychip,whichisdownloadtotheFPGAduringpower-up– similarto“bootingupacomputer”.Oncethisisdone,theFPGAisprogammedtoperformaspecificuserfunction(e.g.yourdesignintheVERIexperiment).

AlternativelyyoucansendthebitstreamtotheFPGAviaacomputerconnectiontothechip.OntheDE1-SOCboard,itdoesboth.PowerupDE1willconfiguretheCycloneVFPGAchiptoa“waiting”mode,whichmakestheDE1boardtalktothecomputerviatheUSBportwhileflashingthelightsONandOFF.YouthensendtotheboardabitstreamofyourdesignviatheUSBport.

11

LetusnowlookattheFPGAthatyouwilluseforthiscourse.TheAlteraCycloneVFPGAhasamoreadvancedprogrammablelogicelementthanthesimple4-inputLUTthatwehaveconsidereduptonow.ThecallthisaAdaptiveLogicModuleorALM.

AnALMcantakeupto8Booleaninputsignalsandproducesfouroutputswithorwithoutaregister.Additionally,eachALMalsocanperformthefunctionofa2-bitbinaryfulladder.

AsauseroftheCycloneVFPGA,youdon’tactuallyneedtoworrytoomuchaboutexactlyhowtheALMisconfiguredtoimplementyourdesign.TheCADsoftwarewilltakecareofthemappingbetweenyourdesignandthephysicalimplementationusingtheALMs.Itishoweverusefultoknowthatasthetechnologyevolves,moreandmorecomplicatedprogrammablelogicelementsarebeingdevelopedbythemanufacturersinordertoimprovetheareautilizationoftheFPGAs.

TheCycloneVontheDE1-SOCboardhas32,000ALMs,whichcouldbeestimatedtobeequivalentto85K+theoldstyleLEs.Puttingthisincontext,youcouldputontothisonechip2,00032-bitbinaryaddercircuits!

12

TheCycloneVismuchmorethanjustanFPGAwithabunchofLogicElements(orALMs).OurchipintheDE1-SOCboardhas32,000ALMs,whichisaround85Koldstyle4-inputLUTLEs.Ontopofthat,italsohasover4Mbitofembeddedmemory,87DSPblocks(todomultiply-accumulateoperationsneededforsignalprocessing),andevenadual-coreARMmicroprocessor!

Ithashard-logictoimplementPCIeinterface(tofastperipherals)andexternalmemoryinterfacetoconnecttoexternalmemory.Itisatrulypowerfulchipontowhichonecouldimplementanentiredigitalelectronicsystem.ThereforeAlteracallthisCycloneVSystem-on-Chip(SoC).

13

Forthislab-basedmodule,youwillbedesigningcircuitsusingthefreeversionofthedesignsuiteknownasQuartusPrimeLitefromIntel/Altera.Youcandownloadyourowncopyontoyournotebookmachine,oryoucanusetheversionsthatareinstalledinanyPCslocatedanywhereinthedepartment.

ThisverypowerfuldesigntoolcontainseverythingyouneedtodesignacomplexdigitalsystemONYOUROWNCOMPUTER!However,thesoftwareonlyrunsoneitheraMSWindowsoraLinuxoperatingsystem.IfyouareusingaMac,youwouldneedtorunaVirtualMachineapplications(suchasVirtualBox)andinstallWindowsorLinuxbeforeinstallingQuartusIIsoftware.

Bewarethatthesoftwareisverylarge– youneedtohaveseveralGBoffreediskspace.TheminimumrequiredRAMis4GB,and8GBisrecommended.

Ifyourlaptopissuitable,dodownloadthissoftwareandplaywithitathome.

14

ThisslideshowsyouthefunctionalblocksoftheDE1-SoCboard.Thishaseverythingyouneedtestbasicdesignsinvolvingswitches,7-segmentdisplaysandevenaVGAoutput.

15

Ialsoprovideapurpose-builtADC/DACboardtosupportthelabexperiment.Thisadd-onboardinonlyneededinweek3onwardsduringthelaboratorysessions.Sofornow,youcanignoreit.

16

Youareveryfamiliarwithschematiccapture.Inthefirstyear,youusedSPICEforsimulatinganaloguecircuitsandQuartusIIforyourdigitalexperimentwhereyoucreateschematiccircuitswithgates.

HowevermoderndigitaldesignmethodsingeneralDONOTuseschematics.Insteadanengineerwouldspecifythedesignrequirementorthealgorithmtobeimplementedinsomeformofcomputerlanguagespeciallydesignedtodescribehardware.Thesearecalled“HardwareDescriptionLanguages”(HDLs).

ThemostimportantadvantagesofHDLasameansofspecifyingyourdigitaldesignare:1)Youcanmakethedesigntakeonparameters(suchasnumberofbitsinanadder);2)itismucheasiertousecompilationandsynthesistoolswithatextfilethanwithschematic;3)itisverydifficulttoexpressanalgorithmindiagramform,butitisveryeasywithacomputerlanguage;4)youcanusevariousdatapathoperatorssuchas+,*etc.;5)youcaneasilyedit,storeandtransmitatextfile,andmuchhardwarewithaschematicdiagram.

Fordigitaldesigns,schematicisNOTanoption.AlwaysuseHDL.Inthislecture,Iwilldemonstratetoyouwhywithanexample.

17

IhavechosentouseVerilogHDLasthehardwaredescriptionlanguageforthecourse.VerilogisverysimilartotheClanguage,whichyoushouldalreadyknowfromyourfirstyearcourse.However,youmustalwaysrememberthatYOUAREUSINGITTODESCRIBEHARDWAREANDNOTACOMPUTERPROGRAMME.

YoucanuseVerilogtodescribeyourdigitalhardwareinthreedifferentlevelofabstraction:1) BehaviouralLevel – youonlydescribehowthehardwareshouldbehavewithoutANYreferencetodigitalhardware.2) Register-Transfer-Level(RTL)– Herethedescriptionassumetheexistenceofregistersandtheseareclockedbyclocksignal.Thereforedigitaldataistransferredfromoneregistertothenextonsuccessfulclockcycles.Timing(intermsofclockcycles)isthereforeexplicitlydefinedintheVerilogonce.Thisisthelevelofdesignweuseonthiscourse.3) GateLevel– thisisthelowleveldescriptionwhereeachgateisdescribedandhowtheseareconnectedtogetherisspecified.VerilogisnotonlyaspecificationlanguagewhichtellstheCADsystemwhathardwareissupposetodo,italsoincludesacompletesimulationenvironment.AVerilogcompilerdoesmorethanmappingyourcodetohardware,italsocansimulate (orexecute)yourdesigntopredictthebehaviourofyourcircuit.Itisthepredominantlanguageusedforchipdesign.

18

ThisisaVerilogcodemodulethatspecifiesa2-to-1multiplexer.ItisrathersimilartoaCfunction(exceptforthemodule keyword).

ItisimportanttorememberthebasicstructureofaVerilogmodule.Thereisamodulename:mux2to1.Thereisalistofinterfaceports:3inputsa,bandsel,and2outputsoutandoutbar.Alwaysusemeaningfulnamesforbothmodulenameandvariablenames.

Youmustspecifywhichportisinputandwhichportisoutput,similartothedatatypedeclarationinaCprogramme.

Finally,the2-to-1multiplexingfunctionisspecifiedintheassignstatementwithaconstructthatisfoundinC.Thisisabehaviouraldescriptionofthemultiplexer– nogatesareinvolved.Thelaststatementspecifiestherelationshipbetweenout andoutbar.ItisimportanttorememberthatVerilogdescribesHARDWAREnotinstructioncode.Thetwoassign statementsspecifyhardwarethat“execute” orperformthetwohardwarefunctionsinparallel.Thereforetheirorderdoesnotmatter.

19

Continuousassignmentspecifiescombinationalcircuits– outputiscontinuouslyreflectingtheoperationsappliedtotheinput,justlikehardware.Rememberthatunlikeaprogramminglanguage,thetwocontinuousassignmentstatementshereAREspecifyinghardwareinPARALLEL,notinseries.HerewealsoseetheconditionalassignmentstatementthatisfoundinC.Thismapsperfectlytothefunctionofa2-to-1multiplexerinhardwareandiswidelyusedinVerilog.Furthermore,therearemanyotherBooleanandarithmeticoperatorsdefinedinVerilog(asinC).HereisaquicksummaryofalltheVerilogoperators(usedinanexpression).

20

WhilethepreviousVerilogcodeforthe2-to-1muxonlyspecify“behaviour”,hereisonethatspecifyagateimplementationofthesamecircuit.Threetypesofgatesareused:and,orannotgates.Thereareinternalnets(declaredaswire)whichtakeonanynames.

Keywordssuchasand,or andxor arespecial– theyspecifyactuallogicgates.Theyarealsospecialinthatthenumberofinputstotheand-gatecanbe2,3,4,…..Anylength!

NotethatthismoduleusesTWOANDgates,andtheyhavedifferentnames:a1anda2.ThereareTWOseparateinstancesoftheANDgate.Forsoftwarefunctions,“calling” afunctionsimpleexecutethesamepieceofprogrammecode.Herethetwolines“anda1(out1,…” and“anda2(out2…” producetwoseparatepieceofhardware.Wesaythateachlineis“instantiating” anANDgate.

Wiringupthegatesisthroughtheuseofportsandwires,anddependsonthepositionsofthese“nets”.Forexample,out1istheoutputnetoftheANDgatea1,anditisconnecttotheinputoftheORgateo1byvirtualofitslocationinthegateportlist.

21

SofarwehaveusedVeriloginaveryhardwarespecificway.“assign” andusinggatespecificationarespecialtoVerilog.

HereissomethingthatismorelikeC– anditiscalled“proceduralassignment”.Typicallyweusesomethingcalled“always” blocktospecifya“procedure” orcollectionofsequentialstatementswhicharesandwichedbetweenbegin-endconstruct.

Thealwaysblockneedsasensitivelist– alistofsignalssuchthatifANYofthesesignalchanges,thealwaysblockwillbeinvoked.Youmayreadthisblockas:

“alwaysatanychangesinnetsa,borsel,dothebitsbetweenbeginand end”Actually,ifyouaredefiningacombinationalcircuitmodule,anevenbetterwaytodefinethealwaysblockistouse:…..always@*....//alwaysatanychangewithanyinputsignals

Insidethebegin-endblock,youareallowedtouseC-likestatements.Inthiscase,weusetheif-elsestatement.Allstatementsinsidethebegin-endblockareexecutedsequentially.

22

NotethatVerilogkeywordreg doesnotimpliesthatthereisaregistercreatedinthehardware.Itismuchmorelikedeclaringavariablethatholdsavalue.ItisaruleinVerilogthatassignmentINSIDEanalwaysblockMUSTbedeclaredreg,andNOTanet(wire).ThisisoneofthefewpeculiaritiesofVerilogthatcanbeconfusingtostudents.

23

ThisslideshowshowtheproceduralstatementismappedtothebasicMUXcircuit.ThecontinuousassignmentstatementcorrespondstotheNOTgate.

24

ThisisyetanotherwaytospecifytheMUXcircuit.Itisstillaproceduralassignmentwiththe“always” block.However,wereplacetheif-elsestatementwitha“case”statement.Thecasevariableissel.Sinceselisa1-bitsignal(ornet),itcanonlytakeon0or1.

Notethatthevariouscasevaluescanbeexpressedindifferentnumberformatsasshownintheslide.Forexample,consider2’b10.The2isthenumberofbitsinthisnumber.‘bmeansitisspecifiedinbinaryformat.Thevalueofthisnumberis10inbinary.

25

Thisslidedemonstrateswhylanguagespecificationofhardwareissomuchbetterthanschematicdiagrams.Bysimpledeclaringthesignalsasamulti-bitbus(8bits[7:0]),wechangethismoduletoonethatspecifies8separate2-to-1multiplexers.

Anotherusefulwaytospecifyabusisusingtheconcatenationoperator:{….}asshownabove.

Theconcatenationoperatorisparticularlyusefulinconvertingdigitalsignalsfromonewordlength(i.e.numberofbitsinaword)toanother.Forexample,toconvertan8-bitunsignednumbera[7:0]toa13-bitunsignednumberb[12:0],youcansimpledothis:

assign b[12:0] = {5’b0, a[7:0]};

26

Hereisasimpleexample:thedesign ofa4-bithexcodeto7segmentdecoder.Youcanexpressthefunctionofthis7-segmentdecoderinthreeforms:1)asatruthtable(notethatthesegmentsarelowactive);2)as7separateK-maps(shownhereisforout6segmentonly);3)asBooleanequations.

ThisisprobablythelasttimeyouseeK-maps.Inpracticaldigitaldesign,youwouldrelyheavilyonCADtools.Inwhichcase,thelogicsimplificationsaredoneforyouautomatically– youneverneedtouseK-mapstodothatmanually!

27

Hereisatediousimplementationintheformofschematicofinterconnectedgates.Veryhardtodoandverypronetoerrors.

28

OnecouldtakeagroupofgatesandspecifythegatesinVeriloggateprimitivessuchasand,oretc.Stillverytedious.Hereistheimplementationfortheout6output.

29

Insteadofspecifyingeachgateseparately,hereisusingcontinuousassignmentstatement,mappingtheBooleanequationdirectiontoasingleVerilogstatement.Thisisbetter.

30

Hereisthecompletespecificationofthehex_to_7segmoduleusingcontinuousassignment.ItshowshowoneshouldwriteVerilogcodewithgoodcommentsandcleardocumentationofinputandoutputports.

31

Finallythe4th methodisthebest.Weusethecaseconstructtospecifythebehaviourofthedecoder.Hereonedirectlymapsthetruthtabletothecasestatement – easyandelegant.

Insteadofusing:always@(in),youcouldalsousealways@*

32

HowisaVerilogdescriptionofahardwaremoduleturnedintoFPGAconfiguration?ThisflowdiagramshowsthevariousstepstakeninsidetheQuartus IICADsystem.

FortheLabExperiment,youwillbeworkinginpairs.Inothertoensurethatyougettoknoweachother,IhaverandomlypairedyoutogetherwithsomeoneelseasLabPartnerforthismodule.