subroutine & interrupts.pptx
TRANSCRIPT
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Subroutine & Interrupts
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Sequence of a subroutine
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Note:
Stack should remain undisturbed Registers in main pgm & subroutine
should not get mixed up
Goto instruction to be used wisely, itshouldnt interfere with subroutine pgm
Call (subroutine entry address-11+2address bits)
Return
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Sequence of a nested subroutine
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Note:
Stack should remain undisturbed
Storage & Retrieval of address from stack takesplace one after the other
8 level stack-LIFO
In a sequence, 8 return addresses can be storedin stack
Goto instruction to be used wisely, it shouldntinterfere with subroutine pgm
Call (subroutine entry address-11+2 address bits)
Return
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Special task to be done on prioritybasis
Examples Monitoring AC supply & emergency back
up
Measuring temperature & pressureduring a particular time slot
Alarm setting
Interrupts
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Interrupts
Main pgm execution
Interrupt signals generated from differentsources
When interrupted, Special task execution
Special task completion Resume main pgm
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Difference between Subroutine &Interrupts
Subroutine Interrupt
Subroutine call occurs at specific& pre-determined location in themain pgm
Interrupt call can occur withoutany prior notice at any point ofthe main pgm
Software initiated Hardware initiated
Structured routine set ofinstructions
Emergency condition-saving thestatus of registers required
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Interrupts-Procedure
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Interrupt enabling
PIR Interrupt requestPIE Interrupt mask register
GIE Global Interrupt Enable
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Bank0
Bank1
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Interrupt timing diagram
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Single interrupt
IRQ
IE
GIE
Dummy cycles
ISR-starts @ ox04
Interrupt status saving
Bank switching
Common scratchpad area
Return from Interrupt
RETFIE
GIE enabled
Interrupt response time
3 to 4 instruction cycles execution of active instruction, save return address, vector to ox04location
3 to 5instruction cycles save mc status
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0x04h
Interruptfrom SourceA
Y
N
Serviceroutine A
Serviceroutine B
PROGRAM:
004H:BTFSCPIR, A
GOTOSRA
ISR FORBRETFIE
SRA: ISR FOR ARETFIE
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Ports
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Port B Circuit
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Port-Output operation-Write
F0-Phase beforeport pin is
configured
F1-Configuringinto output mode
F2-Data writteninto port
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Port-Input operation- Read
F0-Phase beforeport pin is
configured
F1-Configuringinto input mode
F2-Data readfrom port
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Pull up
Input mode
Stray signals destroy ic
Resistance connected from pin to supply PMOS transistor kept in active state
forms pull up
L2-1 nand RBPU-0 => PMOS gate 0state
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Every port has port register
In Output mode-data written to port
register Ports A,B,C,D,E-can be configured as
input or output pins