Sub-20nm Novel Silicon based transistors Yu-Lin Chao, Venkaragirish N., Ritesh Jhaveri, Ahmet Tura, and Jason C. S. Woo

Department of Electrical Engineering, University of California, Los Angeles

Aggressive MOSFET scaling faces the challenges of limited Ion/Ioff ratio and severe short channel effects. To overcome these problems, new device configurations made feasible by small dimensions and new materials need to be explored. In this paper, novel devices incorporating silicon and germanium are presented. These silicon and germanium based asymmetric source injection devices with superior performance have the potential to alleviate the scaling challenges for sub-25nm nodes. 1. Schottky Barrier MOSFET

Schottky barrier MOSFETs which use fully silicided source/drain junctions have been proposed for future very-short-channel devices 0. The major advantage is the formation of ultra shallow junctions with very low resistively. In this abstract, a novel asymmetric Schottky Tunneling Source MOSFET is introduced. The operating principle of the STS MOSFET utilizes the concept of gate controlled Schottky barrier tunneling between a metal and a semiconductor. Fig. 1 shows the band diagram along the surface of the channel region at different gate voltages for a Schottky source with a barrier height (φb) of 0.45eV. When the gate voltage is sufficiently low the tunneling distance of the Schottky junction is high as well as the number of states that electrons can tunnel into is small. Hence the current injection is limited by the tunneling resistance only. As the gate voltage increases, the tunneling distance reduces and the number of states the electrons in the metal source can tunnel into increases thereby reducing the tunneling resistance. Fig 2a shows that as gate oxide thickness reduces, there is a marked improvement in STS MOSFET sub-threshold characteristics as well as ION. A sub-threshold swing of ~130mV/dec is obtained for EOT = 20Å and ~70mV/dec is obtained for EOT = 5Å. This suggests that the sub-threshold swing is a strong function of tOX as opposed to diffusion barrier transport. However, the sub-threshold swing obtained due to gate controlled tunneling is always degraded as compared to best possible diffusion limited sub-threshold swing (~60mV/dec at room temperature); even though STS has excellent DIBL and VTH roll-off characteristics. To further improve the performance of STS transistor, Schottky FETs with asymmetric source/drain pocket is proposed. Fig 2b shows that as the source pocket is made n-type with increasing dopant density, the tunneling distance (and therefore tunneling resistance) reduces for a given gate voltage and the threshold voltage also reduces. But, the sub-surface conduction goes up thereby increasing the off current. However, when the pocket is made p-type, a region of high threshold is created near the source. This reduces the subsurface conduction considerably resulting in low IOFF. ION on the other hand is not degraded

since the band-bending increases due to the p-pocket. Therefore, the tunneling width remains about the same as conventional STS transistor. The n+ pocket on the drain side forms a low resistance contact between the channel and the drain, eliminating the potential drop at the drain side due to the presence of a Schottky barrier.

Figure 1 Conduction Band Edge profile along the channel for different gate voltages. φb=0.45eV.

2. Tunnel Source MOSFET

To further improve the ION/IOFF ratio, we propose the Tunnel Source (P+N+ tunnel diode) MOSFET [3]. The device structure of the novel asymmetric MOSFET is shown in Fig. 3. The gate electrode controls the source-to-channel tunneling current by modulating the band-alignment between the valence band of the P+ tunneling source and the conduction band of the channel (thus modulating the availability of density of states for tunneling) and modulating the tunneling width (Fig 4).

0.0 0.2 0.4 0.6 0.8 1.01.0x10 -4

1.0x10 -3

1.0x10 -2

1.0x10 -1

1.0x10 0

1.0x10 1

1.0x10 2

1.0x10 3

φb= 0.45eV

VD

= 0.1VV

D= 1.0V

20Å

10Å

5Å

tOX

= 2Å

I D(μ

A/μ

m)

VG (V)-0.3 0.0 0.3 0.6 0.9 1.2

1.0x10-6

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x100

1.0x101

1.0x102

φb = 0.45eV tOX= 5Å

p type pocket

n type pocket I D

(μA

/μm

)

VG (V)

(1-8X1018) cm-3

(1-8X1018) cm-3

0.0 0.2 0.4 0.6 0.8 1.01.0x10 -4

1.0x10 -3

1.0x10 -2

1.0x10 -1

1.0x10 0

1.0x10 1

1.0x10 2

1.0x10 3

φb= 0.45eV

VD

= 0.1VV

D= 1.0V

20Å

10Å

5Å

tOX

= 2Å

I D(μ

A/μ

m)

VG (V)0.0 0.2 0.4 0.6 0.8 1.0

1.0x10 -4

1.0x10 -3

1.0x10 -2

1.0x10 -1

1.0x10 0

1.0x10 1

1.0x10 2

1.0x10 3

φb= 0.45eV

VD

= 0.1VV

D= 1.0V

20Å

10Å

5Å

tOX

= 2Å

I D(μ

A/μ

m)

VG (V)-0.3 0.0 0.3 0.6 0.9 1.2

1.0x10-6

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x100

1.0x101

1.0x102

φb = 0.45eV tOX= 5Å

p type pocket

n type pocket I D

(μA

/μm

)

VG (V)

(1-8X1018) cm-3

(1-8X1018) cm-3

-0.3 0.0 0.3 0.6 0.9 1.21.0x10-6

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x100

1.0x101

1.0x102

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x100

1.0x101

1.0x102

φb = 0.45eV tOX= 5Å

p type pocket

n type pocket I D

(μA

/μm

)

VG (V)

(1-8X1018) cm-3

(1-8X1018) cm-3

Figure 2 (a) ID-VG characteristics of devices with different gate oxide thicknesses for a given φb of 0.45eV. NBULK = 1X1017cm-3. (b) ID-VG characteristics with different pocket doping. NBULK = 1X1017cm-3, tSI = 60nm and VD = 0.1V.

VS (fixed at 0V) VD(varied from0 to 1)

VG (varied from 0 to 1)

NAP NDDND NGNA

Buried Oxide

Tsi

TBOX

W Lchannel

TOX

Figure 3 Device structure of the novel PNPN MOSFET

Valence Band

Conduction Band

(a)

Valence Band

Conduction Band

(a)

Valence Band

Conduction Band(b)

Valence Band

Conduction Band(b)

Figure 4. Band Diagram along the channel along section S in Fig. 3. (a) VG < VTH (b) VG > VTH.

Detailed simulations show that the optimized novel PNPN MOSFET exhibits a steep sub-threshold slope (<<60mv/dec) (Fig 5a) with negligible DIBL. This is due to the fact that the overlap of the available density of states changes abruptly from zero to a finite value along with a reduction in tunneling width as the gate voltage increases from 0 to VTH. Since the subthreshold behavior is determined by the tunneling source junction, DIBL is significantly reduced. Fig. 5b shows the ID-VD characteristics for the tunnel source MOSFET and a conventional SOI MOSFET. In the above threshold regime, the resistance of the tunneling junction is negligible for the PNPN MOSFET resulting in a current characteristic similar to a conventional SOI transistor. The threshold voltage (VTH) is defined as the gate voltage at which the channel conduction band overlaps with the source valence band. Therefore, for the same VG-VTH, the drive current is larger (band bending > 2 φb) for the PNPN MOSFET.

3. Tunneling transistors on GeOI Germanium has regained attention for its low field high

electron and hole mobilities which are beneficial for carrier transport in nanoscale devices. In addition, due to its smaller bandgap and therefore smaller tunneling width, Ge is the material of choice for both the Schottky FET and the Tunnel Source FET. To better control short channel effects and junction leakage current and to make germanium acceptable in current silicon production line, germanium-on-insulator (GeOI) is preferred. GeOI substrates can be obtained by wafer bonding and Smart-CutTM techniques. A successfully transferred germanium on oxidized silicon wafer is shown in Fig. 6. The fabricated GeOI substrate has large amounts of vacancies which are the major diffusion vehicles in germanium. The electrical concentrations in bulk germanium and GeOI are then determined by the Fermi level dependency of dopants (Fig. 7a). Boron yields identical active concentration in two substrates, whereas phosphorous shows lower active level in GeOI due to faster diffusion assisted by charged vacancies, and this may affect scalability of germanium nMOSFETs. Another challenge of Ge devices is the quality of gate stack. A stable metal gate electrode against the selection of gate dielectrics is essential. In our study, Mo/germanium oxynitride gate stack is found to be thermally stable up to 400°C with interface charge density in the orders of 1012 /cm2, as shown in Fig. 7b. A further reduction of the charge density is still needed.

Figure 6 XTEM of a GOI sample

4. References [1] Moongyu Jang et al, IEEE Transactions on Nanotechnology, Vol.2, No. 4, pp 205-209, 2003. [2] Kazuya Matsuzawa et al, IEEE Transactions on Electron Devices, Vol. 47, No. 1, pp 103-108, 2000. [3] N. V. Girish, Ritesh Jhaveri and Jason C. S. Woo, IEEE 2004 Silicon Nanoelectronics Workshop, 2004, pp. 33-34.

Source Drain

Gate

P+ Fully Depleted N+ layer S

P+ P N+

1.0x10-91.0x10-81.0x10-71.0x10-61.0x10-51.0x10-41.0x10-31.0x10-21.0x10-11.0x1001.0x1011.0x1021.0x103

0.0 0.2 0.4 0.6 0.8 1.0

I D(µ

A/µ

m)

VG (V)

VD = 0.1 V

VD = 1 V

0

10050

150200250300350400450500550

VD (V)

I D(µ

A/µ

m)

VTH = 0.325 V VG = 1 V

0.8 V

0.9 V

0.7 V

0.6 V 0.5 V 0.4 V

0.0 0.2 0.4 0.6 0.8 1.01.0x10-91.0x10-81.0x10-71.0x10-61.0x10-51.0x10-41.0x10-31.0x10-21.0x10-11.0x1001.0x1011.0x1021.0x103

0.0 0.2 0.4 0.6 0.8 1.0

I D(µ

A/µ

m)

VG (V)

VD = 0.1 V

VD = 1 V

1.0x10-91.0x10-81.0x10-71.0x10-61.0x10-51.0x10-41.0x10-31.0x10-21.0x10-11.0x1001.0x1011.0x1021.0x103

1.0x10-91.0x10-81.0x10-71.0x10-61.0x10-51.0x10-41.0x10-31.0x10-21.0x10-11.0x1001.0x1011.0x1021.0x103

0.0 0.2 0.4 0.6 0.8 1.00.0 0.2 0.4 0.6 0.8 1.0

I D(µ

A/µ

m)

VG (V)

VD = 0.1 V

VD = 1 V

0

10050

150200250300350400450500550

VD (V)

I D(µ

A/µ

m)

VTH = 0.325 V VG = 1 V

0.8 V

0.9 V

0.7 V

0.6 V 0.5 V 0.4 V

0.0 0.2 0.4 0.6 0.8 1.00

10050

150200250300350400450500550

0

10050

150200250300350400450500550

VD (V)

I D(µ

A/µ

m)

VTH = 0.325 V VG = 1 V

0.8 V

0.9 V

0.7 V

0.6 V 0.5 V 0.4 V

0.0 0.2 0.4 0.6 0.8 1.00.0 0.2 0.4 0.6 0.8 1.0

Figure 5 (a) Subthreshold Characteristics of a Tunnel Source FET. (b) ID-VD characteristics for different VG for the Tunnel Source FET (dotted) and conventional MOSFET (solid)

(a)

(b)

Figure 7 (a) Electrical concentrations of n- and p-type dopants in bulk Ge and GeOI (b) C-V curves of Mo/germanium oxynitride gate stack before and after annealing.

CMOS Research Laboratory

Sub-20nm Novel Silicon based transistors

Jason C. S. WooUniversity of California, Los Angeles

Outline

• Motivation for sub-25nm novel device concepts

• GeOI Devices• Schottky Transistors• Tunnel Source (PNPN)MOSFET

Scaling Challenges

Challenges arising due to scaling in the sub-nm regime

Source/Drain-to Channel

Electrostatic Coupling

Channel Transport Limitation

(Mobility Reduction, Velocity saturation)

Parasitic Effects (Source/Drain

Resistance/Capacitanc, Gate Leakage)

SDE & Series Resistance Scaling Trends

2000 2002 2004 2006 2008 2010 2012 2014 2016 20180

10

20

30

40

50

60

70

Rsd

/ R

ch,id

eal [%

]

SDE Junction Depth

Max. Ratio of Rsd

to Ideal Rch

Physical Gate Length2001 ITRS

Gat

e Le

ngth

or S

DE

Dep

th [n

m]

Year

0

10

20

30

40

50

60

)( thgs

oxchch VV

tLR−

∝

jsdshsd XN

RR 1∝∝

⇒ Scaled with Lg (Lch ↓, tox↓)

⇒ Difficult to scale Rsh ⇒ Rsd/Rch ↑(Nsd ↑, Xj ↓ )

Relative Contributions of Resistance Components

• Assumptions : Scaled according to ITRS projection Gradual doping & midgap silicide material

• Rcsd will be a dominant component for highly scaled nanometer transistor( Rcsd/Rseries is rising up to >> ~ 60 % for LG < 53 nm)

32 nm 53 nm 70 nm 100 nm0

100

200

300

400

500NMOS scaled by ITRS

S/D

Ser

ies

Resi

stan

ce [Ω

µm]

Physical Gate Length

Rcsd

Rdp

Rext

Rov

32 nm 53 nm 70 nm 100 nm0

10

20

30

40

50

60

70

Rdp

Rext

Rov

RcsdNMOS

Physical Gate Length

Rela

tive

Con

trib

utio

n [%

]

NMOSFETs

Relative Contributions of Resistance Components

• Relatively large Rov contribution, but still largest in Rcsd

( Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 % for LG < 53 nm)

PMOSFETs

32 nm 53 nm 70 nm 100 nm0

100

200

300

400

500

600

700

S/D

Ser

ies

Resi

stan

ce [Ω

µm]

PMOS scaled by ITRS

Rcsd

Rdp

Rext

Rov

Physical Gate Length

32 nm 53 nm 70 nm 100 nm0

10

20

30

40

50

60

70

Physical Gate Length

Rdp

Rov

Rext

Rcsd PMOS

Rela

tive

Con

trib

utio

n [%

]

Advanced S/D Engineering

0

30

60

90

120

150

180

210

240

270

300

Rcsd

Rdp

Rext

Rov

Source/Drain Engineering

S/D

Ser

ies

Resi

stan

ce [Ω

µm]

Box ProfileLow-Barrier Silicide(Φ

B = 0.2 eV)

Box ProfileMidgap Silicide

Graded JunctionMidgap Silicide

LG = 53 nm • Potential solutions for

advanced S/D Engineering:

⇒ Box-shaped highly-doped ultrashallow SDE junction (i.e., laser annealing)

⇒ Schottky Barrier lowering(i.e., ErSi for NMOS, PtSi2for PMOS, and lower bandgap Si1-xGex layer)

SOI MOSFET

Nsub

x

Ru,co

GateSpacer

Buried Oxide

Rac,ovRspr,ov Rext,sp Rdp,sp

Nm,dp

Nm,ext

Nsd(x)

Rsw,co

Silicide

Lcon

Ru,co

Rsw,co

Rsp

Rspr,ov Rac,ov

Rco

Rext,spRdp,sp

Rov

)( ov sp co RRR2 ++=sdextrinsic RR 2=

Contact resistance in SOI MOSFETs

0 5 10 15 20 25 30 35 40100

200

300

400

500

600

700

800

900

1000

tsoi = 40 nm

tsoi = 20 nm

tsoi = 10 nm

Rco = Ru,co//Rsw,coRu,coRsw,co

Lcon = 50 nm Uniform Doping Nco= 1.5E20 cm-3

tsili[nm]

Rco

(Ωµm

) Low SBH (ΦB = 0.25 eV)(ρc = 1.27X10-8 Ωcm2

for uniform doping)

-50 -40 -30 -20 -10 0 10 20 30 400

10

20

30

40

50

60

70

SOI

Lcon= 50 nm

Simulation tsoi = 10 nmtsoi = 40 nm

Elevated S/D

ΦB = 0.25 eV

Lcon= 200 nm

tsili [nm]

Rco

(Ωµm

)Need Contacts with Low ΦB

Scaling Challenges

Challenges arising due to scaling in the sub-subnm regime

Source/Drain-to Channel

Electrostatic Coupling

Channel Transport Limitation

(Mobility Reduction, Velocity saturation)

Parasitic Effects (Source/Drain

Resistance/Capacitanc, Gate Leakage)

Potential Solutions• Improved Device Architecture (Double/Tri-gate MOSFETS)• New materials to enhance transport (SiGe or Ge channel)• New Gate Dielectrics to reduce gate leakage (High-K)• Small φB contacts --- Small EG Source/Drain Junctions

Potential Solutions

• New Materials with Higher Mobilities• New Gate Stack to Reduce Tunneling• New Contact Materials (Metal and

Semiconductor) to reduce Rco

• New S/D Structures (e.g. Raised S/D) for Small RS/D

• SOI, DG, … to improve SCE

CMOS Research Laboratory

Essentially, Try to Make Scaled MOSFETs Follow Scaling Behavior of “Long Channel Device Miniaturization”

Alternatives?

New Device Architectures• Novel Transports• Incorporate QM Effects

New Materials• High Mobilities• Bnadgap Engineering

Others

Lateral Asymmetric Channel (LAC) MOSFET

polypoly BF2 (NMOS) S D

θTilt angle θLAC

Conventional

-0.1 -0.05 0 0.05 0.1Lateral Position (µm)

1015

1016

1017

1018

1019

1020

Impu

rity

Conv.

S DLgate=0.12 µm

LACCon

cent

ratio

n (c

m-3

)

LAC: Tilt=10o

Formation of Channels in the LAC and conventional structures. Usual tilt angle: 10o-15o

Simulated channel profiles for devices with same Vth from source to drain 1.5 nm away from the SiO2/Si interface.

Lateral Asymmetric Channel MOSFETs

What are the advantages?• Suppression of Short Channel Effects similar to the

Double Halo (DH) structures in bulk devices

• Higher Current Drive than DH for both Bulk and SOI devices

• Higher Transconductance than DH and conventional devices for bulk devices

• Improved Early Voltage compared to DH in bulk devices

• Improved low frequency Flicker Noise compared to conventional devices

Ids = W Cox(Vgs-Vth(y)-V(y))v(y)

-0.05 0 0.05Lateral Position y (µm)

0

1

2LACDPConventional

-0.05 0 0.05Lateral Position y (µm)

0

0.5

1

1.5

2

Ave

Car

rier

Vel

ocity

(107 c

m/s)

LACDPConventional

LAC Transistor

LAC Devices: Higher doping near the source end ⇒• High lateral electric field near the source end in channel region• High average carrier drift velocity near the source end in channel region• High current drive,

Ey(1

05 V/c

m)

LAC DEVICES: ANALOG PERFORMANCE

0 0.2 0.4 0.6 0.8 1.00

0.1

0.2

0.3

0.4LAC Tox =25ÅLAC Tox =36Å

Conv. T ox =25ÅConv. T ox =36Å

NMOS

Ids same at same Lg & Tox

Vds=0.8V

g m(m

S/µ

m)

0 0.2 0.4 0.6 0.8 1.00

5

10

15

LAC Tox=25 ÅLAC Tox=36 Å

Conventional, T ox=25 ÅConventional, T ox=36ÅNMOS

•g m is higher in SP devices•g m/Id ratio is very high compared to conventional devices when biased at same

current density :- due to high current drive, small Vgt is needed. Also high gm

Lg(µm)

g m/I

d(V

-1)

Vgt=0.3V, Vds=0.8V for Conv.Vds=0.8V, Ids same as Conv. for SP(Vgt~0.15-0.3V).

Lg(µm)

Issues with LAC Transistors

• High doping near the source – Lower Mobility• Sharp doping profile in sub45 nm transistors –

Difficult10.0 20.0 30.0 40.0 50.0 60.0

Channel position (nm)

0.5

0.7

0.9

1.1

1.3

pote

ntia

l (V

)

Potential profile for the HL devic e

Vds=0.2 VVds=0.4 VVds=0.6 VVds=0.8 VVds=1.0 V

H L

•An electric field peak is generated in the channel close to the source side which enhances source carrier injection into the channel ( gm ).• Rout can be increased due to the reduced channel-length-modulation.

Lg=45nmWH-WL=0.3eVVgt=0.2V, Vds=0V

Proposed Split Gate Design

H gate

H -- L gate

Source Drain

Vds=0.8 V• The work-function of the H gate is higher than that of the L gate

p- sub

0.0 20.0 40.0 60.0Channel position (nm)

-0.7

-0.5

-0.3

-0.1

0.1

0.3

0.5

Lat

eral

E-F

ield

(MV

/cm

) H-L gate H gate

0 5 10 15Channel-X (nm)

0

20

40

60

E X(k

V/c

m) H gate

H - L gate

Simulation: Gm and Rout in scaled MOSFETs

• Both gm and rout can be improved by using this split gate design for different channel length considered.

0 100 200 300 400 500Bias current (µΑ/ µm)

250

750

1250

1750

2250

Gm

(mS/

mm

)

Lg = 45 nmLg = 90 nmLg = 130 nmLg = 180 nm

Empty Symbol: H deviceSolid Symbol: HL device

0 100 200 300 4000

10

20

30

40

50

Rou

t(K

Ω)

0 50 100 150 200 2500

100

200

300

400Empty symbol: H gate

Solid symbol: HL gate

Lg = 130 nm

Lg = 45 nm

Bias current (µΑ/ µm)

Rou

t(K

Ω)

Bias current (µΑ/ µm)

Sb-induced Work Function Shift in the NiSi Gate

• NiSi Gate: Gate full silicidation and no oxide degradation. • Antimony implantation in the polysilicon gate reduces the NiSi gate work function (~0.25eV) due to the dopantsegregation effect at the NiSi/oxide interface.

2.6nm

Tox = 2.6nm

-2.0 -1.5 -1.0 -0.5 0.0 0.5Gate Bias (V)

0

50

100

Cap

atan

ce(p

F) undoped NiSi

Sb doped NiSi

NiSi/Oxide Capacitor, 100µm x µm

(1.5x1015cm-2)

Process Flow

PR

LTO

Si

Sb

L TO

Si

SiN SiN

Poly

Si

SiN SiN

N iSi

Si

NiSi NiSiSiN SiN

(a)

(b)

(c)

(d)

Poly oxide

• Oxide/Poly/LTO: 4.5nm/50nm/200nm

• Sb implant energy, dose and angle: 25KeV, 1.5x1015 cm-2, 30o

• Nitride spacer width : ~ 80nm

• Silicide conditions: 10mins @ 450 oC

Id-Vg and Id-Vds curves

• Improved current drive capability is observed for the NiSi gate device with tilt angle Sb implantation from the drain side, i.e, the split-gate device.

(Substrates are undoped)

0.0 0.5 1.0 1.5 2.0 2.50.0

1.0m

2.0m

3.0m

4.0m

5.0m

Lg=0.6µm Vg=2 V

Vg=1.5 V

Vg =1.0 V

Vg=0.5 V

Vg=0 V

tilt-angle doped(Sb) NiSi gateUndoped NiSi gate

Dra

in c

urre

nt (A

/ 10

µm

)

Vds (V)-0.5 0.0 0.5 1.0 1.5 2.0

1E-7

1E-6

1E-4

Lg=0.6µm VDS=0.1 V

Dra

in c

urre

nt (A

/ 10µ

m)

Vg (V)

Undoped NiSiTilt-angle Sb-doped NiSi

1E-5

Output Resistance

• At lower bias current, both devices have similar rout due to their large DIBL as a result of un-doped substrates. • At higher bias current, the split-gate device has higher rout due to its less channel-length-modulation at the drain side.

Vds = 2.0 V

0 100 200 300 400 50010

100

Out

put r

esis

tanc

e (K

Ω)

Bias current (µA/µm)

Sb-doped NiSi gateun-doped NiSi gate

Scalable?

0 100 200 300 400 500250

750

1250

1750

2250

g m(m

S/m

m)

Empty Symbol: H deviceSolid Symbol: HL device

0 100 200 300 400Bias Current (µA/µm)

0

10

20

30

40

50

Rou

t(K

Ω)

Lg = 45 nm

Bias Current (µA/µm)

SplitSplit--gate HL gate HL MOSFETsMOSFETs have improved gainhave improved gain-- frequency frequency performance compared with conventional performance compared with conventional MOSFETsMOSFETs

Improved speed-gain performance

Lg=45 nm

10 20 30 40Intrinsic Gain

150

200

250

300

350

F T(G

Hz)

Lsp=27.5 nmLsp=30 nmLsp=35 nmLsp=40 nmLsp=45 nmEmpty symbol: H device

Solid symbol: H-L device

Vth=0.15--0.25Vth=0.25--0.35

Lg=45nmIDS =100 µ A/µm

CMOS Research Laboratory

Novel Materials

GOI MOSFET

• Advantages of germanium- Large low field mobilities- Reduced RS/D

- Large Tunneling Probilities- Possibility of optoelectronic integration

Gemanium-on-Insulators Wafers

• Why Germanium-on-Insulators?- Germanium is expensive ($$$) and brittle.- Germanium has high dielectric constant, so worse SCE.- Help our industry peers incorporate Ge into existing Si production lines.

• How to make it?Wafer bonding and Smart-CutTM technologies are employed to fabricate GeOI substrates.

H+

Ge

Ge

AnnealBondingSi

Si

Ge

Si

Gemanium-on-Insulators Wafers

• Germanium film remains single crystalline known from TEM diffraction pattern.

As-split XTEM

P, 600°C

Before RTA

Dopant Activation in Ge/GeOI

• Bulk Ge- The difficulty of dopant activation arises from the limited solid solubilities and fast diffusion of dopants in Ge.- Rapid thermal annealing and pre-amorphization implantation (PAI) are combined to address the issues.

B, 650°C

Before RTA

Dopant Activation in Ge/GeOI

• GeOI- The lower level of P activation in GeOI is due to enhanced diffusion by vacancies created by hydrogen implantation.- The cause for the high level of boron concentration in GeOIis still under investigation.

Gate Dielectric/Electrode in Ge

• Germanium oxynitride is used as gate dielectric film in our study.

• This film seems to exhibit low gate leakage current, but the reliability remains a concern, and more study is on going.

Al

GeON

Ge

~13Å

HRTEM

(Å)

CMOS Research Laboratory

Novel QM-Injection Transistos

Motivation

Vs/db

unscaled Vth Vsupply

S Ioff Ion

Higher Ioff and reduced Ion/Ioff ratio

Exploit novel device physicsconcepts made possible by nano-dimensions to achieve steep subthreshold swing and ballistic carrier transport to give high Ion.

Vs/db – Source/Drain-Substrate Junction PotentialVth – Threshold VoltageS – Subthreshold Swing

Assymetric Schottky Tunneling Source MOSFET

•Schottky Barrier between Fully Depleted pocket and the source silicided junction

•Fully Silicided Source/ Drain Junctions

•N+ Region on the drain side to form an ohmic contact between drain and substrate

The gate controls the tunneling through the schottky barrier on the source side by changing the tunneling width as well as the available density of states on the semiconductor side

Silicide Silicide

Source DrainGate

P N+

Buried Oxide

Fully depleted N/P layer

Device Concept

0.00 0.05 0.10

Conduction Band

Valence Band

Vg = 0 V

Distance along the channel (μm)

Vg = 1 V

0.5

0.0

-1.0

-0.5

Ele

ctro

n E

nerg

y (e

V) φ

b

a) Vgate < Vthreshold•Tunneling Distance of the schottkyjunction is large•Number of available states on the semiconductor side is limited•Subthreshold current is limited by schottky tunneling resistance

b) Vgate > Vthreshold•Tunneling Distance decreases•Number of available states on the semiconductor side increases•Tunneling Resistance decreases and current gets limited by channel and tunneling resistance depending on certain parameters at the schottkyjunction

Band Diagram across the channel at different gate voltages (Vg) for Vdrain = 0.1 V and φb = 0.55 eV

Source Drain

Barrier Height (φb)

1.0x102

1.0x101

1.0x100

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x10-6

0.0 0.2 0.4 0.6 0.8 1.0

Vd = 0.1

Vd = 1.0

φb =

0.25eV0.45eV

0.65eVtox =20Å

Dra

in C

urre

nt I d

(μA

/μm

)

Gate Voltage Vg (V)

Nbulk = 1x1017cm-3 Npocket = 1x1017cm-3

Gate Oxide thickness (tox)

1.0x102

1.0x101

1.0x100

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x103

0.0 0.2 0.4 0.6 0.8 1.0

Vd = 0.1Vd = 1.0

tox = 2 Å5 Å

10 Å

20 Å φb =

0.45eV

Dra

in C

urre

nt I d

(μA

/μm

)

Gate Voltage Vg (V)

S=80mV/decade

Pocket Doping (Npocket) to improve ION/IOFF

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.210-12

10-11

1x10-10

1x10-9

1x10-8

1x10-7

1x10-6

1x10-5

1x10-4

p_1e19 p_8e18 p_4e18 p_1e18 no pocket n_1e18 n_4e18 n_8e18 n_1e19

Dra

in C

urre

nt Id

(A/µ

m)

Gate Voltage Vg (V)

Φb = 0.45 eVtox = 5 Å.

•As n-type pocket doping ↑tunneling distance ↓ (whereby reducing threshold voltage)

•n-type pocket doping ↑; subsurface conduction increases

•p-type doping ↑ a region with high threshold is obtained near the source

•This reduces subsurface conduction and Ion/Ioff ratio considerably.

1x

1x S=90mV/decade

Id-Vd curves

φb = 0.45 eV

tox = 5 AO

Vg = 1 V

0.8 V

0.6 V

0.4 VDra

in C

urre

nt I d

(μA

/μm

)

Drain Voltage Vd (V)0.0 0.2 0.80.4 1.00.6

0100200300400500600700800900

100011001200

•Due to much better control of SCEs the Rout at a given ID is much higher than for a conventional device.

•However, Ion is always smaller than conventional MOSFET at same (Vg – Vth) at a given toxwhich degrades the gm/IDS ratio

•This is due to a drop at the schottky junction which reduces effective drain-source voltage (VDS)

The Tunnel Source MOSFET

“A novel device structure incorporating gate controlled source injection by band-to-band tunneling”

Device Physics Enabled by small-dimensions:Quantum Mechanical TunnelingQuantum Mechanical Tunneling

(Band(Band--toto--Band)Band)

Basic Equation used for the tunneling current: Esaki Diode integral IIVV--CC==AA ∫∫ FFV V (E)*(E)*nnVV (E)*T(E)*Tt t *[1*[1--FFC C (E)(E)]*]*nnCC (E)* (E)* u(E)dEu(E)dE

Tunneling Probability(Tt )dependent on the Tunneling width

Fermi Selection RuleFFVV (E)* (E)* [1[1--FFCC (E)(E)]*]*u(Eu(E))

Where u(E) =1 if there is availability of states to tunnel to; 0 otherwise. FV(E) and FC(E) are Fermi-Dirac distribution functions for the initial (valence band) and final (conduction band) energy states.

governed by

governed by

Tunneling Source Transistors

• Gate controlled P+-N+ tunneling junction is used as a source of electrons (Tunneling width is reduced by the fully depleted N+ layer)• Novel device concept based on Band-to-Band Tunneling

The Tunnel Source (PNPN) MOSFET

Source DrainGate

P+ N+N+ P+P

Buried Oxide

Fully Depleted N+ layer

S

The Tunnel Source (PNPN) MOSFETGate controls the source-to-channel tunneling current by• modulating the band-alignment between the valence band of the tunneling-source junction and the conduction band of the channel, thus modulating the availability of density of states for tunneling

• modulating the tunneling width (which is already made small because of the narrow and fully depleted n-pocket)

Important condition for successful device operation:•The n-pocket of the PNPN device needs to be narrow (<10nm)•The doping of the pocket should be such that it is fully depleted

The Tunnel Source MOSFET

Valence Band

Conduction Band

(a)

Valence Band

Conduction Band(b)

• When VG < VTH, current level is small since the electrons from the P+ valence band can tunnel only to the trap states

• When VG > VTH, electrons from the P+ source valence band tunnel to empty states in the conduction band of the channel

VG < VTH VG >VTH

Tunneling Width Minimization

For any given width W, doping needs to be less than Ndmax to maintain full depletion. As W decreases, Ndmax ↓ as shown.

As the width W of the N-pocket decreases, the voltage drop across the tunneling junction reduces. A width of 3nm or less is needed for negligible voltage drop.

VG=0.9

VG=0.8VG=0.7VG=0.6

VG=0.9

VG=0.8

VG=0.7

VG=0.6

VG=0.5VG=0.4

VT=0.45 VT=0.35W=3nmND=9x1019cm-3

W=10nmND=1x1019cm-3

Small Pocket Width (W)

A narrow width (W≤3nm) with a doping close to Ndmax gives high IDS

Pocket Doping (ND)

ND ≤ Ndmax for good subthreshold characteristics by minimizing tunneling width.

ND=1.6x1020cm-3

ND=1x1020cm-3

ND=8x1019cm-3

VD=1V

Pocket Doping (ND):

ND > Ndmax results in degraded sub-threshold slope. Device is no longer tunneling limited

1.0x10-9

1.0x10-8

1.0x10-7

1.0x10-6

1.0x10-5

1.0x10-4

1.0x10-3

1.0x10-2

1.0x10-1

1.0x100

1.0x101

1.0x102

1.0x103

1.0x104

I D(µ

A/µ

m)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1-0.1-0.2-0.3VG (V)

ND=8.5x1019cm-3(fullydepleted)

ND=9x1019cm-3(fully depleted)

ND=9.5x1019cm-3(not fully depleted)

VD=1V

Device Performance

1.0x10-91.0x10-81.0x10-71.0x10-61.0x10-51.0x10-41.0x10-31.0x10-21.0x10-11.0x1001.0x1011.0x1021.0x103

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0VG (V)

VD = 0.1 V

VD = 1 V

I D(µ

A/µ

m)

0

10050

150200250300350400450500550

VD (V)

I D(µ

A/µ

m)

VTH = 0.325 V VG = 1 V

0.8 V

0.9 V

0.7 V

0.6 V

0.5 V

0.4 V

0.10.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

SOIMOSFET

TFET

Scaling behavior

LG=100nm

LG=45nm

SummaryMerits of the device

Steep subthreshold slope(<<60mV/dec)

&near infiniteIon/Ioff ratio

Higher drive current

for a given VG-VTH(band bending >

2φB)

Small source-channel coupling

Less Short Channel Effects and low DIBL

Scalableas on-current

controlled by the tunneling

source

High fT(small tunneling time constant

and Less transit time)

High performance digital/analog transistors with high fT and high gain

Even Higher performance using small EG Semiconductor --- Ge

Conclusion

• New Device Structures Exploiting Physical Mechanisms Made Feasible by Nano-dimensions

• Ge has Small EG not just High mobilities• Tunnel-Source Transistors Promosing• Parasitics Still Need Special Attention