study of pic microcontrollers
DESCRIPTION
STUDY OF PIC MICROCONTROLLERS. Design Flow. C CODE. Compiler. Assembly Code. Assembler. Hex File. Chip Programming. I/O Device. Unidirectional Address Bus. Bidirectional Data Bus. Processor. Control Signals. Memory. Basic Micro Computer. BUS Structure. - PowerPoint PPT PresentationTRANSCRIPT
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STUDY OF
PIC MICROCONTROLLERS.
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Design FlowDesign Flow
C CODE
Hex File
Assembly Code
Compiler
Assembler
Chip Programming
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BUS StructureBUS Structure
Bus is a group of lines carrying digital InformationBus is a group of lines carrying digital Information Bus width indicates number of bit lines Bus width indicates number of bit lines Two Types of Buses in any Processor:Two Types of Buses in any Processor:
Data Bus (eg: 8 bit processor has 8 bit data bus. Eg: PIC)Data Bus (eg: 8 bit processor has 8 bit data bus. Eg: PIC) Address Bus (Defines the memory size) Address Bus (Defines the memory size)
I/O Device
Processor
Memory
Bidirectional Data Bus
Unidirectional Address Bus
Control Signals
Basic Micro Computer
Bus is driven by buffers from different devices, processor &memory.
Ques:
How to arbitrate between different devices that want to access the bus at the same time?
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TRISTATE BUFFERSTRISTATE BUFFERS
Regular BUFFERS
INTRODUCTION TO MEMORIES
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Output Buffer
Memory Addressing and AccessMemory Addressing and Access
Input Buffer
Register 0
Register 3
Register 2
Memory Address Decoder
Processor
A0 A1
00
01
10
10
WR
RD
1)Register addresses : 00,01, 10, 11
2)Active Low Wr and Read enable signal comes from control unit
3) Additional chip select also provided if more than one set of memory registers available
Questions:
For a memory of 1 K byte and word size of 8 bits
1) What is the width of MAR
2) How many address lines come out of the decoder
3) What is the register width
4) What is the input/output data width ???
5) What is the size of processor address bus
6) What is the size of the processor data bus
Data Bus
Register 1Memory Address Register[MAR]
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DATA Transfer UnitDATA Transfer Unit
Main Memory location
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DATA Transfer UnitDATA Transfer Unit
Main Memory location along with MAR and Decoder
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DATA Transfer UnitDATA Transfer Unit
Memory with Working Register
WW : work register write (Data bus to register)
WR: Work register read (reg to bus)
WCLK: clock
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DATA Transfer UnitDATA Transfer Unit
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ENHANCED DTU ENHANCED DTU (With Program Counter)(With Program Counter)
Program memory is separate from data memory
OPCODE= instruction codes.
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ENHANCED DTU ENHANCED DTU (With Addition of Control and timing)(With Addition of Control and timing)
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Status of control lines
S.No.
RAWE RE WE IE OWE WW WR Activity
01 0 0 0 1 0 1 0 Transfer data from input port to working register
02 1 0 0 0 0 0 0 Write address into RAM address register (get ready to select an address location in the register file)
03 0 0 1 0 0 0 1 Transfer data from working register into the selected RAM location
04 0 0 0 0 1 0 1 Transfer data from working register to the output port
05 0 1 0 0 0 1 0 Transfer data from selected RAM location into the working register
06 0 1 0 0 1 0 0 Transfer data from selected RAM location into the output port
07 0 0 1 1 0 0 0 Transfer data from input port to working register
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SYSTEM CLOCK and PIPELINING
Instruction execution takes place in 2 stages , each stage needs 4 clock cycles.
Instruction Fetch and Instruction Decode
Fetch: clock1: Increment PC (PC <= PC+1) (phase 1)
clock 2,3: idle.
Clock 4: Instruction loaded in to IR
Decode:
clock 1 : Instruction decode
clock 2 : Fetch data from register or port
clock 3 :Operations carried out with data
Clock 4 :Results loaded back to destination
FETCH AND DECODE ARE INDEPENDENT. HENCE THEY CAN BE DONE IN PARALLEL. THIS IS CALLED PIPELINING. This is a 2 stage pipelining concept.
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Instruction Cycle Pipelining
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12 3 4
Increment PC
Fetch & Loadinstruction into IR
Decode instruction
Fetch data
Process data
Load results
Machine cycle N+2
12 3 41
2 3 4
Machine cycle N+1Machine cycle N
Fetch & executeinstruction N
Instruction Cycle Pipelining