study and design of a dc-dc converter for third generation

IN DEGREE PROJECT ELECTRICAL ENGINEERING,SECOND CYCLE, 30 CREDITS

, STOCKHOLM SWEDEN 2018

Study and Design of a DC-DC Converter for Third Generation Solar Cells

STURLA LANGE

KTH ROYAL INSTITUTE OF TECHNOLOGYSCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

KTH ROYAL INSTITUTE OF TECHNOLOGY

MASTER’S THESIS

Study and Design of a DC-DC Converter forThird Generation Solar Cells

Author:Sturla LANGE

Supervisor:Gael CHOSSON

Examiner:Ana RUSU

Degree project in Electrical Engineering

Integrated Circuits and System Group, Department of ElectronicsSchool of Electrical Engineering and Computer Science

June 18, 2018

http://www.kth.se

https://www.kth.se/ele/units/ekt

https://www.kth.se/en/eecs/skolan-for-elektroteknik-och-datavetenskap-1.760855

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AbstractSchool of Electrical Engineering and Computer Science


by Sturla LANGE

The perceived battery capacity of battery-powered devices can be increased by harvestingenergy from readily available sources. Third generation solar cells are a good candidate forthis purpose since they can be integrated with these battery-powered devices and harvestpower from diffused light. For a single third generation solar cell to be useful in the contextof charging a Lithium based battery, the voltage must be increased tenfold. To increase thisperceived battery capacity as much as possible, efficiency is crucial. In this thesis, DC-DC converter topologies and designs are studied from a system design perspective. Thespecifications of a converter suitable for interfacing Dye-Sensitised Solar Cells with Lithiumbatteries are described and a market research is conducted based on those specifications.A comparison of the available commercial solutions is presented, highlighting the mostsuitable options. However, none of the commercial solutions met the specifications to the fullextent. The design process of two DC-DC converters is presented, one is a Boost converteroperating in Continuous Conduction Mode and the other is a Boost converter operating inDiscontinuous Conduction Mode. A comparison of the two designs highlights the advantagesof operating the Boost converter in Discontinuous Conduction Mode when interfaced witha Dye-Sensitised Solar Cell. The design with a Boost converter operating in DiscontinuousConduction Mode has an efficiency of 80.3% and is capable of tracking the Maximum PowerPoint of the Dye-Sensitised Solar Cell.

Keywords

Third-generation solar cell; Dye-sensitized solar cell; DC-DC converter; Boost converter.

HTTP://WWW.KTH.SE


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SammanfattningSchool of Electrical Engineering and Computer Science

Electrical Engineering


by Sturla LANGE

Den uppfattade batterikapaciteten hos batteridrivna enheter kan ökas genom att skördaenergi från lättillgängliga källor. Tredje generationens solceller är en bra kandidat fördetta ändamål eftersom de kan integreras med dessa batteridrivna enheter och skördaström från spritt ljus. För att en enda tredje generationens solcell ska vara användbar isamband med laddning av ett litiumbaserat batteri måste spänningen ökas tiofaldigt. Föratt öka denna uppfattade batterikapacitet så mycket som möjligt är effektiviteten avgörande.I denna avhandling studeras topologier och strategier för DC-DC-omvandlare från ettsystemdesignperspektiv. Specifikationerna för en omvandlare som är lämplig för att anslutaDye-sensitized solceller med litiumbatterier beskrivs och en marknadsundersökning utförsutifrån dessa specifikationer. En jämförelse av de tillgängliga kommersiella lösningarnapresenteras och belyser de lämpligaste alternativen. Ingen av de kommersiella lösningarnauppfyllde emellertid specifikationerna i sin helhet. Designprocessen för två DC-DC-omvandlare presenteras, en Boost-omvandlare som arbetar i kontinuerligt ledande lägeoch en Boost-omvandlare som arbetar i diskontinuerligt ledande läge. En jämförelse avde två designerna belyser fördelarna med att driva Boost-omvandlaren i diskontinuerligtledningsläge när den kopplats till en färgkänslig solcell. Konstruktionen med en Boost-omvandlare som arbetar i diskontinuerlig ledningsläge har en effektivitet på 80.3% och kanspåra den maximala effektpunkten för solcellen.

Nyckelord

Tredje generationens solceller; Dye-sensitized solceller; DC-DC-omvandlare; Boost-omvandlare.

HTTP://WWW.KTH.SE


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AcknowledgementsI feel privileged that I had the opportunity to get to know Mr. Gael Chosson and experiencea part of the operation within Exeger. He has been most helpful and resourceful throughoutthe project. During my work on this degree project I have been so lucky to have the guidanceof Prof. Ana Rusu in the Integrated Circuits and Systems group, at the Department ofElectronics who has provided valuable feedback during the execution of the project.

I would also like to thank Sven A. Södergren for the discussions on solar cells and theircharacteristics, which proved very valuable for my work.

Finally, I would like to thank my parents and my girlfriend for their love and supportthroughout my studies and especially during the last few months.

Stockholm, June 18, 2018Sturla Lange

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Contents

Abstract i

Sammanfattning ii

Acknowledgements iii

Table of contents v

List of Figures vi

List of Tables vii

List of Abbreviations viii

1 Introduction 11.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4.1 Benefits, Ethics and Sustainability . . . . . . . . . . . . . . . . . . . 41.5 Methodology / Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.6 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.7 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Background 72.1 Dye-Sensitised Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Pulse-Width Modulated DC-DC Converters . . . . . . . . . . . . . . . . . . 8

2.2.1 DC-DC Converter Modelling . . . . . . . . . . . . . . . . . . . . . . 92.2.2 Basic converter Topologies . . . . . . . . . . . . . . . . . . . . . . . 102.2.3 Control Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2.4 Evaluation of solutions . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Lithium-Based Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Design Methodology 213.1 The Engineering Design Process . . . . . . . . . . . . . . . . . . . . . . . . 213.2 Design Specifications For a DC-DC Converter Interfaced With a DSSC and

Li-Based Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.3 Evaluation of Commercially Available Solutions . . . . . . . . . . . . . . . . 24

3.3.1 Linear Technology - LTC3105 . . . . . . . . . . . . . . . . . . . . . 253.3.2 Linear Technology - LTC3108 . . . . . . . . . . . . . . . . . . . . . 253.3.3 Texas Instruments - TPS6120x . . . . . . . . . . . . . . . . . . . . . 263.3.4 Texas Instruments - BQ25505 . . . . . . . . . . . . . . . . . . . . . 263.3.5 Cypress - MB39C831 . . . . . . . . . . . . . . . . . . . . . . . . . 273.3.6 ST Microelectronics - SPV1050 . . . . . . . . . . . . . . . . . . . . 27

v

3.3.7 Analog Devices - ADP5091 . . . . . . . . . . . . . . . . . . . . . . 283.3.8 Monolithic Power Systems - MP3418 . . . . . . . . . . . . . . . . . 283.3.9 Comparison of Potential Commercial Solutions . . . . . . . . . . . . 29

4 Proposed Circuit Solutions 304.1 Boost Converter in Continuous Conduction Mode . . . . . . . . . . . . . . . 31

4.1.1 Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314.1.2 Design Oriented Analysis . . . . . . . . . . . . . . . . . . . . . . . 314.1.3 Circuit validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.1.4 Worst-Case Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 384.1.5 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2 Boost Converter in Discontinuous Conduction Mode . . . . . . . . . . . . . 404.2.1 Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.2.2 Design Oriented Analysis . . . . . . . . . . . . . . . . . . . . . . . 414.2.3 Circuit Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.2.4 Worst-Case Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 464.2.5 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.3.1 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.3.2 Analysis of Topologies and Control Strategies . . . . . . . . . . . . . 484.3.3 Overall Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5 Conclusions and Future Work 49

Bibliography 51

vi

List of Figures

1.1 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Ideal DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Equivalent circuit for an ideal solar cell . . . . . . . . . . . . . . . . . . . . 72.2 The three generations of solar cells (I-III) with respect to cost and efficiency . 82.3 The Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 The limits of load angles for the Buck converter indicating its ability to sweep

the I-V plane, assuming tan−1(

1RL

)= 45° . . . . . . . . . . . . . . . . . . . 13

2.5 The Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.6 The limits of load angles for the Boost converter indicating its ability to

sweep the I-V plane, assuming tan−1(

1RL

)= 45° . . . . . . . . . . . . . . . 15

2.7 The Buck-Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.8 The Cuk converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.9 The Single-Ended Primary-Inductor converter . . . . . . . . . . . . . . . . . 172.10 The limits of load angles for the Buck-Boost, Cuk and SEPIC indicating their

ability to sweep the I-V plane, assuming tan−1(

1RL

)= 45° . . . . . . . . . . 18

2.11 Voltage Mode control block diagram . . . . . . . . . . . . . . . . . . . . . . 182.12 Current Programmed Mode block diagram . . . . . . . . . . . . . . . . . . . 19

4.1 Boost converter input-output characteristics . . . . . . . . . . . . . . . . . . 334.2 Boost converter control-output characteristics . . . . . . . . . . . . . . . . . 344.3 Bode plot for the compensator described in Equation (4.20) . . . . . . . . . . 354.4 Compensated closed-loop transfer function of the Boost converter . . . . . . 354.5 Simulation setup for model verification of static characteristics in LTspice . . 364.6 Model verification of static characteristics for the Boost in CCM . . . . . . . 374.7 Simulation setup for model verification of dynamic characteristics in LTspice 374.8 Model verification of dynamic characteristics for the Boost in CCM . . . . . 384.9 Simplified model using the Thévenin equivalent for the DSSC at a single

operating point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.10 MPPT efficiency as a function of k . . . . . . . . . . . . . . . . . . . . . . . 404.11 Input-output characteristics of the Boost converter in DCM . . . . . . . . . . 434.12 Simulation setup from LTspice . . . . . . . . . . . . . . . . . . . . . . . . . 454.13 Model verification for Boost converter in DCM . . . . . . . . . . . . . . . . 454.14 Simulation setup for model verification of dynamic characteristics in LTspice 464.15 Model verification of dynamic characteristics for the Boost converter in DCM 46

List of Tables

3.1 Design Specifications for a DC-DC Converter Interfaced With a DSSC andLi-Based Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Evaluation of LTC3105 with respect to specifications . . . . . . . . . . . . . 253.3 Evaluation of LTC3105 with respect to specifications . . . . . . . . . . . . . 253.4 Evaluation of TPS6120x with respect to specifications . . . . . . . . . . . . . 263.5 Evaluation of BQ25505 with respect to specifications . . . . . . . . . . . . . 263.6 Evaluation of MB39C831 with respect to specifications . . . . . . . . . . . . 273.7 Evaluation of SPV1050 with respect to specifications . . . . . . . . . . . . . 273.8 Evaluation of ADP5091 with respect to specifications . . . . . . . . . . . . . 283.9 Evaluation of MP3418 with respect to specifications . . . . . . . . . . . . . . 283.10 Evaluation of commercially available solutions with respect to the design

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 Relative losses as a function of the voltage conversion ratio, M . . . . . . . . 304.2 Calculated values for Boost converter in CCM . . . . . . . . . . . . . . . . . 324.3 Calculated values for Boost converter in DCM . . . . . . . . . . . . . . . . . 424.4 Calculated worst case phase margin for Boost converter in DCM . . . . . . . 474.5 Calculated values for Boost converter in DCM and CCM . . . . . . . . . . . 48

viii

List of Abbreviations

CCM Continuous Conduction Mode

DCM Discontinuous Conduction Mode

DSSC Dye-Sensitised Solar Cell

ESR Equivalent Series Resistance

FoM Figure-of-Merit

IoT Internet of Things

LDO Linear Drop-Out

MPP Maximum Power Point

MPPT Maximum Power Point Tracking

PWM Pulse-Width Modulation

SC Switched-Capacitor

SEPIC Single-Ended Primary-Inductor Converter

TF Transfer Function

1

Chapter 1

Introduction

This thesis presents a study of DC-DC converters for third generation solar cells and thedesign of such a converter. A market research is conducted and a comparison of the availablecommercial solutions is presented. The work was proposed by Exeger, a Swedish companyworking on commercialising third generation solar cells. The project was conducted atExeger.

First generation solar cells are the most commonly available solar cells and they arebased on silicon wafers. Second generation solar cells are based on thin-film technology andthe third generation of solar cells improves on the efficiency of the second generation bycircumventing the Shockley-Queisser limit [1]. Third generation solar cells are cheap andcan be easily manufactured compared to their silicon-based counterparts [2]. They are alsothin and light, making them well suited for integration with embedded devices such as thedevices for Internet of Things (IoT) applications or consumer devices, like tablets. Due tothe increasing number of embedded devices in use, the reliance on batteries to power themincreases. Replacing and recharging the batteries can be costly in terms of time and money.In the case of IoT devices it is highly beneficial to decrease the frequency of these operationssince the number of devices is extremely high [3]. There are two solutions to reducethe frequency of replacements and charging: reducing power usage and increasing batterycapacity. Power consumption of embedded devices can be reduced through smart design andtechnology scaling. However, for many embedded devices, increasing the battery capacity isnot feasible. This is because for embedded devices constraints are set for parameters such asshape, size and cost. By constantly recharging the device battery via energy harvesting, thefrequency of battery replacements or recharging can be reduced, even eliminated this needin some cases. Exeger intends to integrate their cells with embedded consumer devices tocharge the battery of the device [4]. The device batteries are typically Lithium (Li) basedbatteries [5, Section 26.6].

Exeger’s solar cells are based on the Dye-Sensitised Solar Cell (DSSC) technology. Theoutput voltage of a DSSC is typically low, around 0.4V. Whereas Li-based batteries requirea charging voltage around 4.0V. The output voltage from the DSSC needs to be convertedto meet the appropriate charging voltage for a Li-based battery. A DC-DC converter witha fairly high voltage conversion ratio is needed to step the 0.4V output of the DSSC up tothe recommended 4.0V charging voltage of a Li-based battery. This is illustrated in Figure1.1 where the Li-based battery is represented with the load on the right. The aim is to havea highly efficient DC-DC converter, to make use of as much of the power generated bythe photovoltaic cell as possible. This degree project covers different DC-DC convertertopologies and designs. The result is a thesis containing a comprehensive overview ofappropriate commercially available DC-DC converters for use with Exeger’s DSSCs and adetailed analysis of the most promising DC-DC converter topology for a customised solution.

Chapter 1. Introduction 2

ExegerDSSC

0.4 VDC DC-DCConverter

4 VDCLoad

FIGURE 1.1: System overview

1.1 Background

To make the integration of DSSCs with embedded devices more appealing it is important toachieve high efficiency in the overall system. This can be achieved by designing the DC-DCconverter specifically for its intended application. A DC-DC converter is an electrical systemthat accepts a DC voltage (VI) at a certain level and outputs a DC voltage (VO) at anotherlevel, the ratio of these two voltages is referred to as the converter’s voltage conversion ratio

MV DC =VO

VI. (1.1)

Converters with MV DC > 1 are said to be step-up or boosting converters while converters with0 < MV DC < 1 are called step-down or bucking converters [6]. A model of an ideal DC-DCconverter, adapted from [6, Figure 1.5], is depicted in Figure 1.2.

−+VI

II

MV DC · IO

+

−

VO

Load

IO

−+ MV DC ·VI

FIGURE 1.2: Ideal DC-DC converter

In an ideal DC-DC converter all input power is transferred to the output. Real DC-DCconverters have components that dissipate power, which leads to lower power at the outputthan at the input. The ratio of the output power to the input power is the efficiency (η) of theconverter.

η =PO

PI(1.2)

An overview of the system as it is considered in this thesis is given in Figure 1.1. TheDSSC produces electricity by harvesting energy from the available light in its surroundings.The generated electricity which is at a low voltage is boosted by a DC-DC converter to theappropriate voltage for charging Li-based batteries.

DC-DC converters are commonly divided into three categories: Switched-Capacitor(SC) converters, Linear Drop-Out (LDO) regulators and Pulse-Width Modulation (PWM)converters. Capacitors and switches move charge from the input to the output in SCconverters, resulting in altered output voltage that can be higher or lower than the inputvoltage [7]. LDO regulators provide variable resistance with a controlled feedback loop toregulate voltage. The variable resistance is implemented with a transistor and controlled byadjusting its gate voltage. LDOs can only output lower voltage than their input voltage [6].PWM converters are based on switching current through an inductor and their output voltageis controlled by a signal applied to the switch. PWM DC-DC converters are commonlyemployed as voltage regulators and require a control system to accomplish voltage regulation.


In the case of DC-DC converters that are used with solar cells the PWM controller iscommonly designed to track the solar cells Maximum Power Point (MPP). The MPP is apoint on the current-voltage characteristic curve of a solar cell, at a certain level of solarradiation and temperature, where maximum power is delivered to the load of the solar cell[8]. By tracking the MPP the power transfer is increased. This is referred to as MaximumPower Point Tracking (MPPT) [9]. To compare DC-DC converters, characteristics such asthermal regulation, line regulation and load regulation are important. These quantify howwell the converter responds to environmental changes [6]. In PWM converters device stressfactor has been used to estimate the size needed for the silicon devices of the converter, lowerstress means smaller devices [10]. When the voltage has been boosted a Li-based battery canbe charged. For safe charging of Li-based batteries methods to control the charge rate areused, these include constant-current, constant-voltage and a combination of the two [11].

1.2 Problem

Currently available commercial DC-DC converters can achieve high efficiency levels andhigh voltage conversion ratios in typical conditions specified in their data-sheet. When DC-DC converters are employed in conditions outside the specified range their efficiency tendsto be reduced. Exeger has conducted tests where their DSSCs are paired with differentcommercially available DC-DC converters. The results have confirmed that the DC-DCconverters display reduced efficiency. This is their initiative for the degree project presentedin this thesis. By choosing the topology and control strategy the design of the DC-DCconverter can be entirely dictated by the specifications of the intended application, as opposedto a device that performs well for a range of different applications. There are multipletopologies and control strategies to choose from and the evaluation of them has to be donewith regard to the application specifications to reach high efficiency levels. The goal isto identify whether any topologies and control strategies can be used to design a DC-DCconverter for 0.4V to 4.0V conversion with high efficiency.

1.3 Purpose

The purpose of this thesis is to study DC-DC converter topologies and control strategies forthird generation solar cells. It presents the comparison of available solutions found in theliterature. By analysing the most promising solutions further the most appropriate solutionfor converting voltage from Exeger’s DSSCs to charge Li-based batteries is presented. Fromthis analysis, a DC-DC converter with the potential to meet the specifications in the expectedoperating conditions is designed and analysed in this thesis.

1.4 Goals

The goal of the project is to investigate and identify DC-DC converters suitable for Exeger’sspecific application, charging battery-powered embedded devices with their DSSC. Thecollected data is summarised and presented in this thesis. Circuits based on the mostpromising topologies and control strategies are analysed. Analysis and simulations are usedto evaluate the designs presented in this thesis and evaluate their efficiency. Documentshanded over to Exeger at the end of the project will be the thesis, the circuits in a formatcompatible with LTspice as well as simulation setup and output data. Based on investigationand the preliminary designs presented in this thesis, a future design can hopefully result in ahighly efficient system for integration with embedded consumer devices.


1.4.1 Benefits, Ethics and Sustainability

Advancing technology for the sake of technology is a fair objective but the wider effectsof work such as this thesis should be considered. By having devices that don’t have to berecharged very often or have their batteries replaced, opportunities for people with limitedaccess to electrical power to use these devices increase. Since the DSSCs can be integratedwith internet connected devices the availability of these devices can be increased in locationswith limited or unstable access to electricity. It has been shown that increasing the availabilityof information has a good impact on the economy of the group of people where informationavailability increases [12]. The availability of information on the internet is immense and byacquiring access to it communities get a new opportunity to prosper.

The power generated by DSSCs is sustainable since they don’t emit greenhouse gaseswhile turning solar energy into electrical energy. Thus, by increasing the efficiency of powertransfer from the cells to devices less energy from non-sustainable sources is needed. Thiscan potentially have a big effect on the sustainability of IoT devices that need little powerindividually but collectively use vast amounts of power. For example, the standby powerusage of mains connected IoT devices reported in [13, Figure 3] is already in the tens of TeraWatt hours and expected to keep increasing.

By developing cheap devices that can be distributed in remote places the number ofdevices would likely increase and much waste would be produced. However, less wastewould be produced by providing alternative charging methods to "charge packs" which areexternal batteries commonly used with consumer mobile devices.

Ethics can be looked at for every situation, there is more than only one correct solutionand each of these different solutions have strengths and weaknesses attached. Engineersshape the world with innovations, like integrating a DSSC with consumer devices, and it isimportant that the work is done in the interest of the community as a whole.

By integrating DSSCs with consumer devices these devices can be made less reliant ontheir battery, through this the possibility to empower people arises. In the long run this willenhance human welfare more than it will have negative environmental impact.

The further we progress the use of energy harvesting such as integrating DSSCs withconsumer devices, the more we can replace the use of fossil fuels which will create a cleanerenvironment and a sustainable source of energy.

1.5 Methodology / Methods

To benefit the scientific community, research must focus on obtaining truthful conclusions.This means being careful not to alter the result to align with the authors needs or desires.To reach a correct result, the choice of research methodology and method is essential. Theresearch described in this thesis is quantitative as opposed to qualitative since the research isnot based on observing behaviours, opinions or meanings but rather on measuring variablesand processing data. The "Quantitative Research method supports experiments and testing bymeasuring variables to verify or falsify theories and hypothesis" [14]. The applied researchmethod is used with a deductive approach to solve the problem by understanding the theoryand limitations of different DC-DC converter architectures and identify the ones that meetthe specifications [14]. The hypothesis that a feasible DC-DC converter exists that has highefficiency is tested. To aid with the design of a DC-DC converter the Engineering DesignProcess discussed in [10] is used. The Engineering Design Process is comprised of sevensteps. The process starts with the specification of the design. The specifications of a solutionto interface a DSSC with a Li-based battery are presented in Section 3.2. Next, a solution isproposed. The discussion of the advantages of the DC-DC converter topologies consideredin this thesis is in Section 4 which concludes with the proposal of a solution. A model of the


proposed solution is used for design-oriented analysis. The model is verified to be appropriateby comparing the predictions of the model to a physical prototype or computer simulations.Simulations are conducted with LTspice1 which is a circuit simulator based on spice. LTspicewas developed by Linear Technology and is distributed for free. Linear Technology is nowa part of Analog Devices. The design is analysed for worst-case conditions and verified tooperate under these. Finally the need for iteration of the previous steps is decided based onthe ability of the design to meet the specifications. These steps are described in Sections 4.1and 4.2, for the respective designs presented there.

1.6 Delimitations

For this study some delimitations have been made regarding the choice of modelling methods.Other choices might have given different results. Certain aspects pertaining to the applicationwill be considered out of scope for this thesis. A battery charging block will preferably beimplemented to manage the current-voltage characteristics presented to the battery to ensuresafe charging. By managing multiple DSSCs a DC-DC converter can possibly apply methodsto counteract shading effects and sizing differences, this is out of scope for this thesis. Withthe aim of designing a functional DC-DC converter there are numerous system componentsneeded for operation. The focus in this thesis is on the main functionality of the DC-DCconverter, namely the voltage conversion/regulation and tracking of the maximum powerpoint. To implement a fully functional DC-DC converter additional system components suchas a clock generator, voltage reference, current limiter and short circuit protection would haveto be designed. Clock generators are needed for the pulsed signals of the design, importantfactors in the design of these generators are their accuracy as well as rise and fall times.In the presented work the clock signal has been assumed to be ideal. The generation ofreference voltages is needed in control systems, this voltage must be stable despite changesin environment variables such as temperature. The reference voltages are assumed to beideal in this work. To ensure reliability, various methods can be used to protect againstover-current and short circuits. Current limiting is needed to protect electrical components,especially switches.

1.7 Outline

The thesis is organised as follows. The theory of DSSCs, DC-DC converters and Li-based batteries is presented in Chapter two. Here a discussion of various DC-DC convertertopologies and their characteristics such as conduction modes, input resistance and controlstrategies can be found.

In the third chapter the design methodology is discussed. There is a short descriptionof the Engineering Design Process and a discussion of how it is applied in this thesis tothe design of a DC-DC converter. Next, the specifications of the design are presented.By presenting the design specifications clearly, the evaluation of commercial solutions canbe conducted. During the design process in Chapter four, the specifications are used forconstraints and evaluation. Finally, the market research is presented and the availablecommercial solutions are compared to the design specifications.

In Chapter four the reasoning for the choice of topology, based on the data collectedin Chapter two, is presented. The design of a Boost converter operating in continuousconduction mode is presented and evaluated in the final step of the design process. Thedesign of a Boost converter operating in discontinuous conduction mode is then presented

1http://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html

http://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html


and adjustments are made for the shortcomings of the first design. Furthermore, the resultsare presented and the two designs presented in the chapter are compared. Conclusions aredrawn in Chapter five and future work is discussed.

7

Chapter 2

Background

To integrate DSSCs with embedded consumer devices, such as tablets, there are three systemcomponents that are of most importance: the input from the DSSC, the DC-DC converterperforming a voltage conversion and the load presented by the battery while charging. Thesecomponents and their relations are shown in Figure 1.1. To support the discussion for thechoice of topology and control strategy, the background theory of these system componentshas been researched.

In this chapter the system components, their background theory and the characteristicsthat are relevant for this work are discussed.

2.1 Dye-Sensitised Solar Cells

Solar cells convert energy in the form of light into electricity, this happens due to lightbeing absorbed into the solar cell creating an electron-hole pair. When the pair is separatedelectrical power is generated [15]. The I-V characteristic of an ideal solar cell is given by

I = Iph− I0

[exp(

qVkT

)−1]

(2.1)

where Iph is the photo-generated current, IO is the diode saturation current, q is theelectron charge, V is the voltage at the terminals of the solar cell, k is Boltzmann’s constantand T is absolute temperature [15]. This relationship can be represented with the equivalentcircuit model shown in Figure 2.1.

Iph D

IPV

+

−

VPV

FIGURE 2.1: Equivalent circuit for an ideal solar cell

Solar cell technology is commonly divided into generations, the first generation is themost common and is based on silicon wafers. Second generation solar cells are based onthin-film technology, cutting the starting cost associated with silicon wafers [16]. The firsttwo generations are limited by the Shockley-Queisser limit [1] while the third-generation,by definition, circumvents this limit. Exeger’s DSSCs are a third generation solar cell

Chapter 2. Background 8

technology. By exploiting multiple energy levels, the efficiency limit of solar cells can beshifted from the Shockley-Queisser limit to the thermodynamic limit of 86.8% efficiencyfor an infinite stack of tandem cells, each operated independently [16]. This is clearlyillustrated in Figure 2.2 where the Shockley-Queisser limit is represented by a grey boxbetween 31% and 41% efficiency and the Thermodynamic limit by a similar box from 67%up to 87% efficiency. The figure was adapted from [16, Figure 1] by [17] and made accessibleunder the CC BY-NC-ND1 licence. The thermodynamic limit stems from the second law ofthermodynamics: dS > δQ

T , where S, Q and T are a system’s entropy, heat and temperaturerespectively. The conversion of solar heat into chemical energy is limited by this due to theentropy of solar heat. However, the conversion of chemical energy into electrical energy hasno such limit since both are free of entropy, meaning that in theory it can be 100% efficient[18].

FIGURE 2.2: The three generations of solar cells (I-III) with respect to costand efficiency

The breakthrough of using TiO2 in DSSCs was presented in [19], which resulted in muchhigher efficiency as well as better stability than previous experiments with DSSCs usingdifferent semiconducting materials. DSSCs are a good candidate for charging embeddedconsumer devices since they can be easily integrated with the devices and harvest powerfrom diffused light, such as indoor lighting [19].

2.2 Pulse-Width Modulated DC-DC Converters

Transformers are used to convert AC voltages with ease and high efficiency. Unlike ACvoltage conversion there is no simple solution to DC voltage conversion. During the 1930’sthere were DC-DC converters in industrial use but as of the 1940’s and especially after the endof the second world war, DC-DC converters were found to be practical for communicationdevices that used low DC voltages [20]. As various designs for DC-DC converters utilisingswitches were derived from chopper circuits it became apparent that this method was farsuperior to previous methods. Between the 1970’s and 1990’s numerous novel topologies[21–23] were introduced [20]. These converters, among other inventions, enabled thedevelopment of mobile devices that would not have been practical with older methods ofDC-DC conversion due to low efficiency and the physical size of the implementations.

DC-DC converters have been realised with many different topologies and for even moreapplications. Multiple classifications exist for the different topologies, commonly DC-DC

1https://creativecommons.org/licenses/by-nc-nd/3.0/

https://creativecommons.org/licenses/by-nc-nd/3.0/


converters are divided into three groups. Linear Drop-Out (LDO) regulators provide variableresistance with a controlled feedback loop to regulate voltage. LDOs can only outputlower voltage than their input voltage [6]. Switched-capacitor (SC) converters, as the namesuggests, make use of capacitors and switches to convert between DC voltages. For SCconverters the control of the switches is regularly implemented in such a way that the chargeof a capacitor is moved around, giving it a different potential [7]. The third group consists ofPulse-width modulated (PWM) DC-DC converters. These converters utilise switches alongwith power storing elements, most notably inductors, to achieve conversion between two DCvoltages. The switches are controlled by an input signal with pulses of varying width, byvarying the pulse widths the conversion ratio of the converter can be altered [21]. The PWMDC-DC converters typically have an efficiency of around 80%-90% [6].

PWM DC-DC converters have different characteristics, most notably whether voltagegets stepped up or down. Some topologies are capable of both. Isolating topologieshave galvanic isolation between the input and output of the converter, this is achieved byusing transformers. Non-isolating do not have galvanic isolation. Inverting topologies havevoltage inversion, meaning their output voltage polarity is opposite to that of their inputvoltage, while non-inverting do not. Single-ended topologies have a single outgoing terminalwhile multiple-ended topologies have multiple terminals that can have different voltages[6]. PWM DC-DC converters have two operating modes: Continuous Conduction Mode(CCM) and Discontinuous Conduction Mode (DCM). The conduction refers to the inductorcurrent, which goes to zero under certain conditions. This leads to a change in the convertercharacteristics, such as its voltage conversion ratio. [24] highlights that systems with solarcell sources should not have a discontinuous input current since this means that for a certainperiod the energy generated by the cell will not be utilised. For some topologies, e.g. theBoost converter, the input current is continuous when operated in CCM and discontinuouswhen operated in DCM.

Losses appear in the inductor resistance, the capacitor equivalent series resistance (ESR),the MOSFET on-resistance and due to charge lost in the MOSFET output capacitor whileswitching. Since the dominating losses in many converters are due to switching, it is usefulto represent the total losses in the following way

PLS = Pcond +Pf ixed + fsWsw, (2.2)

where the Pf ixed represents the fixed losses due to control, fsWsw are switching losses andPcond are conduction losses.The efficiency is

η =PO

PI=

11+ PLS

PO

, (2.3)

where PO is the output power and PI is the input power. In the following sections thefunctionality and characteristics of the basic DC-DC converter topologies will be discussed.

2.2.1 DC-DC Converter Modelling

By modelling systems by mathematical representations, engineers seek to simplify thesystem and gain insight into the behaviour of the system. The simplification is done byapplying approximations and neglecting some system components. This allows the engineerto design a system to meet specifications [10].

A simple model of the steady-state operation of DC-DC converters can be derived bymaking three important assumptions. The first assumption concerns the volt-second balancefor inductors, which is that the changes in inductor voltage during one switching period add


up to zero.

0 =∫ Ts

0vL(t)dt (2.4)

The second assumption is capacitor charge balance, where the changes in the capacitorcurrent during one switching period add up to zero.

0 =∫ Ts

0iC(t)dt (2.5)

The small ripple approximation for capacitors is the third assumption. It assumes is that thecommon requirement of low output voltage ripple is met. If the converter is operating in CCMthe small ripple approximation can also be applied to inductors. When a converter operatesin DCM, the inductor ripple is by definition large so the approximation is invalid. Anothercase when the small ripple approximation breaks down is when the modelled converter has atwo-pole output filter [10].

To evaluate a converter under dynamic conditions, i.e. during input voltage or duty-cycletransitions, the steady-state model is not sufficient. A small-signal model is needed that islinearised around a quiescent operating point predicted by the steady-state model. In [10]low-frequency AC variations are modelled by averaging inductor and capacitor waveformsover a single period of the switching signal, in effect this replaces the inductor volt-secondand capacitor charge balance approximations. The small-ripple approximation is still validin this case. Common modelling approaches include state-space averaging and the averageswitch model [10].

It is very common to use state-space descriptions in control theory. State-space averagingmakes use of state-space descriptions to derive small-signal models of PWM DC-DCconverters. To develop the state-space description of a PWM DC-DC converter the sub-circuits for the possible switch positions must be inspected. Sets of matrices can be derivedthat describe the system behaviour during the period that the switches are in each of thepossible positions. The averaged state-space model is derived by multiplying the matrix for agiven switch position with the portion of the PWM signal spent in that position. Furthermore,the assumption of small ripple is made for the state-space average model [10].

The average switch model, also known as circuit averaging is fundamentally the samemethod as state-space averaging but without writing out the state-space matrices. Simulationswith a circuit simulator such as LTspice can benefit from applying the averaged model. Thisignores the switching ripple and focuses on low-frequency variations that are of more interest[10].

2.2.2 Basic converter Topologies

The basic PWM DC-DC converter topologies are the Buck, Boost and Buck-Boost converters[6]. These three topologies consist of a single active switch, a diode, a capacitor, andan inductor. In addition, two topologies each with two inductors and two capacitors arediscussed, these are the Single-Ended Primary-Inductor Converter (SEPIC) and the Cukconverter.

PWM DC-DC converters can operate in two modes, Continuous Conduction Mode(CCM) and Discontinuous Conduction Mode (DCM). The modes are defined according tothe current in the converter inductor, when the current goes to zero at some point during thepulsing signal’s period the converter is said to be operating in DCM, otherwise it is said tooperate in CCM. When operated in DCM the converter voltage conversion ratio is not thesame as when operated in CCM. The voltage conversion ratios for the basic topologies inboth CCM and DCM are derived in [6, 10].


There are two main sources of losses in DC-DC converters, the frequency dependentswitching losses and the frequency independent conduction losses. The switching losses aredirectly proportional to the frequency fs as expressed by

Psw = fsWsw. (2.6)

Where Wsw is the energy lost in the switches. The switching energy is found in the same wayfor all of the converters considered in this thesis,

Wsw =CDSV 2O. (2.7)

Where CDS is the capacitance between drain and source of the transistor used for implementingthe active switch and VO is the output voltage.

Conduction losses are independent of the switching frequency and arise mainly frominductor series resistance rL, capacitor equivalent series resistance rC, transistor on-resistanceRon as well as diode resistance RF and forward voltage VF . The conduction losses Pcondare evaluated assuming that the inductor current is ripple free [6]. Conduction losses andswitching losses increase with the power transferred though the converter. However, lossesdue to the operation of the components required for control of the converter do not. Theselosses are called fixed losses Pf ixed and will not be accounted for in this thesis. The criticalfrequency where the frequency dependent and frequency independent losses are equal isthe practical upper limit for the switching frequency [10]. The critical frequency can beexpressed as

fcrit =Pcond +Pf ixed

Wsw. (2.8)

Despite having the same sources of losses, the effect of the conduction loss mechanisms differfrom one topology to another. The derivation of the expressions for losses can be found in[6].

In [25] it is stated that the diode forward voltage places a hard limit on the achievableefficiency, this can be improved upon by employing synchronous rectification, replacingthe diodes that are conventionally used to implement some of the converter’s switches witha CMOS transistor that is controlled to have unidirectional current flow like the diode itreplaces. Since the on-resistance Ron of a transistor can be lowered by having a larger devicethe conduction losses in the transistor can be made to be very low, this does not apply to thediode resistance RD [10]. When using active rectification, care must be taken to detect thecurrent flowing through the transistor to ensure that this current is kept unidirectional, thisadds extra complexity compared to using a diode.

A trade-off can be made between conduction losses and switching losses by using soft-switching methods. For diodes, zero current switching lowers reverse-recovery losses whilefor MOSFETs, zero voltage switching lowers losses due to energy stored in the outputcapacitance CDS. Multiple methods exist to implement soft-switching [10].

The input resistance of the converter as seen by the DSSC is important when aiming foroptimal power transfer. Maximum power transfer is achieved when the input resistance of theconverter matches the output resistance of the DSSC. To achieve MPPT the input resistanceof the converter must be controllable either by the duty cycle or the switching frequency.

The ability of DC-DC converter topologies to sweep the entire I-V plane is importantwhen tracking the MPP. This means that the converter can present any resistance required bythe DSSC for maximum power transfer. Buck converters cannot track the MPP when voltageis low and current is high. Boost converters have the opposite limitation of not reachingoperating points with high voltage and low current. However, the Buck-Boost, Cuk andSEPIC can sweep the entire I-V plane and are not limited in the same fashion as the Buck


and the Boost converters. The inclination angle of the effective resistance presented by theconverter can be expressed as

θRe(D,RL) = tan−1(

1Rin

)(2.9)

In the following sections the basic DC-DC converter topologies are introduced, and theircharacteristics presented.

Buck converter

The Buck converter is a step-down converter, it has a discontinuous input current due to theswitch at the input. The Buck is a non-inverting converter. Its circuit diagram, adopted from[10, Fig. 6.14] can be seen in Figure 2.3a.

S

D

L

C

II

+

−

VI

IO

+

−

VO

(A) Circuit diagram0.0 0.2 0.4 0.6 0.8 1.0

D

0.0

0.2

0.4

0.6

0.8

1.0

MVDC

(B) Voltage conversion ratio vs. duty cycle

FIGURE 2.3: The Buck converter

The voltage conversion ratio, MV DC, of a Buck converter is derived in [6] and is shown tobe

MV DC = D, (2.10)

where D is the duty cycle of the active switch S in Figure 2.3a. The duty cycle is the partof the period of the signal applied to S which leads to S being closed and so D is limited tovalues between 0 and 1. The conversion ratio is plotted in Figure 2.3b and shows how MV DC

is limited to values between 0 and 1 since it is directly proportional to D.The voltage conversion ratio of the Buck converter when operated in DCM is

MV DC,DCM =D

D+D1=

21+√

1+ 4Re/RL. (2.11)

Where D1 is the period without current running through the inductor and Re =2L

d2Tswith d

as the transistor duty cycle, which might differ from the system duty cycle D. Ts =1fs

isthe PWM signal period. The transistor duty cycle might differ from the system duty cycleD, for example, when synchronous rectification is implemented. Then a dead time must begenerated to ensure that the two switches are not closed at the same time, resulting in a breakbefore make mechanism. In this case D 6= d since the reduced duty cycle is not present in D.

The conduction losses in the transistor used for implementing the switch arise from itson resistance as follows

PrDS = rDSDRL

PO. (2.12)

Where rDS is the resistance from the drain to source.


Losses in the diode arise from its forward resistance and forward voltage.

PD = (1−D)

(VF

VO+

RF

RL

)PO. (2.13)

The output capacitance of the converter has losses, modelled as the ESR rC. The powerdissipated in this resistance is

PrC = rCRL(1−D)2

12 f 2s L2 PO. (2.14)

Since the inductor is essentially a long wire, it has a series resistance called rL. The powerdissipation caused by rL is

PrL = rL1

RLPO. (2.15)

The total conduction losses are the sum of the losses due to the transistor on-resistance,the diode forward voltage and forward resistance, the capacitor ESR and the inductor seriesresistance. The derivation of the expressions for losses can be found in [6].

For a Buck converter operating in CCM, the input resistance is

Rin =RL

D2 . (2.16)

Using Equation (2.9) the load angle is found as θRe(D,RL) = tan−1(

D2

RL

), with limits 0° <

θRe(D,RL)< tan−1(

1RL

). These limits of the load inclination angle are shown in Figure 2.4,

adapted from [26, Fig 5]. In this adaptation it has been assumed that tan−1(

1RL

)= 45° to

clearly illustrate the difference between topologies. The figure shows that the Buck converteris unable to sweep the entire I-V plane [26].

Voltage

Current

FIGURE 2.4: The limits of load angles for the Buck converter indicating itsability to sweep the I-V plane, assuming tan−1

(1

RL

)= 45°

Boost converter

The Boost converter shown in Figure 2.5a is a non-inverting step-up converter. The Boostconverter has the voltage conversion ratio

MV DC =1

1−D(2.17)

The Boost converter’s voltage conversion ratio is limited to values over 1 and has anasymptote at D = 1. The voltage conversion ratio is plotted in Figure 2.5b.


L

S

D

C

II

+

−

VI

IO

+

−

VO

(A) Circuit diagram0.0 0.2 0.4 0.6 0.8

D

5

10

15

20

MVDC


FIGURE 2.5: The Boost converter

The voltage conversion ratio of the Boost converter when operated in DCM is

MV DC,DCM = 1+DD1

=1+√

1+ 4RL/Re

2. (2.18)

Where Re =2L

d2Ts. According to the model presented in [25] the efficiency of a Boost converter

operating in DCM is always higher than that of one in CCM.For the Boost converter, the losses are due to: transistor on-resistance

PrDS =DrDS

(1−D)2RLPO, (2.19)

diode forward voltagePrF =

rF

(1−D)RLPO, (2.20)

diode forward resistancePvF =

vF

VOPO, (2.21)

capacitor ESR

PrC =DrC

(1−D)RLPO (2.22)

and inductor series resistancePrL =

rL

(1−D)2RLPO. (2.23)

The derivation of the expressions for losses can be found in [6].For a Boost converter operating in CCM the input resistance is

Rin =1

(1−D)2RL. (2.24)

Using Equation (2.9) the load angle is found as θRe(D,RL) = tan−1(

1(1−D)2RL

), with values

tan−1(

1RL

)< θRe(D,RL) < 90°. These limits of the load inclination angle are shown in

Figure 2.6, adapted from [26, Fig 6]. In this adaptation it has been assumed that tan−1(

1RL

)=

45° to clearly illustrate the difference between topologies. The figure clearly illustrates thatthe Boost converter is unable to sweep the entire I-V plane [26].


Voltage

Current

FIGURE 2.6: The limits of load angles for the Boost converter indicating itsability to sweep the I-V plane, assuming tan−1

(1

RL

)= 45°

Previous work with Boost converters for interfacing with a single solar cell has been done[27, 28].

Buck-Boost converter

The Buck-Boost is an inverting converter capable of both step-up and step-down. It canbe derived by cascading the buck and boost topologies and then simplifying the resultingcircuit [21]. The buck-boost inherits the discontinuous input current of the buck and thediscontinuous output current of the boost.

MV DC = − D1−D

(2.25)

The negative sign of the voltage conversion ratio of the Buck-Boost converter indicatesits inverting characteristic, like the Boost converter it has an asymptote at D = 1 but its valueis limited to absolute values higher than 0.

S

L

D

C

II

+

−

VI

IO

+

−

VO

(A) Circuit diagram

0.0 0.2 0.4 0.6 0.8D

−15

−10

−5

0

MVDC


FIGURE 2.7: The Buck-Boost converter

According to [10] the conversion ratio of the Buck-Boost converter when operated inDCM is

MV DC,DCM = −√

RL

Re(2.26)

Where Re =2L

d2Ts. However, in [6] the same conversion ratio is derived as

MV DC,DCM =DD1

. (2.27)


For the Buck-Boost converter losses are due to: transistor on-resistance

PrDS =DrDS

(1−D)2RLPO, (2.28)

diode forward voltagePrF =

rF

(1−D)RLPO, (2.29)

diode forward resistancePvF =

vF

VOPO, (2.30)

capacitor ESR

PrC =DrC

(1−D)RLPO (2.31)

and inductor series resistancePrL =

rL

(1−D)2RLPO. (2.32)

The derivation of the expressions for losses can be found in [6].

Cuk converter

The Cuk converter was invented with the goal to have a converter capable of both step-up andstep-down while having a continuous input current [21]. The Cuk, as it can be seen in Figure2.8a, has double the amount of energy storing components compared to the Buck, Boost andBuck-Boost. It is an inverting converter as can be seen in Figure 2.8b and Equation (2.33).

MV DC = − D1−D

(2.33)

The voltage conversion ratio is the same as for the Buck-Boost converter.

L1

S

C1

D

L2

C2

II

+

−

VI

IO

+

−

VO


D

−15

−10

−5

0

MVDC


FIGURE 2.8: The Cuk converter

The voltage conversion ratio of a Cuk converter when operated in DCM is

MV DC,DCM = −√

RL

Re. (2.34)

Where Re =2(L1||L2)

d2Ts[10].

According to [29] the Cuk depends heavily on C1 since all current flowing through itmust pass through that capacitor.


Single-Ended Primary-Inductor Converter

The SEPIC is a non-inverting step-up/down DC-DC converter. As can be seen in Figure 2.9a,which was adapted from [6, Figure 1.17], the SEPIC has two inductors and two capacitors.According to [29], C1 inherently provides output short circuit protection in the SEPIC. Thevoltage conversion ratio of the SEPIC is

MV DC =D

1−D, (2.35)

this is plotted in Figure 2.9b where it can be seen that the SEPIC has the same voltageconversion ratio as the Buck-Boost and Cuk, only negated.

L1

S

C1

L2

D

C2

II

+

−

VI

IO

+

−

VO


D

0

5

10

15

MVDC


FIGURE 2.9: The Single-Ended Primary-Inductor converter

The voltage conversion ratio of the SEPIC when operated in DCM is

MV DC,DCM =

√RL

Re. (2.36)

Where Re =2(L1||L2)

d2Ts[10].

For the Buck-Boost converter, the Cuk converter and the SEPIC operating in CCM theinput resistance is

Rin =

(1−D

D

)2

RL. (2.37)

Using Equation (2.9) the load angle of the Buck-Boost, Cuk and SEPIC is found to beθRe(D,RL) = tan−1

(D2

(1−D)2RL

), with limits 0° < θRe(D,RL) < 90°. These limits of the load

inclination angle are shown in Figure 2.10, adapted from [26, Fig 7]. In this adaptation it hasbeen assumed that tan−1

(1

RL

)= 45° to clearly illustrate the difference between topologies.

The figure clearly illustrates that the Buck-Boost, Cuk and SEPIC are able to sweep the entireI-V plane [26].


Voltage

Current

FIGURE 2.10: The limits of load angles for the Buck-Boost, Cuk and SEPICindicating their ability to sweep the I-V plane, assuming tan−1

(1

RL

)= 45°

2.2.3 Control Strategies

A converter might experience changes in input, load and environment that may change itsperformance. By applying a control strategy, the converter can maintain, or at least stay closeto, the intended characteristics despite these changes [6]. Control strategies can also act asa countermeasure to component tolerances that lead to component values straying from thedesigned value. When developing control strategies, systems are commonly described witha transfer function (TF). The stability of the system can be evaluated by calculating its phasemargin which is found by inspecting the phase of the closed loop TF when the gain of the TFis unity and adding to that phase measurement 180°. A negative phase margin indicates anunstable system [10]. Two control approaches will be discussed in this thesis: Voltage ModeControl and Current Programmed Mode [10]. The Voltage Mode control, as it can be seen inFigure 2.11 (adapted from [10, Fig 9.4]), consists of sensing the output voltage and adjustingthe duty cycle to correct for any deviation from the desired output voltage. Gvg is the input-output TF, Gvd is the control-output TF, Zout is the output impedance of the converter, Gc isthe compensator TF, VM is the modulation voltage of a PWM signal generator and H is thecontrol sensor gain, which is used to adjust the value of vO to a range that can be comparedto vre f (which is usually a low voltage). vg is the input voltage and iload is the load current.

+ Gc(s) 1VM

H(s)

-Gvd(s)

Gvg(s)

+

Zout(s)

-vre f (s) vO(s)

vg(s)

iload(s)

FIGURE 2.11: Voltage Mode control block diagram

In Current Programmed Mode, the active switch of a converter (e.g. the switch S inFigure 2.5a) is controlled in such a way that its peak current follows the reference current ic.


This leads to inherent current limiting [10]. A block diagram of Current Programmed Modecontrol is shown in Figure 2.12.

+-

+-

-Fm

Fv

Fg

Gid(s)

Gvd(s)

Gvg(s)

Gig(s)

+

+

ic

vg

vO

iL

FIGURE 2.12: Current Programmed Mode block diagram

Figure 2.12 is adapted from [10, Fig 12.26]. Gid and Gig are the control and input currentTFs, respectively. iL is the inductor current that is controlled.

By utilising a certain control strategy, the DC-DC converter can also maximise thepower transfer by matching its input impedance with the source impedance. An exampleof this is Maximum Power Point Tracking (MPPT), a control method for solar cells whichincreases efficiency by tracking the MPP of the solar cell. Tracking is needed since the I-Vcharacteristics of solar cells are non-linear [9].

Maximum Power Point Tracking

DSSCs, like other solar cells exhibit a non-linear I-V characteristic. To extract as muchpower as possible from the cell, its MPP must be tracked. According to the maximum powertransfer theorem, the maximum power transfer occurs when the source resistance and theload resistance match. For ideal DC-DC converters, the static input resistance is

Rin(DC) =ηRL

M2V DC

(2.38)

where RL is the load resistance and MV DC is the voltage conversion ratio of the converter [6].For the in-resistance of the converter to be matched with the source resistance of the DSSC,the converter’s voltage conversion ratio must be adjusted.

There numerous strategies for achieving MPPT available in the literature. Thesestrategies include algorithms such as the Perturb and observe algorithm as well as methodsbased on fuzzy logic and machine learning [30].

2.2.4 Evaluation of solutions

To evaluate different approaches, performance metrics have been defined a Figure-of-Merit(FoM) is often used. For DC-DC converters, the performance is defined by their ability to


convert a DC voltage into another despite various disturbances. Furthermore, the efficiencyof DC-DC converters is an important metric and is used for evaluation. For comparison oftopologies, component stress and switch utilisation are useful metrics which can be usedto evaluate the cost of implementing a specific topology [10]. In thermal, line and loadregulation are defined.

Thermal regulation, T HR, defines the output voltage deviation from its nominal valuedue to a change in power dissipation PD. T HR is defined as [6, Section 1.5]

T HR =∆VO

VOnom×100%

∆PD

∣∣∣∣IO=Const and VI=Const

[%W

]. (2.39)

To quantify the effect of a change in the input voltage on the output voltage line regulation,LNR is defined as [6, Section 1.5]

LNR =

(∆VO

∆VI

)∣∣∣∣IO=Const and TA=Const

[mVV

]. (2.40)

Load regulation, LOR, describes how well the converter maintains a defined output voltagewhen the load is changed. LOR is defined as [6, Section 1.5]

LOR =VOmax−VOmin

IOmax− IOmin

∣∣∣∣VI=Const and TA=Const

[mVA

]. (2.41)

The last two FOMs can be combined into line/load regulation as follows [6, Section 1.5]

LLR =∆VO

VOnom×100%

∆IO

∣∣∣∣VI=Const and TA=Const

[%A

]. (2.42)

A topology can be compared numerically to other topologies according to thesecharacteristics.

2.3 Lithium-Based Batteries

Lithium-based batteries have become notorious for their tendency to burn or explode. Safecharging of these batteries is important among other methods for battery safety [31]. For safecharging of Li-based batteries, methods to control the charge rate are used, which includeconstant-current, constant-voltage and a combination of the two [11]. Using these controlmethods, the Li-based batteries are charged at voltages ranging from 3.8V to 4.2V [32, 33].

21

Chapter 3

Design Methodology

In this chapter the methodology for design will be described. The design specifications willbe presented and a market research of commercially available solutions is presented.

3.1 The Engineering Design Process

To identify the converter topologies that meet the specifications and to test the hypothesispresented at the beginning of this thesis the Engineering Design Process [10] is used.

1. "Specifications and other design goals are defined." [10]

For the design of a DC-DC converter, the most important specifications are those ofthe input and output characteristics. The efficiency of the converter is also importantsince the goal of this project is to design a converter with high efficiency.

2. "A circuit is proposed. This is a creative process that draws on the physical insight andexperience of the engineer." [10]

This step is challenging for an engineer with limited experience of designing DC-DCconverters since there are many options and without experience it can be hard to predictthe effects of each choice. To compensate for this lack of experience, the theoriespresented in Chapter 2 were used to identify the differences between the availabletopologies of DC-DC converters.

3. "The circuit is modeled. The converter power stage is modeled" [10]. "Componentsand other portions of the system are modeled as appropriate, often with vendor-supplied data." [10]

The models for components account for the losses caused by non-ideal components. Inthis work the series resistance of inductors, equivalent series resistance of capacitorsand on-resistance of transistors have been modelled to account for non-idealities ofcomponents Other non-idealities are not included. Average circuit models of PWMconverters focus on low frequency variations and ignore switching ripple.

4. "Design-oriented analysis of the circuit is performed. This involves development ofequations that allow element values to be chosen such that specifications and designgoals are met. In addition, it may be necessary for the engineer to gain additionalunderstanding and physical insight into the circuit behavior, so that the design can beimproved by adding elements to the circuit or by changing circuit connections." [10]

The equations needed to calculate component values have been derived in variousbooks and articles and these equations are applied rather than derived in this thesis.

5. "Model verification. Predictions of the model are compared to a laboratory prototype,under nominal operating conditions. The model is refined as necessary, so that themodel predictions agree with laboratory measurements." [10]

Chapter 3. Design Methodology 22

Since laboratory measurements will not be done at this stage, the model verificationrevolves around verifying the expected behaviour of the models using simulations inLTspice.

6. "Worst-case analysis (or other reliability and production yield analysis) of the circuitis performed. This involves quantitative evaluation of the model performance, to judgewhether specifications are met under all conditions. Computer simulation is well-suited to this task." [10]

For this step LTspice simulation is used and component values varied to reflect likelycomponent tolerances.

7. "Iteration. The above steps are repeated to improve the design until the worst-case behavior meets specifications, or until the reliability and production yield areacceptably high." [10]

The evaluation of the design is documented in this step and a discussion on furtherimprovement takes place.

The work described in this thesis follows the steps in the engineering design process. Inthe next section specifications for the design will be defined to complete the first step.

3.2 Design Specifications For a DC-DC Converter InterfacedWith a DSSC and Li-Based Battery

The first step of the Engineering Design Process is defining the specifications and designgoals. For the considered design, the specifications can be extracted from the characteristicsof the DSSC source and the battery load. As previously mentioned, the output voltage of theDSSC is around 400mV. To be able to design a converter a range of likely values is neededto calculate component values for the converter. By measuring the open-circuit voltage ofthe DSSC, the maximum output voltage of the cell can be determined. However, at opencircuit conditions no power will be transferred from the cell. To acquire a useful range ofvoltages, the voltage at the MPP can be inspected. On average, this voltage is 400mV butvaries under different lighting conditions and between cell configurations. The input voltagerange is assumed to be 300mV≤VI ≤ 500mV. This range corresponds roughly to the limitsof measured open-circuit voltage and the voltage at the maximum power point for a subsetof Exeger’s DSSCs in various lighting conditions. This range also indicates that the start-up voltage, the voltage at which point the converter begins operating, must be below theminimum input voltage. Hence, Vstart ≤ 300mV.

The output voltage of around 4.0V mentioned earlier is also an approximation of theactual voltages needed for charging Li-based batteries. Li-based batteries are charged atvoltages ranging from 3.8V to 4.2V [32, 33]. The output voltage range is assumed to be3.8V≤VO ≤ 4.2V.

The voltage must be regulated. The maximum allowable ripple in the output voltage isassumed to be vr,max = 0.1VO. A control system is needed to ensure that the converter canreact to changes in environment, source and load as well as to compensate for componenttolerances. A good figure of merit for stability of the control system is the phase-margin.The converter is designed so that its closed-loop control-to-output transfer function has aphase-margin of φm = 50°, which should be sufficient to guarantee stability despite deviationfrom ideal values of components due to their tolerances.

Through inspection of the measurements of the maximum output power of Exeger’sDSSCs, the possible values for the input power of the converter are assumed to be 4.2mW≤PI ≤ 360mW.


From the measurements of short-circuit current and the current at the MPP the expectedinput current can be estimated to be in the range 8.4mA ≤ II ≤ 350mA. The limits of theoutput current can be estimated by assuming 100% efficiency.

IO,max =max(PI)

min(VO)(3.1)

and

IO,min =min(PI)

max(VO). (3.2)

Where max(PI) and min(PI) are the maximum and minimum values of the input powerrespectively, max(VO) is the maximum output voltage and min(VO) is the minimum outputvoltage. This gives the output current range of 1.0mA≤ IO ≤ 94.7mA.

Exeger’s objective is to charge batteries as fast as their cells can possibly manage. Thismeans that the maximum power point of the DSSC must be tracked accurately and that thelosses between the cell and the battery should be low. From the specifications supplied forthe input power and input voltage, the range of the source resistance seen by the convertercan be calculated as Rs =

V 2I

PI, resulting in a range of 250mΩ≤ Rs ≤ 59.5Ω.

A goal of achieving high efficiency for the DC-DC converter has been set. The minimumefficiency is assumed to be 80%. Efficiency reports are often based on peak efficiency, this isnot appropriate in this work since the goal is to keep efficiency high in all expected operatingconditions so in this work the efficiency reported is the minimum efficiency that occurs withinthe expected operating range.

These specifications are summarised in Table 3.1.

TABLE 3.1: Design Specifications for a DC-DC Converter Interfaced Witha DSSC and Li-Based Battery

Variable SpecificationVI,min 300mVVI,max 500mVVO,min 3.8VVO,max 4.2VPI,min 4.2mWPI,max 360mWIO,min 1mAIO,max 94.7mAVstart,max 300mVVr,max 0.1VOφm 50°ηmin 0.8

In addition to the limits of the ranges described above, the middle of the range, found bytaking the average of the limits, are given here.

VI,avg =VI,max +VI,min

2=

500mV+ 300mV2

= 400mV,

VO,avg =VO,max +VO,min

2=

4.2V+ 3.8V2

= 4V,

PI,avg =PI,max +PI,min

2=

360mW+ 4.2mW2

= 182mW


andIO,avg =

IO,max + IO,min

2=

95mA+ 1mA2

= 48mA.

The load resistance range is calculated from the specification for the output voltage andcurrent ranges and is

RL,max =VO,max

IO,min=

4.2V1mA

= 4.2kΩ

andRL,min =

VO,min

IO,max=

3.8V95mA

= 40Ω

with average

RL,avg =VO,avg

IO,avg=

4V48mA

= 83.3Ω.

The output power is also calculated from the specification for the output voltage andcurrent ranges:

PO,max = VO,maxIO,max = 4.2V×95mA = 399mW,

PO,min = VO,minIO,min = 3.8V×1mA = 3.8mW

with average ofPO,avg = VO,avgIO,avg = 4V×48mA = 192mW.

The PWM signal frequency, MOSFET device characteristics, capacitor equivalent seriesresistance (ESR) and the inductor series resistance are design parameters for which valuesmust be assumed since these are needed to calculate component values and their losses. PWMsignal frequency is assumed to be fs = 300kHz. Device characteristics for the MOSFETswitches are assumed to be rDS = 10mΩ and CDS = 10pF. The ESR of capacitors is assumedto be rC = 100mΩ and the series resistance of inductors, rL = 40mΩ.

The required voltage conversion ratio is inpedendent of the chosen topology and iscalculated from the specifications as follows.

MV DC,min =VO,min

VI,max=

3.8V500mV

= 7.600,

MV DC,max =VO,max

VI,min=

4.2V300mV

= 14.000

and on average

MV DC,avg =VO,avg

VI,avg=

4V400mV

= 10.000.

3.3 Evaluation of Commercially Available Solutions

A market research is conducted and the available solutions that were deemed likely to meetthe specifications are evaluated in this section. Even though some of the evaluated solutionsdo not meet the specifications, their implementations may be a good source of inspirationfor a customised design. The most promising solutions from several manufacturers areevaluated in the market research. The solutions that were closest to fulfilling the applicationspecifications have been selected for closer analysis. The evaluation is done based on thespecifications given in Section 3.2.


3.3.1 Linear Technology - LTC3105

The LTC3105 is a synchronous boost converter, specifically designed to be efficient in lowpower applications. The LTC3105 datasheet reports that the chip has a typical start-upvoltage of 250mV (max 400mV) and an input voltage range 225mV ≤ VI ≤ 5V. Thedevice includes an auxiliary LDO regulator intended for powering sensitive devices suchas microcontrollers and sensors. Additionally it offers MPPT, inrush current limiting, anti-ringing control and automatic power adjustment. A Burst Mode optimizes the converterefficiency overall operating conditions by adjusting peak current. The device is intended forsolar powered battery and energy harvesting applications [34]. The characteristics in Table3.2 were extracted from the datasheet.

TABLE 3.2: Evaluation of LTC3105 with respect to specifications

Variable Specification LTC3105VI,min 300mV 225mVVI,max 0.5V 5VVO,min 3.8V 1.6VVO,max 4.2V 5.25VIO,min 1mA 0µAIO,max 95mA 500mAVstart,max 300mV 250mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.7

Efficiency is evaluated from the datasheet at VO = 3.3V, VI = 0.6V and VO = 5V, VI =1.5V. In Table 3.2 the characteristics that met the specifications are highlighted with a greencolour, those not met are highlighted with a red colour. It is clear from this summary that theLTC3105 does not meet all the specifications, most importantly the minimum efficiency is70%, 10% below the specification.

3.3.2 Linear Technology - LTC3108

According to the datasheet for the LTC3108, it can operate from voltages as low as 20mVand output a discrete set of voltages including 4.1V. The device features an energy harvestingpower management system as well as an auxiliary linear drop out (LDO) regulator intendedfor powering sensitive devices such as microcontrollers and sensors. The LTC3108 relieson step-up transformers and is intended for use with, among others, surplus heat energyharvesting applications and small solar cells. The characteristics in Table 3.3 were extractedfrom the datasheet [35].

TABLE 3.3: Evaluation of LTC3105 with respect to specifications

Variable Specification LTC3108VI,min 300mV 20mVVI,max 0.5V 0.5VVO,min 3.8V 2.3VVO,max 4.2V 5.1VIO,min 1mA 0mAIO,max 95mA 7mAVstart,max 300mV 20mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.2


Efficiency was evaluated from the datasheet with a 1:20 ratio transformer.The LTC3108 is rated for output currents up to 7mA, only 7.4% of the specified

maximum output current. It also has a minimum efficiency well below the specified 80%at only 20%.

3.3.3 Texas Instruments - TPS6120x

The TPS6120x is a synchronous Boost converter intended for solar cell or battery poweredproducts. It has a start-up voltage of 500mV an input voltage range of 0.3V ≤ VI ≤ 5.5Vand output voltage range of 1.8V≤VO ≤ 5.5V [36]. The device features output short circuitprotection and a Power Save mode to improve efficiency over a wide range of load currents.[36, Figure 27] shows an example of adding a MPPT circuit to the converter. Further detailsof this circuit can be found in [37].

TABLE 3.4: Evaluation of TPS6120x with respect to specifications

Variable Specification TPS6120xVI,min 300mV 300mVVI,max 0.5V 5.5VVO,min 3.8V 1.8VVO,max 4.2V 5.5VIO,min 1mA 100µAIO,max 95mA 600mAVstart,max 300mV 500mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.6

As it is shown in Table 3.4, the TPS6120x has a high start-up voltage, in fact it is equalto the maximum input voltage. This means that for the device to start transferring energy, theDSSC would have to operate at its maximum output voltage. The efficiency, evaluated from[36, Figure 8], is 60% which does not meet the specification.

3.3.4 Texas Instruments - BQ25505

The BQ25505 is a boost converter designed to power wireless sensor networks with energyharvesters such as solar cells. It has a start-up voltage of 330mV and has an input voltagerange down to 100mV. The device includes programmable MPPT and battery chargingcircuitry [38].

TABLE 3.5: Evaluation of BQ25505 with respect to specifications

Variable Specification BQ25505VI,min 300mV 100mVVI,max 0.5V 5.1VVO,min 3.8V 2VVO,max 4.2V 5.5VIO,min 1mA 0µAIO,max 95mA 285mAVstart,max 300mV 330mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.75


Table 3.5 shows that besides the start-up voltage and efficiency the BQ25505 meets thespecifications. The efficiency is only 5% below the specified 80% and the start-up voltage is30mV higher than the desired start-up voltage.

3.3.5 Cypress - MB39C831

The MB39C831 is a synchronous Boost converter intended for application with solar cells.According to the datasheet for MB39C831 the start-up voltage is 350mV and the inputvoltage range is 0.3V ≤ VI ≤ 4.75V and the output voltage range is 3.0V ≤ VO ≤ 5.0V[39]. The chip has built-in MPPT and can switch between Pulse-Frequency Mode (PFM)and PWM modes to improve efficiency at low output power. Moreover, the device includesvoltage and current protection for Li-based batteries.

TABLE 3.6: Evaluation of MB39C831 with respect to specifications

Variable Specification MB39C831VI,min 300mV 300mVVI,max 0.5V 4.75VVO,min 3.8V 3.0VVO,max 4.2V 5.0VIO,min 1mA 0µAIO,max 95mA 200mAVstart,max 300mV 350mVVr,max 0.1VO 0.005VOφm 50° N/Aηmin 0.8 0.55

Table 3.6 shows that except for the start-up voltage and efficiency, the MB39C831 meetsthe specifications. The efficiency is too low at 55% and the start-up voltage is 50mV higherthan the specified start-up voltage.

3.3.6 ST Microelectronics - SPV1050

The SPV1050 is capable of both Boost and Buck-Boost operation and the intendedapplications include charging batteries with energy harvested from solar cells. It hasprogrammable MPPT and battery charge circuitry [40]. The output voltage range is 2.6V≤VO ≤ 5.3V. Two LDOs are included that output 1.8V and 3.3V respectively.

TABLE 3.7: Evaluation of SPV1050 with respect to specifications

Variable Specification SPV1050VI,min 300mV 75mVVI,max 0.5V 18VVO,min 3.8V 2.6VVO,max 4.2V 5.3VIO,min 1mA 0µAIO,max 95mA 70mAVstart,max 300mV 550mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.75

As Table 3.7 shows, the SPV1050 has a high start-up voltage, in fact it is 50mV higherthan the maximum input voltage. This means that for the device to start transferring energy,


the DSSC would have to operate above its maximum output voltage. The efficiency is only5% from the specified minimum efficiency of 80%.

3.3.7 Analog Devices - ADP5091

According to the datasheet [41] for the ADP5091 it has a start-up voltage of 380mV, an inputvoltage range of 0.08V≤VI ≤ 3.3V, and an output voltage range of 2.2V≤VO ≤ 5.2V. Thechip features MPPT and hysteresis mode for higher efficiency at light loads.

TABLE 3.8: Evaluation of ADP5091 with respect to specifications

Variable Specification ADP5091VI,min 300mV 80mVVI,max 0.5V 3.3VVO,min 3.8V 2.2VVO,max 4.2V 5.2VIO,min 1mA 0µAIO,max 95mA 155mAVstart,max 300mV 380mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.7

Table 3.8 shows that except for the start-up voltage and efficiency the ADP5091 meetsthe specifications. The efficiency is too low at 70% and the start-up voltage is 80mV higherthan the specified start-up voltage.

3.3.8 Monolithic Power Systems - MP3418

The MP3418 has a start-up voltage of 0.8V, input voltage range of 0.6V ≤ VI ≤ 4V andoutput voltage range of 1.8V ≤ VO ≤ 4V. The device features an internal synchronousrectifier, high efficiency under light load and inrush current limiting [42] .

TABLE 3.9: Evaluation of MP3418 with respect to specifications

Variable Specification MP3418VI,min 300mV 600mVVI,max 0.5V 4.0VVO,min 3.8V 1.8VVO,max 4.2V 4VIO,min 1mA 0µAIO,max 95mA 350mAVstart,max 300mV 800mVVr,max 0.1VO N/Aφm 50° N/Aηmin 0.8 0.6

The MP3418’s characteristics, as shown in Table 3.9 do not meet the specifications forfour values, the minimum input voltage, the maximum output voltage, the start-up voltageand the minimum efficiency. The high value of the minimum input voltage makes thisconverter completely unusable for the application considered in this thesis as it is 100mVhigher than the maximum input voltage.


3.3.9 Comparison of Potential Commercial Solutions

Nine commercial solutions have been evaluated in this section, this evaluation is summarisedin Table 3.10. Out of these nine products, two stick out as the most promising. However,they do not meet the specifications. The most promising products are the LTC3105 and theBQ25505 since they are very close to meeting the specifications. The LTC3105 meets allspecifications except the minimum efficiency specification where it lacks 10%. Despite notmeeting the specified start-up voltage, the BQ25505 makes up for it with its efficiency whichis evaluated as 5% below the specified 80%.

TABLE 3.10: Evaluation of commercially available solutions with respect tothe design specifications

Variable Specification LTC3105 LTC3108 TPS6120x BQ25505 MB39C831 SPV1050 ADP5091 MP3418VI,min 300mV 225mV 20mV 300mV 100mV 300mV 75mV 80mV 600mVVI,max 0.5V 5V 0.5V 5.5V 5.1V 4.75V 18V 3.3V 4.0VVO,min 3.8V 1.6V 2.3V 1.8V 2V 3.0V 2.6V 2.2V 1.8VVO,max 4.2V 5.25V 5.1V 5.5V 5.5V 5.0V 5.3V 5.2V 4VIO,min 1mA 0µA 0mA 100µA 0µA 0µA 0µA 0µA 0µAIO,max 95mA 500mA 7mA 600mA 285mA 200mA 70mA 155mA 350mAVstart,max 300mV 250mV 20mV 500mV 330mV 350mV 550mV 380mV 800mVVr,max 0.1VO N/A N/A N/A N/A 0.005VO N/A N/A N/Aφm 50° N/A N/A N/A N/A N/A N/A N/A N/Aηmin 0.8 0.7 0.2 0.6 0.75 0.55 0.75 0.7 0.6

Since no commercial products evaluated in the market research met all specifications, areasonable decision is to design a customised DC-DC converter. In the following chapter, theEngineering Design Process will be used to design a DC-DC converter with the specificationsgiven in Section 3.2.

30

Chapter 4

Proposed Circuit Solutions

The specifications of the design are given in Section 3.2, completing the first step of theEngineering Design Process. As mentioned in Chapter 3, the second step of the EngineeringDesign Process is challenging for a designer with limited experience. This step involvesproposing a circuit based on the designer’s experience. The difference between differentconverter topologies was highlighted in Section 2.2 and is analysed further in this chapter tojustify the choice of topology.

The difference in the effect of conduction losses in the basic topologies can be seen inTable 4.1 where the expressions from Section 2.2.2 have been manipulated to depend on thevoltage conversion ratio. An exception is the expression for losses due to capacitor ESR forthe Buck converter, which depend on multiple other factors. This is because the capacitor isa part of an LC-filter at the output of the Buck converter, as can be seen in Figure 2.3a.

TABLE 4.1: Relative losses as a function of the voltage conversion ratio, M

Variable Buck Boost Buck-BoostPrDS

rDSI2O

M M2 +M M2 +MPrL

rLI2O

1 M2 (M+ 1)2

PrCrCI2

O

(1−M)2

12 f 2s L2I4

OP2

O M−1 MPrF

rF I2O

1−M M M+ 1PvF

vF IO1−M 1 1

The total relative losses of the basic topologies can be calculated by summing up theterms in Table 4.1. For the Buck converter this leads to : 3−M +

((1−M)2

12 f 2s L2I4

O

)P2

O. For the

Boost: 2M2 + 3M and for the Buck-Boost: 2M2 + 5M + 3. The expressions are alwayspositive since 0 ≤M ≤ 1 for the Buck converter, 1 ≤M for the Boost converter and 0 ≤Mfor the Buck-Boost converter as is discussed in Section 2.2.2.

As described in the problem statement in Chapter 1, the goal is to boost a low inputvoltage from the DSSC (approximately 400mV) to a voltage fit for charging Li-basedbatteries (around 4.0V). From this description, the Buck converter can be dismissedimmediately since its voltage conversion ratio, as it is given in Equation (2.10), is limitedto stepping down voltage. The remaining topologies that were presented in Section 2.2 arecapable of stepping up voltage, this is clear from Figures 2.5b, 2.7b, 2.8b and 2.9b.

As mentioned in Section 2.2, [24] proposes that interfacing a converter with a discontinuousinput current with a solar cell leads to less power transfer since the energy generated duringno conduction will be lost. Assuming, as in [24], that no energy is stored in the cell then thepart of the switching signal’s period where no current is drawn from the solar cell translatesdirectly to power losses and lower efficiency. This can be used to dismiss the Buck-Boostwhich has the same discontinuous input current characteristics as the Buck. The Boost

Chapter 4. Proposed Circuit Solutions 31

converter, Cuk, and SEPIC have a continuous input current. The Buck-Boost also has 2M+3higher relative conduction losses than the Boost.

While the Cuk has a continuous input current, its voltage conversion ratio as describedby Equation (2.35) is negative, resulting in inversion of the output voltage compared to theinput voltage. Inverting converters are not desirable for systems with rechargeable batteriessuch as the embedded consumer devices Exeger wants to integrate its DSSCs with. This isbecause the power delivered by the non-inverting converter can be used both for chargingand powering the device since the ground is shared, as opposed to an inverting converterthat would have to share its ground with the positive terminal of the battery and in turn theconsumer device [29].

The remaining two topologies are the SEPIC and the Boost converter. As can be seen bycomparing Figures 2.5a and 2.9a, the SEPIC has twice as many energy storing componentsas the Boost. The SEPIC is dismissed because of the increased conduction losses assumed toarise due to these added elements.

The Boost converter can step up voltage, has a continuous input current when operated inCCM and has few circuit elements, which leads to low losses and good reliability, in additionit is relatively easy to design.

4.1 Boost Converter in Continuous Conduction Mode

As outlined in Chapter 4 a design with the Boost converter topology will be designed. In thissection the implementation details and evaluation of the design is described.

To reach high efficiency, one of the methods mentioned in Section 2.2.2 is implemented.Synchronous rectification increases efficiency significantly since typical values for the diodeforward voltage drop VF are large compared to the specified VO. In addition, the on-resistanceof the transistor used to implement the active rectification can be made lower than what ispossible for a diode forward resistance RF since this resistance depends on the geometry ofthe transistor [10].

4.1.1 Circuit Model

The average switch model, described in detail in Section 2.2.1, is used to model the Boost.The model is based on three assumptions, the volt-second balance for inductors, the capacitorcharge balance and the small ripple approximation for the capacitor and inductor.

4.1.2 Design Oriented Analysis

Following the steps of the Engineering Design Process, the fourth step, the Design OrientedAnalysis, "involves development of equations that allow element values to be chosen suchthat specifications and design goals are met. In addition, it may be necessary for the engineerto gain additional understanding and physical insight into the circuit behavior, so that thedesign can be improved by adding elements to the circuit or by changing circuit connections."[10]

The specifications for the converter design are described in Section 3.2 and summarisedin Table 3.1. The design follows the example design of a Boost converter in CCM from [6,Section 3.2.10]. When the Boost converter is operated in CCM, the following equations areused to find appropriate component values with respect to the specifications.

D is the duty cycle of the PWM signal, it is calculated in the following way.

Davg = 1− ηmin

MV DC,avg= 1− 0.800

10.000= 0.920 (4.1)


VO and VI are chosen to be in the middle of their ranges as was described in Section 3.2, thisis done to best represent the range in a single value during the design process that follows.Maximum and minimum values for the duty cycle are

Dmin = 1− ηmin

MV DC,min= 1− 0.800

7.600= 0.895 (4.2)

andDmax = 1− ηmin

MV DC,max= 1− 0.800

14.000= 0.943. (4.3)

The minimum inductor value can be determined by

Lmin =RL,maxDmin(1−Dmin)2

2 fs=

4.2kΩ×0.895(1−0.895)2

2×300kHz= 69.4µH, (4.4)

The inductor value is chosen as the next standard inductor value above Lmin, L = 75µH. Thestandard inductor values are those commercially available.

The capacitor’s role is to suppress voltage ripple at the output, to determine its valuethe capacitor voltage ripple is calculated, assuming that the ripple voltage is divided equallybetween the capacitor and its ESR.

VCpp =12

Vr,max

VOVO,avg =

12×0.100×4V = 200mV (4.5)

Now the minimum capacitance required to suppress the voltage ripple is found as

Cmin =DmaxVO,max

fsRL,minVCpp=

0.943×4.2V300kHz×40Ω×200mV

= 1.65µF. (4.6)

Choosing the next standard capacitor value above Cmin leads to C = 2.2µF.To ensure that CCM operation is guaranteed, the boundary between CCM and DCM is

inspected. This is done through calculating the critical load resistance Rcrit which defines theboundary of the two operating modes. If the load resistance rises above this value then theconverter would operate in DCM.

Rcrit(D = 0.920) =2L

Davg(1−Davg)2 1fs

=2×75µH

0.920(1−0.920)2 1300kHz

= 7.64kΩ (4.7)

min0≤D≤1

(Rcrit) =272

L fs =272×75µH×300kHz = 304Ω (4.8)

The calculations in Equations (4.7) and (4.8) show that RL ≤ min0≤D≤1

(Rcrit), which means that

CCM operation is guaranteed for all loads smaller than 304Ω and since the maximum loadresistance is RL,max =

VO,maxIO,min

= 4.2V1mA = 4.2kΩ, CCM operation is guaranteed.

The calculated values are summarised in Table 4.2.

TABLE 4.2: Calculated values for Boost converter in CCM

Variable ValueL 75µHC 2.2µFDmin 0.895Dmax 0.943


Control Loop

A control loop is added to compensate for component tolerances and ensure stability duringchanges in either the source or load. The Voltage Mode control presented in Section 2.2.3is the chosen control method since it regulates voltage directly. A block diagram of VoltageMode control is shown in Figure 2.11.

The Boost converter has the following characteristics according to [10]. Using the valuesalready determined for D, VO, L, C, and RL the characteristics can be calculated.

Ggo =1

1−Davg=

11−0.920

= 12.500 (4.9)

Gdo =VO,avg

1−Davg=

4V1−0.920

= 50.000 (4.10)

ωo =1−Davg√

LC=

1−0.920√75µH×2.2µF

= 6.23krads

(4.11)

In Hertz this frequency is fo =ωo2π

=6.23k rad

s2π

= 991Hz.

Q = (1−Davg)RL,avg

√CL= (1−0.920)×83.3Ω×

√2.2µF75µH

= 1.142 (4.12)

ωz = (1−Davg)2 RL,avg

L= (1−0.920)2 83.3Ω

75µH= 7.11k

rads

(4.13)

ωz in Hertz is fz =ωz2π

=7.11k rad

s2π

= 11.2kHz.Two transfer functions are of interest for this system, these are the input-output (Gvg) and

the control-output (Gvd) transfer functions. Gvg is a second order transfer function with nozeroes.

Gvg(s) = Ggo1

1+ sQωo

+(

sωo

)2 (4.14)

Bode plots and the step response for Gvg are given in Figure 4.1.

102 103 104

−20

0

20

Magnitude

[dB]

102 103 104

Frequency [Hz]

−100

0

Phase

[deg]

(A) Bode plot

0.0000 0.0005 0.0010 0.0015 0.0020 0.0025Time [sec]

0.0

2.5

5.0

7.5

10.0

12.5

15.0

Amplitude[V]

(B) Step response

FIGURE 4.1: Boost converter input-output characteristics

Gvd is a second order transfer function with one zero.

Gvd(s) = Gdo

(1− s

ωz

)1+ s

Qωo+(

sωo

)2 (4.15)


Bode plots and the step response for Gvd are given in Figure 4.2.

101 102 103 104 105

0

20

40Magnitude

[dB]

101 102 103 104 105

Frequency [Hz]

−200

−100

0

Phase

[deg]

(A) Bode plot

0.0000 0.0005 0.0010 0.0015 0.0020 0.0025Time [sec]

0

20

40

60

Amplitude[V]

(B) Step response

FIGURE 4.2: Boost converter control-output characteristics

The loop gain of the system shown in Figure 2.11 is

T (s) = H(s)Gc(s)Gvd(s)/VM. (4.16)

Where H(s) is the sensor gain, Gc(s) is the compensator transfer function and VM is thevoltage level of the pulse width modulator.

Without compensation, assuming sensor gain is H(s) = 1 and modulation voltage isVM = 1V the loop gain is

T (s) = Gvd(s). (4.17)

The phase margin of the uncompensated system is φm = 180° + 6 Gvd( jωc) = 180° +−267° =−87.4°. Since converter with a phase margin of φm = 50° is desired, a compensatormust be designed to improve the phase margin. A lead compensator is useful to improvephase margin. Its transfer function is

Gc(s) = Gco

1+(

sωz

)1+

(s

ωp

) (4.18)

fz and fp are positioned in the following way to improve the phase margin by θ : fz =

fc

√1−sin(θ )1+sin(θ ) = 43.4kHz

√1−sin(−267°)1+sin(−267°) = 31.2kHz and fp = fc

√1+sin(θ )1−sin(θ ) = 43.4kHz

√1+sin(−267°)1−sin(−267°) =

60.6kHz. Where fc is the crossover frequency of T (s) at which point |T (s)| is 0dB.To avoid changing the crossover frequency of the loop gain transfer function, the

compensator gain is chosen to be 1 at fc. This can be done by fulfilling this requirement:

1 = Gco =

√fz

fp(4.19)

Choosing other values of Gco will move the crossover frequency. Gco is found to be Gco =√fzfp=√

31.2kHz60.6kHz = 717×10−3 and the compensator bode plot is shown in Figure 4.3 for the

compensator

Gc(s) = 0.3321+

(s

2π(31.2kHz)

)1+

(s

2π(60.6kHz)

) . (4.20)


104 105 106−2.5

0.0

2.5

Magnitude

[dB]

104 105 106

Frequency [Hz]

5

10

15Phase

[deg]

FIGURE 4.3: Bode plot for the compensator described in Equation (4.20)

After including the compensator then the loop gain becomes

T (s) = Gc(s)Gvd(s), (4.21)

assuming like before that the sensor gain is H(s) = 1 and the modulation voltage is VM = 1V.The compensated closed loop bode plot and step response are shown in Figure 4.4.

101 102 103 104 105

0

20

Magnitude

[dB]

101 102 103 104 105

Frequency [Hz]

−200

−100

0

Phase

[deg]

FIGURE 4.4: Compensated closed-loop transfer function of the Boostconverter

After compensation the phase margin is φm = −69.1° and so the lead compensator hasnot been able to stabilise the system. More advanced methods are needed for stabilisation.

Losses

To evaluate losses in the converter, some device characteristics must be assumed, sinceno technology has been chosen for the implementation. As mentioned in Section 3.2 thetransistor characteristics will be assumed to be rDS1 = rDS2 = 10mΩ and Cout1 = 10pF. Theoutput capacitor’s ESR and the inductor series resistance are assumed to be rC = 100mΩ andrL = 40mΩ respectively.

The energy lost due to switching is calculated with Equation (2.7) and results in Wsw =CDSV 2

O,avg = 10pF×4V2 = 160pJ. The losses due to switching are found by using Equation(2.6), Psw = fsWsw = 300kHz×160pJ = 48µW.

The conduction losses in the converter arise from non-ideal components. The componentsthat cause conduction losses are the transistors, the capacitor and the inductor. The


conduction losses can be determined by using Equations (2.19) through (2.23). Equation(2.19) predicts the conduction losses due to the active switch, these are found to be PrDS1 =

rDS

(IO,max

√Dmax

1−Dmax

)2= 10mΩ

(95mA

√0.943

1−0.943

)2= 26.1mW. The rectifying transistor also causes

conduction losses these losses are expressed in [6] as

PrDS2 =rDS

(1−Davg)RL,avgPO,max =

10mΩ

(1−0.920)83.3Ω399mW = 599µW. (4.22)

Losses due to the capacitor’s ESR are calculated using Equation (2.22) and found to be PrC =

rC

(IO,max

√Dmax

1−Dmax

)2= 100mΩ

(95mA

√0.943

1−0.943

)2= 14.9mW. The series resistance of

the inductor causes losses described by Equation (2.23) and are PrL = rL

(IO,max

1−Dmax

)2=

40mΩ( 95mA

1−0.943

)2= 111mW.

Total losses due to conduction and switching losses are PLS = PrL +Psw +PrDS +PrC =111mW+ 48µW+ 26.1mW+ 14.9mW = 152mW. This leads to the efficiency being η =0.725 or 72.5% which is 7.5% below the specified 80%.

4.1.3 Circuit validation

The validation of the Boost converter operating in CCM is presented here, the verificationconsists of simulating the circuit under nominal conditions in LTspice and checking that thespecifications are met. The simulation setup is shown in Figure 4.5 for a Boost convertercorresponding to Figure 2.5a, the component values are set to those derived in Section 4.1.2.The simulator directive .param rL 40m sets a 40mΩ series resistance for the inductor and.param rC 100m sets a 100mΩ equivalent series resistance for the capacitor. The inputvoltage is in the middle of the range specified in Section 3.2 and so is the load resistanceRL1. The duty cycle is varied between the extreme ends of its range as it was calculated inSection 4.1.2, this is done by using a DC sweep with the .dc simulation command. TheLTspice library average.lib is included to enable the use of the average switch model CCM2,this model includes on-resistance conduction losses specified by the Ron parameter, whichis set to 10mΩ. The average.lib library was developed by the authors of [10] and madeavailable through an online course given by them.

L1 75µH2.2µF

C1

V1

PWL(0 0.868 10ms 0.929)

400mV

V2RL1

84.2ohm

Ron=10mVD=0 RD=0

CCM2

outin

d

.lib average.lib

.dc V1 0.895 0.943 0.01

.param rL 40m.param rC 100m

--- C:\Users\sturla.lange\Desktop\2018-05-25\LTSpice models\boost_CCM_efficiency_curves_parasitics.asc ---

FIGURE 4.5: Simulation setup for model verification of static characteristicsin LTspice

The results from the simulation are shown in Figure 4.6. In Figure 4.6a the efficiency isshown to stay above the specified minimum of 80% for the complete duty-cycle range since


η = 0.847 at its lowest point. In Figure 4.6b, the converter is shown to be able to span theentire specified output voltage range within the duty-cycle range.

0.90 0.91 0.92 0.93 0.94D

86

88

90

92

94

η[%

]

(A) Efficiency decreasing as D increases

0.90 0.91 0.92 0.93 0.94D

3.5

4.0

4.5

5.0

5.5

6.0

Vout[V]

(B) Output voltage with respect to D

FIGURE 4.6: Model verification of static characteristics for the Boost inCCM

In Figure 4.7 the simulation setup for the verification of the dynamic characteristics canbe seen. The difference to that seen in Figure 4.5 is with respect to the losses which are notincluded in this simulation. The simulation command is .ac which is a AC sweep from 1Hzto 1MHz with 300 points per decade. The AC sweep acts on the voltage source Vduty whichis an AC source with amplitude 1. For the DC operating point solution required to start theAC sweep Vduty is set to 0.9V.

L1 75µH2.2µF

C1

400mV

V2RL1

84.2ohm

CCM1

0.9AC 1

Vduty

outin

d

sw

.lib average.lib

.ac dec 300 1 1Meg

--- C:\Users\sturla.lange\Desktop\2018-05-25\LTSpice models\boost_CCM_model_verification_OL.asc ---

FIGURE 4.7: Simulation setup for model verification of dynamiccharacteristics in LTspice

The simulation results are shown in Figure 4.8. By comparing this figure to Figure 4.2ait is verified that the dynamic modelling used in Section 4.1.2 was appropriate and the phasemargin is roughly the same. It is measured as −85.6°, compared to the calculated value of−87.4°.


100 101 102 103 104 105 106

Frequency [Hz]

−20

0

20

40

Magnitude

[dB]

(A) Magnitude

100 101 102 103 104 105 106

Frequency [Hz]

−250

−200

−150

−100

−50

0

Phase

[deg]

(B) Phase

FIGURE 4.8: Model verification of dynamic characteristics for the Boost inCCM

4.1.4 Worst-Case Analysis

Component tolerances must be considered to achieve a robust design. Components availablefrom manufacturers have a tolerance range within which the component value will be. Precisecomponents can be acquired but with increased cost. Since the design is not stable even whentolerances are not taken into account this step is not performed at this point.

4.1.5 Evaluation

In order to evaluate the choice of sampling frequency, the critical frequency can becalculated as described by Equation (2.8): fcrit =

PcondWsw

= 942MHz. The critical frequencyis significantly higher than the chosen switching frequency of fs = 300kHz. In general,increasing the frequency leads to a lower value for the energy storing elements in a converter,which means smaller inductors and capacitors. The trade-off comes from the switchinglosses which increase with frequency. Assuming that the sampling frequency is set to equalthe critical frequency, the switching losses become Psw2 = fcritWsw = 151mW, significantlyhigher than the losses of 48µW at fs = 300kHz. The efficiency becomes 56.9%, which showsa significant drop in efficiency. Since the margin for efficiency is none or low depending onwhether the values from simulations or calculations are used, the sampling frequency willnot be altered.

The design meets all specifications except for the phase margin. However, other designgoals have not been checked. One of the design goals is that the design can do MPPT. For thisto be possible, the converter must be able to adjust its input resistance. The input resistancefor a Boost converter is given in Equation (2.24). Another design goal is that the outputvoltage is regulated to be within 10% of the desired VO. In Section 2.2.3 it is described howthe output voltage is regulated with voltage mode control by varying the duty cycle. The inputresistance and the voltage regulation both depend on the duty cycle. In both expressions theduty cycle is the only parameter that can be controlled. Hence, it is not possible to achieveboth voltage regulation and MPPT at the same time with a Boost converter operating in CCM.To highlight the need for MPPT, a calculation of the power lost due to mismatch is presentedbelow assuming an extremely simplified model using the Thévenin equivalent for the DSSCat a single operating point.


−+ VI

Rs

Rin

FIGURE 4.9: Simplified model using the Thévenin equivalent for the DSSCat a single operating point

To achieve voltage regulation, Rin becomes Rin =ηRLM2 = 961mΩ, assuming RL = 84.2Ω.

The power delivered out of the DSSC, assuming that Rs = 2.29Ω, is

P =V 2

IR2

sRin

+ 2Rs +Rin

= 14.6mW

To achieve MPP, Rs = Rin = 2.29Ω:

M =

√ηRL

Rs= 5.68.

Power delivered out of the DSSC is

Pmppt =V 2

I

4Rs= 17.5mW

. The power lost by not tracking the MPP is:

PLS = Pmppt −P = 2.91mW

.By defining k as the matching coefficient of the source resistance Rs and the converter

input resistance Rin, k = RsRin

, the efficiency of MPPT can be evaluated with

ηMPPT =P

Pmppt=

4kk2 + 2k+ 1

. (4.23)

Figure 4.10 shows the variation of efficiency with k for efficiency levels above 80%.


0.5 1.0 1.5 2.0 2.5K

0.80

0.85

0.90

0.95

1.00

η

FIGURE 4.10: MPPT efficiency as a function of k

For the example above k = RsRin

= 2.29Ω

961mΩ= 2.38 and ηmppt =

4kk2+2k+1 = 0.834. Making

use of the efficiency levels from the circuit validation where η = 0.847, the efficiency whenlosses due to mismatch are considered is ηtot = η ×ηmppt . The total efficiency is 60.5%,which is below the specified 80%.

This example shows how important it is to be able to track the MPP. To solve the issueof not being able to regulate the output voltage and the input resistance separately there is aneed for a change of strategy.

4.2 Boost Converter in Discontinuous Conduction Mode

As discussed in Section 4.1.5 the Boost converter in CCM cannot control both the outputvoltage and the input resistance, to do that the converter must be operated in DCM. Byoperating the Boost in DCM, its input resistance depends on the duty cycle and switchingfrequency. This method has been used before, such as in [43]. The input current of a Boostconverter operating in DCM is given in [6, Eq. (3.128)] as

II =D2VO

2 fsL(MV DC−1). (4.24)

By assuming an ideal converter and substituting MV DC with 1+ DD1

and VO with (1+ DD1)VI

the input current is expressed by

II =D2(1+ D

D1)VI

2 fsL DD1

=VI(DD1 +D2)

2 fsL. (4.25)

It follows that the input resistance is

Rin =VI

II=

2 fsLD2 +DD1

. (4.26)

Another reason to choose to the boost in DCM is the simplicity of controlling it. Thisis because of its transfer function which is first order (see Section 4.2.2) as opposed tothe second order transfer function of the Boost in CCM, as discussed in Section 4.1.2. Inaddition, the right-hand plane zero is at high frequencies and has little effect on the slowlyvarying input signals that are to be expected [10].


4.2.1 Circuit Model

Like the previous design (see Section 4.1.1) this design will use the average switch model.However, the model must be adjusted for DCM operation. The details of how this is doneand why this is needed can be found in [10, Chapter 11]. The most important differencebetween the average switch model for CCM and DCM, as discussed in Section 2.2.1, is thesmall ripple approximation for the inductor, which cannot be made for DCM operation sincethe ripple in the inductor is large by definition.

4.2.2 Design Oriented Analysis

The equations used to calculate component values can be found in a design example for aBoost converter operating in DCM in [6, Section 3.3.8].

The duty-cycle at the boundary of CCM and DCM operation is calculated as DBmin =1− 1

MV DC,min= 1− 1

7.600 = 0.868 and DBmax = 1− 1MV DC,max

= 1− 114.000 = 0.929.

Assuming a PWM signal frequency of 300kHz the maximum inductance required tooperate in DCM is

L1max =RL,minDBmax(1−DBmax)2

2 fs=

40Ω×0.929(1−0.929)2

2×300kHz= 316nH,

L2max =RL,minDBmin(1−DBmin)2

2 fs=

40Ω×0.868(1−0.868)2

2×300kHz= 1µH,

Lmax = min(L1max,L2max) = min(316nH,1µH) = 316nH.

The dwell-duty cycle is defined in [6, Eq. (3.139)] as

Dw = 1−D−D1 = 1−DMV DC

MV DC−1(4.27)

Assuming that Dw = 0.100 the maximum inductance can be found with [6, Eq. (3.142)]

Lmax =RL,min(1−Dw)2(MV DC,max−1)

2 fsM3V DC,max

=40Ω(1−0.100)2(14.000−1)

2×300kHz×14.0003 = 256nH.

(4.28)L is chosen to be a standard inductance value lower than Lmax to have the converter operatein DCM, L = 240nH.

Next the capacitor value should be determined, the expression for the minimum capacitorvalue is given as

Cmin =DmaxVO

fsRL,minVCpp(4.29)

in [6, Eq. (3.184)]. To calculate Cmin the values for the maximum duty-cycle Dmax and thecapacitor ripple VCpp must be determined.

Assuming that the specified minimum efficiency is achieved, η = 0.8, the maximum andminimum duty-cycle values can be found. These are

Dmax =

√2 fsLMV DC,max(MV DC,max−1)

ηminRL,min

=

√2×300kHz×240nH×14.000(14.000−1)

0.800×40Ω= 0.905


and

Dmin =

√2 fsLMV DC,min(MV DC,min−1)

ηminRL,min

=

√2×300kHz×240nH×7.600(7.600−1)

0.800×40Ω= 0.475.

The maximum value of D determines the minimum value of D1

D1min =Dmax

MV DC,max−1=

0.90514.000−1

= 0.070.

The dwell-duty cycle can also be found from Dmax as Dw = 1−Dmax−D1min = 1−0.905−0.070 = 0.025. The maximum value of D1 can be found from Dmin in the same way as D1,min

was found from Dmax. Thus D1,max is DminMV DC,min−1 =

0.4757.600−1 = 0.072. Now the dwell-duty cycle

is Dw = 1−Dmin−D1max = 1−0.475−0.072 = 0.453.Having found Dmax, the next variable to be determined is VCpp, its expression is given in

[6, Eq. (3.183)] as VCpp = Vr −VrC where Vr is the maximum allowed output ripple andVrC is the peak-to-peak ripple across the capacitors ESR. Vr is 400mV according to thespecified 10% allowed ripple at the output. According to [6, Eq (3.182)] VrC is expressedas rcIDM,max and using [6, Eq (3.179)] IDM,max is found as DminVI,max

fsL= 0.475×500mV

300kHz×240nH = 3.3A.Now assuming rc = 100mΩ then VrC = rcIDM,max = 100mΩ×3.3A = 330mV and VCpp =400mV−330mV = 70.1mV.

Dmax and VCpp have been determined so the minimum capacitance is found to be

Cmin =DmaxVO,avg

fsRL,minVCpp=

0.905×4V300kHz×40Ω×70.1mV

= 4.31µF.

Now C is chosen to be a standard capacitance value higher than Cmin to ensure that the outputvoltage ripple is lower than the allowed ripple, resulting in C = 4.7µF.

The calculated values are summarised in Table 4.3.

TABLE 4.3: Calculated values for Boost converter in DCM

Variable ValueL 240nHC 4.7µFDmin 0.475Dmax 0.905

Control Loop

When the Boost converter is operated in DCM it has a first order transfer function for input-output and control-output [10]. The control-output transfer function is

Gvd = Gdo1

1+ sωp

(4.30)

The Boost converter has the following characteristics when operated in DCM according to[10]. Using the values already determined for MV DC, VO, D, C, and RL the characteristics canbe evaluated:

Ggo = MV DC,avg = 10.000 (4.31)


Gdo =2VO,avg

Davg

MV DC,avg−12MV DC,avg−1

=2×4V0.689

10.000−12×10.000−1

= 5.500 (4.32)

ωp =2MV DC,avg−1

(MV DC,avg−1)RL,avgC=

2×10.000−1(10.000−1)83.6Ω×4.7µF

= 5.38krads

(4.33)

ωp in Hertz is fp =ωp2π

=5.38k rad

s2π

= 856Hz. Assuming the same control mode as for thedesign in Section 4.1 the closed loop equals the control-output transfer function, T (s) =Gvd(s). The bode plot and step-response of the system are shown in Figure 4.11.

100 101 102 103 104−10

0

10

Magnitude

[dB]

100 101 102 103 104

Frequency [Hz]

−50

0

Phase

[deg]

(A) Bode plot

0.00000 0.00025 0.00050 0.00075 0.00100 0.00125Time [sec]

0

1

2

3

4

5

Amplitude[V]

(B) Step response

FIGURE 4.11: Input-output characteristics of the Boost converter in DCM

The system has a phase margin of φm = 101° which fulfils the specifications so nocompensation is needed.

Losses

The losses arise from conduction and switching. The energy lost due to switching is Wsw =CDSV 2

O,avg = 10pF×4V2 = 160pJ and the switching losses are

Psw = fsWsw = 300kHz×1.6×10−10 J = 48µW,

assuming CDS = 10pF. The losses due to conduction in the transistor on-resistance, rDS =10mΩ, are

PrDS =2rDS

3

√2(MV DC,max−1)3

fsLRL,minMV DC,maxPO,max

=2×10mΩ

3

√2(14.000−1)3

300kHz×240nH×40.1Ω×14.000398mW

= 27.7mW.

The inductor series resistance is rL = 40mΩ and causes losses that are

PrL =2rL

3

√2MV DC,max(MV DC,max−1)

fsLRL,minPO,max

=2×40mΩ

3

√2×14.000(14.000−1)

300kHz×240nH×40.1Ω398mW

= 70.1mW.


The losses in the rectifying switch are assumed to be small and are neglected. The total lossesare

PLS = PrL +PrDS +Psw = 70.1mW+ 27.7mW+ 48µW = 97.8mW.

It is noteworthy that the losses due to the inductor series resistance are dominating by far at71.7%. The efficiency is calculated as

η =1

1+ PLSPO,max

=1

1+ 97.8mW398mW

,

which is 80.3% and very close to the specified efficiency, any unconsidered losses may resultin the converter efficiency dropping below the specification.

MPPT

To evaluate whether maximum-power point tracking is feasible for this design, the inputresistance is calculated.

max(Rin) = 252Ω

min(Rin) = 147mΩ

According to the specifications the resistance at the maximum power point has the range

250mΩ≤ Rs ≤ 59.5Ω.

These results show that the converter can track the MPP for all operating points since therange of Rs is within the range of Rin. The sampling frequency required for these resistancevalues can be found by solving [6, Eq. (3.169)] for fs and is found to be

fmin =min(RL)(1−Dw)2(max(MV DC)−1)

2Lmax(MV DC)3 = 375kHz

and

fmax =max(RL)(1−Dw)2(min(MV DC)−1)

2Lmin(MV DC)3 = 125MHz.

If the converter can operate as intended for this range of fs values, then the MPPT can beachieved.

4.2.3 Circuit Validation

The verification of the Boost converter operating in DCM is presented here, the verificationconsists of simulating the model under nominal conditions in LTspice and checking that thespecifications are met. The simulation setup is shown in Figure 4.12 for a Boost convertercorresponding to Figure 2.5a, the component values are set to those derived in Section 4.2.2.The simulator directive .param rL 40m sets a 40mΩ series resistance for the inductor and.param rC 100m sets a 100mΩ equivalent series resistance for the capacitor. The inputvoltage is in the middle of the range specified in Section 3.2 and so is the load resistance RL1.The duty cycle is varied between the extreme ends of its range as it was calculated in Section4.2.2, this is done by using a DC sweep with the .dc simulation command. The LTspicelibrary average.lib is included to enable the use of the average switch model CCM-DCM1, thismodel allows for operation in DCM. To set the inductor value for the CCM-DCM1 componentand the inductor L1 the simulator directive .param L 240n is used which sets the inductorvalue to 240nH. The switching frequency is set to 300kHz with fs=300k. The average.lib


library was developed by the authors of [10] and made available through an online coursegiven by them.

L1 L4.7µF

C1

V1

0.7

400mV

V2RL1

84.2

L=L fs=300k

CCM-DCM1

outin

d

.lib average.lib

.dc V1 0.474 0.904 0.01

.param L 240n

.param rL 40m

.param rC 100m

--- C:\Users\sturla.lange\Documents\2018-05-25\LTSpice models\boost_CCM-DCM_efficiency_curves.asc ---

FIGURE 4.12: Simulation setup from LTspice

The results of the simulation are shown in Figure 4.13 where it can be seen that theefficiency meets the specifications and that the output voltage is higher than intended.

0.5 0.6 0.7 0.8 0.9D

82.5

85.0

87.5

90.0

92.5

η[%

]

(A) Efficiency decreasing as D increases

0.5 0.6 0.7 0.8 0.9D

5

6

7

Vout[V]

(B) Output voltage with respect to D

FIGURE 4.13: Model verification for Boost converter in DCM

In Figure 4.14 the simulation setup for the verification of the dynamic characteristics canbe seen. The difference from that shown in Figure 4.12 is with respect to the losses whichare not included, i.e. the dynamic simulation assumes ideal components. The simulationcommand is .ac which is an AC sweep from 1Hz to 1MHz with 300 points per decade. TheAC sweep acts on the voltage source Vduty which is an AC source with amplitude 1. For theDC operating point solution required to start the AC sweep Vduty is set to 0.9V.


L1 L4.7µF

C1

400mV

V1RL1

84.2ohm

0.9AC 1

Vduty1

CCM-DCM1

L=L fs=300k

outin

d

sw

.lib average.lib

.ac dec 300 1 1Meg

.param L 240n

--- C:\Users\sturla.lange\Desktop\2018-05-25\LTSpice models\boost_DCM_model_verification_OL.asc ---

FIGURE 4.14: Simulation setup for model verification of dynamiccharacteristics in LTspice

The simulation results are shown in Figure 4.15. By comparing this figure to Figure 4.11ait can be seen that the dynamic modelling used in Section 4.2.2 was a simplified version anddid not include the high frequency zero of the Boost converter when operated in DCM. Thisdoes not affect the phase margin measurement greatly. The phase margin is measured as 88°,compared to the calculated value of 101°, and still meets the design specifications.

100 101 102 103 104 105 106

Frequency [Hz]

−40

−20

0

20

Magnitude

[dB]

(A) Magnitude

100 101 102 103 104 105 106

Frequency [Hz]

−250

−200

−150

−100

−50

0

Phase

[deg]

(B) Phase

FIGURE 4.15: Model verification of dynamic characteristics for the Boostconverter in DCM

4.2.4 Worst-Case Analysis

Component tolerances must be considered to achieve a robust design, components availablefrom manufacturers have a tolerance range within which the component will be. Precisecomponents can be acquired but with increased cost. In this thesis it is assumed that theinductor and capacitor have a tolerance of 10%.

The AC simulation described in Section 4.2.3 is run with 9 different combinations of theinductor value and the capacitor values adjusted up and down 10% as well as the originalvalue. This results in 9 phase margins, the worst case occurs for a 10% lower value for bothcomponents. The specifications are still met in this worst case and so the design should bestable despite maximum drift in the component values.

The simulated values are summarised in Table 4.4.


TABLE 4.4: Calculated worst case phase margin for Boost converter in DCM

L C φm

216nH 4.23µF 86.3°240nH 4.23µF 87.1°216nH 4.70µF 87.2°264nH 4.23µF 87.7°240nH 4.70µF 88.0°216nH 5.15µF 88.0°264nH 4.70µF 88.6°240nH 5.15µF 88.7°264nH 5.15µF 89.3°

4.2.5 Evaluation

In order to evaluate the choice of sampling frequency, the critical frequency can becalculated as described by Equation (2.8): fcrit =

PcondWsw

= 611MHz. The critical frequencyis significantly higher than the chosen switching frequency of fs = 300kHz. In general,increasing the frequency leads to a lower value for the energy storing elements in a converter,which means smaller inductors and capacitors. The trade-off comes from the switchinglosses which increase with frequency. Assuming that the sampling frequency is set to equalthe critical frequency, the switching losses become Psw2 = fcritWsw = 97.7mW, significantlyhigher than the losses of 48µW at fs = 300kHz. The efficiency is 67.1%, a significant dropin efficiency. It is clear from the efficiency vs. duty cycle graph shown in Figure 4.13a thatthe design meets the specified efficiency. In Section 4.2.4 it has been verified that the stabilityof the converter will not be compromised despite 10% component tolerance.

4.3 Results and Discussion

In this section the results will be presented and discussed. First, the most important datacollected for the background chapter is discussed. This is followed by a discussion on thechoice of topology and finally, an overall evaluation of the designs from Sections 4.1 and 4.2is presented.

4.3.1 Data collection

The data collected from the investigation through literature is the following.Interfacing a DC-DC converter with a discontinuous input current with a solar cell leads

to less power transfer since the energy generated while the converter does not accept anyinput current will be lost.

The Boost converter in CCM cannot control both the output voltage and the inputresistance. To be able to regulate the output voltage and at the same time adjust its inputresistance the Boost converter must be operated in DCM. By operating the Boost converterin DCM its input resistance depends on the duty cycle and switching frequency. The inputresistance of a Boost converter operated in DCM is

Rin =VI

II=

2 fsLD2 +DD1

. (4.34)

This information was used to choose the topology and its operating mode during design.A market research was conducted, and the comparison of the commercial solutions in

Table 3.10 shows that none of these solutions meet the specifications to the full extent.


4.3.2 Analysis of Topologies and Control Strategies

Five different topologies were considered: the Buck, Boost, Buck-Boost, Cuk and SEPIC.The Buck converter was dismissed since it is limited to stepping down voltage. The Buck-Boost converter has a discontinuous input current and thus it was dismissed because of theresult from data collection, that interfacing such a converter with a solar cell leads to lesspower transfer. The Cuk was dismissed because of its inverting characteristic. The SEPICwas dismissed because of the increased conduction losses assumed to arise from its additionalenergy storing components, compared to the Boost. Through this analysis and the collecteddata the Boost converter topology was chosen.

4.3.3 Overall Evaluation

In Sections 4.1 and 4.2 the Engineering Design Process was followed when two converterswere designed, both using the Boost converter topology. The Boost converter designed inSection 4.1 operates in CCM, the decision to operate in CCM is made to avoid loosing powerdue to discontinuous input current resulting in no power transfer for a part of the PWMsignal’s period. As is explained in Section 4.1.5 this design cannot work as both a voltageregulator and a MPP tracker at the same time. This lead to the next design, a Boost converteroperated in DCM. By operating the Boost in DCM MPPT can be achieved at the same timeas voltage regulation, this is because the input resistance depends on D and fs when the Boostis operated in DCM. Assuming that the Boost in DCM has a perfect MPPT a fair comparisonof the two designs can be made in the following way: ηtot,DCM = ηMPPT ,DCM×ηBoost,DCM =1.0× 0.803 = 0.803 and ηtot,CCM = ηMPPT ,CCM ×ηBoost,CCM = 0.834× 0.847 = 0.706.It is clear that the converter efficiency is lower for CCM than DCM. However, despite notachieving MPPT the CCM is only 10% from the specified efficiency of 80%. It shouldbe noted that ηMPPT ,CCM is calculated assuming a certain matching coefficient (see Section4.1.5) and that changing it will affect this result greatly. Inductor resistance is the largestcontributor to losses in both designs. The design values and converter efficiency levels forthe two designs are summarised in Table 4.5. There it can be seen how the design for DCMhas a much smaller inductance, a wider duty-cycle range and a higher converter efficiency.

TABLE 4.5: Calculated values for Boost converter in DCM and CCM

Variable CCM DCML 75 µH 240 nHC 2.2 µF 4.7 µFDmin 0.895 0.474Dmax 0.943 0.904PrL 110 mW 70.1 mWη 0.725 0.803ηmin 0.847 0.808φm,min −85.6° 88°

49

Chapter 5

Conclusions and Future Work

The goals for this project were

1. To investigate and identify DC-DC converters suitable for Exeger’s specific application,charging battery-powered embedded devices with their DSSC.

2. To analyse of circuit models based on the most promising topology and controlstrategy.

3. To evaluate the efficiency of the proposed design through simulations.

The results of the investigation of suitable DC-DC converters for Exeger’s application aresummarised and presented in this thesis. This information was used to choose the topologyand its operating mode during design.

The specifications for a DC-DC converter that interfaces a DSSC and a Li-based batterywere derived. These specifications give a basis for evaluating solutions and give constraintsfor designs. A market research was conducted, and the comparison of the commercialsolutions shows that none of these solutions meet the specifications to the full extent. Asthe market research indicated that an application specific solution would be logical, a designmeant to meet the specifications was performed.

The choice of topology was based on the information collected and presented in Chapter2, eliminating all the considered topologies except the Boost converter.

Two designs based on the specifications were performed, a Boost converter operated inCCM on one hand and DCM on the other hand. These design were evaluated by calculationsand simulations in LTspice. The design with a Boost operated in CCM has an efficiency of72.5%, missing the specified minimum efficiency of 80%. Furthermore, the design did notmeet the requirement to achieve MPPT and voltage regulation at the same time. The seconddesign presented, a Boost converter operated in DCM, was introduced to achieve both MPPTand voltage regulation at the same time. This design was also evaluated using calculationsand simulations in LTspice which showed that it has an efficiency of 80.3% and that it canachieve both voltage regulation and MPPT at the same time.

In this thesis simplified models for the battery and DSSC were used, more accurate resultsmay be reached by using the many models suggested in the literature for modelling thesedevices. The MPPT control system was not implemented or tested since the aim was to designa converter capable of MPPT and not to implement the MPPT itself. The implementation ofan MPPT control system is the subject of many articles in the literature. The thesis did notinvestigate the numerous system components needed for the operation of a fully functionalDC-DC converter, such as a clock generator, voltage reference, current limiter and shortcircuit protection. Further research into developing a DC-DC converter suitable for chargingbattery-powered embedded devices with Exeger’s DSSCs may benefit from taking a closerlook at these. Furthermore, management of multiple solar cells was not taken into accountbut this may be of interest since it could possibly account for the problems that arise fromconnecting multiple cells together, such as shading and ageing effects.

Chapter 5. Conclusions and Future Work 50

Based on the investigation and preliminary designs in this thesis, a future circuit that hashigh efficiency for the expected operating conditions, resulting in a highly efficient systemfor integration with embedded consumer devices, can hopefully be developed.

51

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