stmp3500 reference sch revb

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STMP35XX Reference Schematics

REV. A - 3/3/03

Original Release

Revision History

7) If required, select one of the "FM Tuner" pages.

5) Select options on the "Display" page as required.

1) Select USB and Microphone options on "USB & MICROPHONE" page

NAND flash only

STMP35XX 144-BGA Dual Channel Buck Mode

3) Select one of the STMP35XX pages:

MMC + NAND flash

STMP35XX 100-TQFP Single Channel Buck Mode

4) Select one of the "Memory" pages:

To use these schematics to create a design:

8) If required, select any of the circuits on the "Optional Circuits" page.

NOTE: These schematics arepreliminary and are subject tochange.

REV. B - 8/20/03

Added Switched USB Jack 3500 page

Edited boot mode tables.

Updated the Buck mode Play/Pswitch circuit to prevent excessivecurrent being injected into the Pswitch pin.

STMP35XX USB Shared Jack Boost Mode

Added Optional Line-In circuit to Optional Circuits Page.

Added 35XX 1-Channel Buck page

6) Select options on the "Buttons" page as required.

Removed 35XX 144QFP information.

Added Panasonic BTF-03 FM Tuner page.

STMP35XX 100-TQFP Boost Mode

Removed C115 and C116, optional ESD caps on USB D+ and D-.

Removed R139, NOPOP resistor shorting VDDIO to VDDIO_P.

Changed LED drive to match 3410 Rev. G schematics (andkeep the same polarity as 3410 SDK LEDs).Changed the value of resistors to PSwitch from 47K to 20K.

Added pull-up resistors on MMC socket pins 8 and 9.

Added optional 16-bit NAND support.

Updated Boot Mode tables.

Removed SmartMedia circuit.

Changed default TEA5767 FM Tuner connections as follows:

FM_DATA changed from GPIO_19 to I2C_DATAFM_CLOCK changed from GPIO_18 to I2C_CLKSWP1 changed from I2C_CLK to GPIO_33

Removed TEA5757 FM Tuner.

Rev. B

2) Select one of the audio pages: 100QFP STMP35XX Audio Options

144BGA STMP35XX Audio Options

USB & MICROPHONE

DISPLAY

FM TUNER

FM Tuner

Page 2

BUTTONS

STMP35XX3 or 14

Microphone

AUDIO

OPTIONALCIRCUITS

Host Computer

MAIN MEMORY

BacklightLED

24.000MHz crystal

Page 3 or 4

Boot ModeSelect

DCDCConverterComponents

Battery

Page 12

Page 5, 6, 7, or 8

HeadphoneConnector

Misc. Circuits

Page 9 or 10

Headphones

STMP35XX

Page 11

Button Matrix

LiquidCrystalDisplay(LCD)

Page 15

VoltageGenerationCapacitors

Universal Serial BusConnector

Block Diagram

NAND FLASH

SD/MMC Connector

Added SW24 (Reset Button) option to STMP35XX pages.

Removed 1K pull-up to VDDIO on the Hold Switch.

B


B

1 15Monday, September 08, 2003

Revision History

Title

Size Rev

Date: Sheet of

This design is the property of SigmaTel, Inc. It is offered on an "as is" basis, and carries no implied warranty.

www.sigmatel.comtel: (512)381-3700Austin, TX 78704

Suite 3003815 Capital of Texas Hwy.

SigmaTel, Inc.

Page

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

L13 and L14 are placeholders for optional ferrites that can be populated for ESDimmunity if necessary. If they are not required, populate a 0 ohm resistor.

OPTION 1: Microphone using LRADC1 MIC_BIAS

Use this circuit if it is notpossible to use the LRADCmicrophone bias circuit.

Microphone Bias OptionsUSB 2.0 Connector

Use 20 mil minimum spacing between D+ and D- and other signal lines.

OPTION 2: Microphone using VDDIO bias

In order to maximize ESD immunity, the industrial design plastics should expose theUSB Connector as little as possible.

Route USB D+ and D- according to the High Speed USB2.0 Design Guidelines.

Note: If the LRADC1 line is unavailable, LRADC2 may be used for theMicrophone Bias. If both LRADC1 and LRADC2 are unavailable, useOPTION 2.

D+ and D- should have a 90 ohm differential trace impedance.

CN1 Pins 6-9 are pins connecting to the USB connector outer shield

B


B


USB & MICROPHONE

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

USB_D+

MIC

USB_5V

MIC

LRADC1

USB_D-

GNDGND

GND

VDDIO_P

GND

AGND

AGND

+C3810uF6.3VTantalum

L14600 Ohms @ 100MHzDCR < 350mOhms

C390.1uF

C132NOPOP

C37

0.1uF

C37

0.1uF

C360.1uF

R26

2.2K 10%

L13600 Ohms @ 100MHz

DCR < 350mOhms

R18

0 Ohm

X1

WM-62A Microphone

R19

0 Ohm

L22

600 Ohms @ 100MHzDCR < 350mOhms

R161

0 Ohm

R252.2K10%

C133NOPOP

CN1USB_AMP_MINI

123459

8

76

X1

WM-62A Microphone

T1COMMON MODE CHOKENOPOP

R160

0 Ohm

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

This connection should be as close tothe Headphone Jack as possible.

Direct Drive Headphone Jack

NOTE: HP_GND_A is the antenna for designs with an FM Tuner

AC-Coupled Headphone Jack

For a design using a 100QFP with an FM Tuner or Line-In Jack:

For a design using a 100QFP with no FM Tuner or Line-In Jack:

OPTION 1: LINE-IN CIRCUIT ONLY

For the 100 Pin QFP package, onlyone set of LINE IN inputs areavailable. If a LINE-IN Jack and anFM Tuner are both included in thedesign, they will need to share theLINE-IN input. This circuit uses aswitched audio jack to switchbetween LINE-IN and FM Tuner. When nothing is plugged into thejack, the FM Tuner is connect to theLINE-IN inputs. When a plug isinserted, the FM Tuner will bedisconnect.

OPTION 3: FM TUNER ONLY

OPTION 2: LINE-IN JACK + FM TUNER

100QFP STMP35XX AUDIO OPTIONS

B


B


100QFP AUDIO OPTIONS

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

LINE_OUT_L

LINE_IN_R

LINE_OUT_R

LINE_IN_L

LINE_OUT_R

LINE_OUT_L

HP_GND_A

LINE_IN_R

LINE_IN_RFM_R

LINE_IN_R

LINE_IN_L

FM_L

LINE_IN_L

FM_L LINE_IN_L

FM_R

AGND AGNDAGND

AGND

AGND


DCR < 350mOhmsJ1

headphone

1

23

R2110010%

L5600 Ohms @ 100MHz

DCR < 350mOhms

R221610%

L20


L6600 Ohms @ 100MHz

DCR < 350mOhms

+

C32220uF4VTantalum

C350.01uF

J5

line-in jack

1

23

C340.01uF

C127

1uF

R231610%

C126

1uF


DCR < 350mOhms

J1

headphone

1

23

+

C33220uF4VTantalum


L5600 Ohms @ 100MHz

DCR < 350mOhms

C127

1uF

C126

1uFJ5

CUI SJ-3525Nline-in jack

2

51

43

R231610%

C350.01uF

L4600 Ohms @ 100MHz

DCR < 350mOhms

R221610%

C340.01uF

L4600 Ohms @ 100MHz

DCR < 350mOhms


R2010010%


L20


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

For a design using a 144BGA with FM Tuner or Line-In Jack:

This connection should be as close tothe Headphone Jack as possible.



OPTION 1: LINE-IN CIRCUIT ONLY

If a LINE-IN Jack and an FM Tunerare both included in the design,they will need to share the LINE-INinput. This circuit uses a switchedaudio jack to switch betweenLINE-IN and FM Tuner. Whennothing is plugged into the jack,the FM Tuner is connect to theLINE-IN inputs. When a plug isinserted, the FM Tuner will bedisconnect.

For a design using a 144BGA with FM TUNER and Line-In Jack :


AC-Coupled Headphone Jack

LINE-IN CIRCUIT FM TUNER LINE-IN JACK + FM TUNER


This connection should be as close tothe Headphone Jack as possible.NOTE: HP_GND_A is the antenna for designs with an FM Tuner

OR

144BGA STMP35XX AUDIO OPTIONS

OPTION 2: FM TUNER ONLY

B


B


144BGA AUDIO OPTIONS

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

LINE_IN2_LLINE_OUT_L

LINE_IN2_RLINE_OUT_R

HP_GND_A LINE_IN_R

LINE_IN_L

FM_LLINE_IN_R

LINE_OUT_R

LINE_IN2_R

LINE_IN_L

LINE_OUT_L

FM_R

LINE_IN2_L

HP_GND_A

LINE_OUT_R

LINE_OUT_L

LINE_IN_R

FM_R

LINE_IN2_R

LINE_IN_L

FM_L

HP_GND_A

LINE_IN2_L

FM_R

FM_L

LINE_IN2_R

LINE_IN2_L

AGND

AGND

AGND

AGND AGND

AGND

L4600 Ohms @ 100MHz

DCR < 350mOhmsC127

1uF

R2010010%

L6600 Ohms @ 100MHz

DCR < 350mOhms

L5600 Ohms @ 100MHz

DCR < 350mOhms

C350.01uF


C127

1uF

L4600 Ohms @ 100MHz

DCR < 350mOhms

C126

1uF

L5600 Ohms @ 100MHz

DCR < 350mOhms


DCR < 350mOhms

C350.01uF

L5600 Ohms @ 100MHz

DCR < 350mOhms

J5

CUI SJ-3525Nline-in jack

2

51

43

R231610%

L20



R231610%

L20


C126

1uFJ1

headphone

1

23

R221610%L6

600 Ohms @ 100MHz

DCR < 350mOhms

R221610%

J1

headphone

1

23

C340.01uF


DCR < 350mOhms


L4600 Ohms @ 100MHz

DCR < 350mOhmsJ1

headphone

1

23

C340.01uF

R221610%

C127

1uF

+

C33220uF4VTantalum


DCR < 350mOhms

R231610%

C340.01uF

J5

line-in jack

1

23

+

C32220uF4VTantalum

J5

line-in jack

1

23

R2110010%

C350.01uF

C126

1uF


L20


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

1

One cap for each pin (29, 96)

XTAL must beclose to theSTMP35XX

Route GND back to the battery negative terminal as eithera 30mil trace or as part of a wide digital ground plane

E

The industrial design plastics should mechanicallyprevent a battery accidentally inserted backwards frommaking contact with the battery terminals.

TOP VIEW

Tie all grounds togetherunder the IC

IMPORTANT DESIGN NOTES

GROUNDING & POWER

3

"Power/Play/PauseButton"

SOT-23

Power/PlaySwitch

MMBT3904

This circuitry creates a VDDIO_P for peripheral devices. When theplayer is powered-down, VDDIO_P will drop to GND. This allowsperipheral devices to receive a power-on reset, since VDDIO dropsto the battery voltage when the player is powered down.

2

TOP VIEW

D

Route VDD_BAT as a 30mil trace from the positivebattery terminal to the L2 inductor, and from the L2inductor to the STMP35XX DCDC_BATT pin.

Si2305DS

3

2

STMP35XX 100-Pin TQFP - BOOST MODE VDDIO_P Power Switch

This circuit shows the STMP35XX in a NiMH or 1.5V Alkalineboost-mode configuration. For the NiMH case, the battery may becharged using USB_5V as a source. The charge current will bedelivered through the DCDC_BATT pin. Care must be taken in thedesign to ensure that the user may not charge an alkaline battery.

B

G

The L2 inductor is a critical component - for best batterylife, L2 should be a quality, low-ESR inductor. ThePanasonic ELL6H inductor or equivalent isrecommended for this component.

NOTE: Vag and Vbg filtercaps should have theirground return paths toVssA1, pin 72.

SOT-23

C

1

One cap betweeneach PWR andGND pair.

S

One cap for each pin (39, 11, 86)

100-Pin TQFP

The D14 diode may be required for batterycharge applications.

The PFET used in this circuit should have anRds,on less than 2 ohms when Vgs = -2.8V. A good choice is an Si2305 transistor orequivalent.

0

STMP35XX BOOT MODE SELECT

1

1

1.8V NAND w/Play Recovery

0

1

1

0

0

0

1

All resistors are 47KRES0603. However, itmay be necessary to usea stronger pull-down,such as a 10K,depending on the LCDused.

0

1

USB

1

Populate either a pull-upor a pull-down on theseGPIOs to select thedesired Boot Mode

1

1

1

1

SPI Slave

0

0

1

1


0

1

01

1

08

SPI Master

I2C Master

0

02

1

00

1

0

3.3V NAND w/PSwitch Recovery

1 1

GPIO

0

BOOT MODE

1

1

1

I2C Slave

0

1

0

1

0

0

0

1

03


1

0

1

1

3.3V NAND w/ PlayRecovery is the DefaultBoot Mode.

"Reset Button"

Note: For players with a non-removeable battery (i.e. rechargeable), itmay be necessary to include switch SW24 (Reset) to allow the user toenter Player Recovery Mode. For players with a removeable battery(i.e. alkaline), this switch is not necessary.

B


C


STMP35XX 100-Pin TQFP - Boost Mode

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

USB_D-

SE#

GPIO_51

SPI_MOSI

ONCE_DRN

GPIO_19

IO0

GPIO_11

IO6

GPIO_32

LINE_OUT_R

GPIO_52

GPIO_08

GPIO_43

FLASH_RDY

SPI_SCK

LINE_IN_R

ONCE_DSK

LRADC2

CE2#

GPIO_09

IO7

SPI_SS

ALE

USB_5V

WE#

GPIO_47

GPIO_07

LRADC2

CE0#

WP#

I2C_DATA

GPIO_01

ONCE_DSI

GPIO_02

IO4

PSWITCH

IO1

CE3#

MIC

PSWITCH

GPIO_49

USB_D+

GPIO_48

GPIO_42

GPIO_05

LINE_IN_L

ONCE_DSO

GPIO_35

GPIO_00

I2C_CLK

IO5

GPIO_04

CE1#

IO2

GPIO_34

CLE

GPIO_18

GPIO_44

RE#

GPIO_06

LINE_OUT_L

GPIO_03

LRADC1

GPIO_46

GPIO_10

IO3

SPI_MISO

GPIO_50

PLAY_SW

GPIO_33

GPIO_08

GPIO_02

GPIO_01

GPIO_03

GPIO_00

AGND

VDD_BAT

GND

VDD5V

VDDD

VDDIO

VDDIO_P

VDDIO

VDDD

VDD_BAT

GND

VDDA

VDDD

GND

VDDIO

GND

AGND

AGND

AGND

VDDA

VDDIO

GND

GND

VDDIO

GND

GND

GND

GND

AGND

VDDD

GND

VDD_BAT

GND

VDDIO

GND

D1410BQ0151 AmpSchottkyNOPOP

R3910K10%

C180.1uF

C250.1uF

Y1

24.000MHz

R847K10%NOPOP

C1290.1uF

L10 Ohm resistor

R947K10%

C70.1uF

C60.1uF

+ C168uF

C170.1uF

L24.7uH1 W

R326201%

C20.01uF

R1147K10%NOPOP

C41uF

C30.1uF

C151uF

C130.1uF

R647K10%

R1447K10%NOPOP

C100.1uF

R1247K10%

R4210K10%

C1301uF

C190.1uF

Q15Si2305

R13

47K10%

R141100K10%

C230.001uF

JP21 2

SW2

SW PUSHBUTTON

R747K10%

+C868uF

C220.001uF

C111uF

R140100K 10%

R1547K10%

C200.1uF

C120.1uF

C50.1uF

C2622pF

R1047K10%NOPOP

R142

100K 10%

L3


C421uF

C2722pF

R4120K10%

+

_

BT1

NiMH / Alkaline Battery

1

2

3

POS

NEG

NTC

C161uF

SW24SW PUSHBUTTON

C210.1uF

U1

STMP35XX

64

63

6265

76

60

55

56

58

5759

72

7071

73

7574

8081

6

29 28

88 89 90 91 92 93 94 95 82 83 85 8446 52 51 53 98 9986 87

100

1 2 3 4 5

25

40414245

24

4344

11 10

27

89

1213

17

21

141516

181920

3031323334353637

22

23

26

39 38544847 5049

6667

797

6869

61

77

78

96 97

VddHP

VssHP

HPLHPR

VddPLL

LRADC2 / TEMP_SENSE / MIC_BIAS

MIC

BATT

LRADC1 / MIC_BIAS

LINE1L / HP_SENSELINE1R / HP_COMMON

VssA1

REF_RESREFp

VddA1

XTALiXTALo

USB_DPUSB_DM

TES

TMO

DE

Vdd

IO1

Vss

IO1

GP

7 / I

2S_D

ataO

2G

P6

/ I2S

_Dat

aO1

GP

5 / I

2S_D

ataO

0G

P4

/ I2S

_BC

LKG

P3

/ I2S

_WC

LKG

P2

/ I2S

_Dat

aI2

GP

1 / I

2S_D

ataI

1G

P0

/ I2S

_Dat

aI0

GP

11G

P9

GP

10G

P8

ON

CE

_DS

IO

NC

E_D

SO

ON

CE

_DS

KO

NC

E_D

Rn

GP

19 /

TIO

1G

P18

/ TI

O0

Vdd

D3

Vss

D3

GP

15 /

SP

I-SS

n

GP

14 /

SP

I_M

OS

I / S

M_W

P2n

GP

13 /

SP

I_M

ISO

GP

12 /

SP

I_S

CK

GP

16 /

I2C

_SC

LG

P17

/ I2

C_S

DA

GP56 / SM_READY / CF_WAITn

GP46 / CF_CDnGP47_CF_READY

GP48 / CF_WPnGP49 / CF_BVD1

GP45 / SM_CE1n / CF_CE0n

GP50 / CF-RESETnGP43 / CF_REGn

Vdd

D2

Vss

D2

GP55 / SM_WPn

GP52 / CF_IORDnGP51 / CF_IOWRn

GP32 / CF_A0GP33 / CF_A1

GP37 / SM_CE2n / CF_A5

GP41 / SM_ALE / CF_A9



GP38 / SM_CE0n / CF_A6GP39 / SM_SEn / CF_A7GP40 / SM_CLE / CF_A8

GP24 / SM_D0 / CF_D0GP25 / SM_D1 / CF_D1GP26 / SM_D2 / CF_D2GP27 / SM_D3 / CF_D3GP28 / SM_D4 / CF_D4GP29 / SM_D5 / CF_D5GP30 / SM_D6 / CF_D6GP31 / SM_D7 / CF_D7

GP42 / CF_A10

GP53 / SM_REn / CF_OEn

GP54 / SM_WEn

Vdd

D1

Vss

D1

DC

DC

_Mod

e2

DC

DC

_Vdd

D

DC

DC

_Vdd

IO

DC

DC

_Gnd

DC

DC

_Bat

t

VbgVag

PS

WIT

CH

GP44 / CF_CE1nADCLADCR

Vdd5V

VddXTAL

VssPLL

Vdd

IO2

Vss

IO2

+C1468uF

Q16

MMBT3904

C90.01uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GROUNDING & POWER

STMP35XX 100-Pin TQFP - 1 CHANNEL BUCK MODE


Route GND back to the battery negative terminal aseither a 30mil trace or as part of a wide digital groundplane

100-Pin TQFP

The L2 inductor is a critical component - for best batterylife, L2 should be a quality, low-ESR inductor. ThePanasonic ELL6H inductor or equivalent isrecommended for this component.

Route VDD_BAT as a 30mil trace from the positivebattery terminal to the STMP35XX input.

NOTE: Vag and Vbg filtercaps should have theirground return paths toVssA1, pin 72.





One cap between eachPWR and GND pair.

One cap between eachPWR and GND pair.

This circuit shows STMP35XX in a Li-Ion single buck-mode configuration. This schematic assumes a Li-Ion battery voltage of 3.0V to 4.2V. The Li-Ionbattery will be recharged using USB_5V as a source, with the constantcurrent charge current being delivered through the BATT pin.

B

Regulator EnableCircuit

2

MMBT3904

SOT-23TOP VIEW

C

E

1

3

0

08

0

BOOT MODE

1

0

1

0USB

0


1

0

01

1

1

1

1


1

02

1

1

0

0

0

0

03

1

1


0

1

1

1

I2C Master

0

1

GPIO

1

00

1

0

1

1

0

0

0

1

I2C Slave

0


SPI Master





1

1

1

1

SPI Slave 1

1

1

0

0

Power/PlaySwitch


Note: For players with a non-removeable battery (i.e. rechargeable),it may be necessary to include switch SW24 (Reset) to allow theuser to enter Player Recovery Mode. For players with a removeablebattery (i.e. alkaline), this switch is not necessary.

"Reset Button"

B


C

6 15Thursday, September 04, 2003

STMP35XX 100-Pin TQFP - 1 Channel Buck Mode

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

ENABLE

ENABLE

IO2

IO6

IO0

IO5

GPIO_10

GPIO_02

GPIO_08

I2C_DATA

GPIO_35

GPIO_03

RE#

SPI_SS

GPIO_05

GPIO_19

SPI_MOSI

GPIO_33

MICCLE

USB_5V

LRADC2

USB_D+

SPI_MISO

PSWITCH

GPIO_09

CE1#

I2C_CLK

FLASH_RDY

SE#

ONCE_DSI

LINE_OUT_L

LINE_IN_R

WP#

GPIO_52

ONCE_DSO

GPIO_32

GPIO_11

USB_D-

GPIO_44

GPIO_42

GPIO_43

CE3#

GPIO_34

IO3IO4

GPIO_04

ALE

GPIO_51

GPIO_00

LRADC1

GPIO_01

GPIO_06

CE0#CE2#

LINE_IN_L

WE#

GPIO_18

IO7

SPI_SCK

LINE_OUT_R

GPIO_07

ONCE_DSK

GPIO_50

IO1

LRADC2

USB_5V

GPIO_48GPIO_47

GPIO_49

ONCE_DRN

GPIO_46

GPIO_00

GPIO_02

GPIO_08

GPIO_01

GPIO_03

PLAY_SW

PSWITCH

VDDA

VDDIO

VDDIO

AGND

AGND

VDDA

AGND

AGND

GND

VDDD

GND

GND

VDD_BAT

GND

AGND

VDDD

VDDIO

VDDD

GND

VDD_BAT

VDD_BAT

GND

VDD5V

GND

VDDIO_P

GND

VDD_BAT

GND

VDDIO

GND

VDD_BAT

GND

L24.7uH1 W

Q13MMBT3904

C130.1uF

U15

Zetex ZXCL300

150mA3.0V Regulator

123 4

5INGNDEN FB

OUT

R1247K10%

C2622pF

R13

47K 10%

C161uF

C50.1uF

C41uF

C1301uF

R747K10%

C230.001uF

R326201%

C180.1uF

C100.1uF

C190.1uF

C111uF

C210.1uF

C250.1uF

C151uF

C170.1uF

R847K10%NOPOP

C20.01uF

C120.1uF

C70.1uF

R1447K10%NOPOP

+

_

BT1

Li-Ion Battery

1

2

3

POS

NEG

NTC

L3

600 Ohms @ 100MHz

DCR < 350mOhms

C2722pF

+ C168uF

C200.1uF

+C868uF

R1147K10%NOPOP

R176

100K 10%

R1547K10%

C220.001uF

+C1468uF

R70100K10%

R947K10%

C60.1uF

+ C12410uF C9

0.01uF

Y1

24.000MHz

JP21 2

C30.1uF

R647K10%

U1

STMP35XX

64

63

6265

76

60

55

56

58

5759

72

7071

73

7574

8081

6

29 28

88 89 90 91 92 93 94 95 82 83 85 8446 52 51 53 98 9986 87

100

1 2 3 4 5

25

40414245

24

4344

11 10

27

89

1213

17

21

141516

181920

3031323334353637

22

23

26

39 38544847 5049

6667

79

76869

61

77

78

96 97

VddHP

VssHP

HPLHPR

VddPLL


MIC

BATT

LRADC1 / MIC_BIAS


VssA1

REF_RESREFp

VddA1

XTALiXTALo

USB_DPUSB_DM

TES

TMO

DE

Vdd

IO1

Vss

IO1

GP

7 / I

2S_D

ataO

2G

P6

/ I2S

_Dat

aO1

GP

5 / I

2S_D

ataO

0G

P4

/ I2S

_BC

LKG

P3

/ I2S

_WC

LKG

P2

/ I2S

_Dat

aI2

GP

1 / I

2S_D

ataI

1G

P0

/ I2S

_Dat

aI0

GP

11G

P9

GP

10G

P8

ON

CE

_DS

IO

NC

E_D

SO

ON

CE

_DS

KO

NC

E_D

Rn

GP

19 /

TIO

1G

P18

/ TI

O0

Vdd

D3

Vss

D3

GP

15 /

SP

I-SS

n

GP

14 /

SP

I_M

OS

I / S

M_W

P2n

GP

13 /

SP

I_M

ISO

GP

12 /

SP

I_S

CK

GP

16 /

I2C

_SC

LG

P17

/ I2

C_S

DA






Vdd

D2

Vss

D2

GP55 / SM_WPn









GP42 / CF_A10


GP54 / SM_WEn

Vdd

D1

Vss

D1

DC

DC

_Mod

e2

DC

DC

_Vdd

D

DC

DC

_Vdd

IO

DC

DC

_Gnd

DC

DC

_Bat

t

VbgVag

PS

WIT

CH


Vdd5V

VddXTAL

VssPLL

Vdd

IO2

Vss

IO2

C1290.1uF

L10 Ohm resistor

R1047K10%NOPOP

C421uF

SW2

SW PUSHBUTTON

R3910K10%

SW24SW PUSHBUTTON

R4210K10%

R4120K10%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STMP35XX 144-Pin BGA 2 Channel BUCK MODE

One cap for each Vdd/Vss pin pair

The L2 and L18 inductors are critical components - for bestbattery life, these inductors should be a quality, low-ESRinductor. The Panasonic ELL6H inductor or equivalent isrecommended.

NOTE: Vag and Vbg filter capsshould have their ground returnpaths to VssA1, pin 105.

This circuit shows STMP35XX in a Li-Ion buck-mode configuration. This schematic assumes a Li-Ion battery voltage of 3.0V to 4.2V. TheLi-Ion battery will be recharged using USB_5V as a source, with thecharge current being delivered through the BATT pin.



One cap for each Vdd/Vss pin pair




Route GND back to the battery negative terminal aseither a 30mil trace or as part of a wide digital groundplane

144-Pin BGA

0

08

0

BOOT MODE

1

0

1

0USB

0


1

0

01

1

1

1

1


1

02

1

1

0

0

0

0

03

1

1


0

1

1

1

I2C Master

0

1

GPIO

1

00

1

0

1

1

0

0

0

1

I2C Slave

0


SPI Master





1

1

1

1

SPI Slave 1

1

1

0

0

GROUNDING & POWER


Power/PlaySwitch

"Reset Button"

Note: For players with a non-removeable battery (i.e. rechargeable),it may be necessary to include switch SW24 (Reset) to allow theuser to enter Player Recovery Mode. For players with a removeablebattery (i.e. alkaline), this switch is not necessary.


B


C


STMP35XX 144-Pin BGA - 2 Channel Buck Mode

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

PSWITCH

USB_D+USB_D-

LRADC2

LINE_IN_LLINE_IN_R

MIC

LINE_OUT_RLINE_OUT_L

LRADC1LRADC2

ONCE_DRN

ONCE_DSOONCE_DSI

ONCE_DSK

GPIO_02GPIO_03

GPIO_01

GPIO_11

I2C_CLK

GPIO_18

GPIO_04

GPIO_08GPIO_10

GPIO_19

SPI_MOSI

GPIO_05

SPI_SCKSPI_MISO

GPIO_09

GPIO_06

SPI_SS

GPIO_07

GPIO_00

I2C_DATA

GPIO_33

GPIO_35

IO6IO7

GPIO_51

FLASH_RDY

GPIO_34

CE0#

IO0

IO5

SE#

GPIO_43

GPIO_47

CE3#

WP#

CLE

IO4

WE#

GPIO_46

GPIO_42

CE2#

GPIO_32

GPIO_49

IO1

GPIO_50

RE#

GPIO_48

GPIO_52

GPIO_44

CE1#

IO3

ALE

IO2

USB_5V

IO15

IO11IO12

IO10IO9IO8

IO14IO13

GPIO_00

GPIO_02

GPIO_08

GPIO_01

GPIO_03

LINE_IN2_LLINE_IN2_R

PSWITCH

PLAY_SW

GND

GND

VDDD

VDDD

AGND

GNDVDD_BAT

GND

AGND

VDDA

AGND

VDD_BAT

AGND

VDDIO

GND

GNDVDD_BAT GND

GND

VDDIO

VDD5V

GND

VDDIO

GND

VDDDVDDA

GNDAGND

VDDIO_P VDDIO

GND

VDD_BAT

R326201%

C60.1uF

C50.1uF

R747K10%

C1190.1uF

SW2

SW PUSHBUTTON

+C868uF

C210.1uF

L10 Ohm resistor

C190.1uF

R13

47K 10%

C2722pF

+C1468uF

C20.01uF

C180.1uF

R847K10%NOPOP

+

_

BT1

Li-Ion Battery

1

2

3

POS

NEG

NTC

C1200.1uF

R1447K10%NOPOP

+ C168uF

R4120K10%

C90.01uF

U1

STMP35XX

M2

L2 K4

M3

L3H6

M4

J5L4

G6

H7

M5

K5

L5

M6

K6

J6

L6

L7

K7

F7

G7

M7

J7

L8

K8

M8

J8

M9

L9

K9

L10M10

M11K10

M12

L12

L11

K11

K12

J9

H8

G8

J10

J12

H9

J11

H12

H11

H10

G11

G10

G12

G9

F9

F11

F12

F10

F8

E8

E9

E12E10E11

C11D11

D10

B11

C3C4

B3A4

B4A5

C5D4

A6

D5

D6

C6

B6

B8

D7

A7

M1

L1 K1

K2

K3

J4

H5

G5

J2J1 H1

H2

J3H4

G1

H3

G2

G3

F1

G4

F2

F3

F4

F5

F6

E1

D1

E2

D2

E3

C1C2

D3

E5

E4

B1

A8

A12

B12

C12

D12

A11

B10

A10

A9

C10

D9

C9

A1

E6

E7

A2

B2

B5

A3

B9

B7

C7

C8

D8

GP

14 /

SP

I_M

OS

IG

P13

/ S

PI_

MIS

OG

P12

/ S

PI_

SC

KG

P16

/ I2

C_S

CL

GP

17 /

I2C

_SD

A

TES

TMO

DE

GP44 / CF_CE1n


Vss

D2

Vdd

D2

GP32 / CF_A0 / RAM_A0

GP

69 /

CF_

A22


GP

68 /

CF_

A21


GP

67 /

CF_

A20


GP

66 /

CF_

A19

GP36 / SM_CE3n / CF_A4 / RAM_A4

Vdd

IO3

Vss

IO3

GP

65 /

CF_

A18


GP

64 /

CF_

A17


GP

63 /

CF_

A16

GP39 / SM_SEn / CF_A7 / RAM_A7

GP

62 /

CF_

A15

/ R

AM

_A13

GP40 / SM_CLE / CF_A8 / RAM_A8

GP

61 /

CF_

A14

/ R

AM

_A12

GP41 / SM_ALE / CF_A9 / RAM_A9GP42 / CF_A10 / RAM_A10

GP53 / SM_REn / CF_OEnGP45 / SM_CE1n / CF_CE0n


GP

80 /

CF_

A11

/ R

AM

_A11

GP54 / SM_WEn / CF_WEn

GP

81 /

CF_

A12

/ R

AM

_BA

0

GP55 / SM_WPn

GP

82 /

CF_

A13

/ R

AM

_BA

1

Vss

IO1

Vdd

IO1

GP24 / SM_D0 / CF_D0 / RAM_D0

GP79 / CF_D15 / RAM_D15


GP78 / CF_D14 / RAM_D14


GP77 / CF_D13 / RAM_D13


GP76 / CF_D12 / RAM_D12


GP75 / CF_D11 / RAM_D11


GP74 / CF_D10 / RAM_D10


GP73 / CF_D9 / RAM_D9


Vss

D1

Vdd

D1

GP72 / CF_D8 / RAM_D8

GP46 / CF_CDnGP47 / CF_READY

GP48 / CF_WPn

GP50 / CF_RESETnGP43 / CF_REGn

GP49 / CF_BVD1

ON

CE

_DS

I

REFpREF_RES

ADCRADCL

VagVbg

LINE2RLINE2L

HPR

VddHP

DC

DC

_Mod

e1

VssHP

HPL

LINE1L / HP_SENSE

BATT

MIC

GP

70 /

CF_

A23

GP

15 /

SP

I_S

Sn

GP

91 /

I2S

_WC

LK

GP

18 /

TIO

0

GP

93 /

I2S

_BC

LK

GP

19 /

TIO

1

Vss

IO2

Vdd

IO2

GP

92 /

I2S

_Dat

aI0

GP

0 / I

2S_D

ataI

0

GP

87 /

RA

M_W

En

GP

1 / I

2S_D

ataI

1

GP

86 /

RA

M_C

AS

n

GP

2 / I

2S_D

ataI

2

GP

85 /

RA

M_R

AS

n

GP

3 / I

2S_W

CLK

GP

88 /

RA

M_C

Sn

GP

4 / I

2S_S

CK

GP

89 /

RA

M_C

KE

GP

5 / I

2S_D

ataO

0

GP

84 /

RA

M_D

QM

1

GP

6 / I

2S_D

ataO

1G

P7

/ I2S

_Dat

aO2

Vss

D3

Vdd

D3

GP

10G

P8

GP

90 /

RA

M_C

LK

GP

9G

P11

USB_DMUSB_DP

PS

WIT

CH

VssPLL

VddXTAL

VddPLL

LRADC1 / MIC_BIAS

DC

DC

_Gnd

DC

DC

_Bat

t

DC

DC

_Vdd

D

DC

DC

_Vdd

IO

DC

DC

_Vdd

A

DC

DC

2_G

nd

DC

DC

2_B

att

DC

DC

2_V

out

ON

CE

_DS

KO

NC

E_D

SO

ON

CE

_DR

n

XTALi

Vss

IO4

Vdd

IO4

XTALo

VddA1

VssA1

DC

DC

_Mod

e0

GP

83 /

RA

M_D

QM

0

Vdd5V


LINE1R / HP_COMMON

DC

DC

_Mod

e2

SW24SW PUSHBUTTON

C1301uF

R1147K10%NOPOP

C30.1uF

L3

600 Ohms @ 100MHz

DCR < 350mOhms

R3910K10%

Y1

24.000MHz

L184.7uH1 W

R1547K10%

C200.1uF

C130.1uF

C100.1uF

R947K10%

C41uF

C161uF

C120.1uF

C230.001uF

L2

4.7uH 1 W

R647K10%

C111uF

R1047K10%NOPOP

C151uF

JP21 2

C2622pF

C220.001uF

C170.1uF

R1247K10%

C421uF

C250.1uF

C1290.1uF

C70.1uF

R4210K10%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STMP35XX 100-Pin TQFP - Switched USB Jack - BOOST MODE

The L2 inductor is a critical component - for best battery life, L2should be a quality, low-ESR inductor. The Panasonic ELL6Hinductor or equivalent is recommended for this component.

MMBT3904

2

Si2305DS

G

1

1

E

3

D

2

B

C

S

This circuitry creates a VDDIO_P for peripheral devices. When theplayer is powered-down, VDDIO_P will drop to GND. This allowsperipheral devices to receive a power-on reset, since VDDIO dropsto the battery voltage when the player is powered down.

3

VDDIO_P Power Switch

SOT-23TOP VIEW

SOT-23TOP VIEW

This circuit shows the STMP35XX in a NiMH or 1.5V Alkalineboost-mode configuration. The USB Jack is used for both USB and forsupplying the battery connection. Battery charge is not available inthis configuration.

NOTE: Vag and Vbg filter capsshould have their ground returnpaths to VssA1, pin 72.


One cap for each pin (39, 11, 86)

One cap for each pin (29, 96)


Power/PlaySwitch


Route GND back to the battery negative terminal as eithera 30mil trace or as part of a wide digital ground plane

IMPORTANT DESIGN NOTES"Power/Play/PauseButton"

100-Pin TQFP

The PFET used in this circuit should have anRds,on less than 2 ohms when Vgs = -2.8V. A good choice is an Si2305 transistor orequivalent.

The PNP transistor used for Q28 should have low Vce,satcharacteristics. When the power button is pressed, the transistorbase current will be about 1mA when the 5V_or_1.5V power rail is .9V. At this point, the STMP35XX will begin to start up and VDD_BAT willrequire about 35mA, which will be the current flowing through thecollector of the FMMT717 transistor. Given 35mA of collector currentand 1mA base current, the Vce,sat of the FMMT717 transistor will beabout 12mV. Because the voltage on the PSWITCH pin must also be> 900mV during startup, the battery voltage required for startup usingthe FMMT717 transistor will be about 912mV. Similarly, the batteryvoltage required for startup using a FMMT591A transistor will be about940mV. If a PNP transistor with higher Vce,sat. characteristics isused, such as the MMBT3906, the startup voltage will be 1.05V orhigher. Please consult the transistor datasheet.

The NFET used for Q27 should have characteristics similar to theSi2312DS N-channel mosfet. The minimum gate threshold voltagemust be 1.2V or less. The most important characteristic of thismosfet is the Rds,on for a given Vgs. The Rds,on should be 0.06ohms or less when Vgs = 1.8V. Using a mosfet with higher Rds,oncharacteristics may decrease battery life.

The PFET used Q26 and Q30 in this circuit should have an Rds,on lessthan 2 ohms when Vgs = -2.8V. A good choice is an Si2305 transistor orequivalent.

0

08

0

BOOT MODE

1

0

1

0USB

0


1

0

01

1

1

1

1


1

02

1

1

0

0

0

0

03

1

1


0

1

1

1

I2C Master

0

1

GPIO

1

00

1

0

1

1

0

0

0

1

I2C Slave

0


SPI Master





1

1

1

1

SPI Slave 1

1

1

0

0

GROUNDING & POWER


B


C


STMP35XX 100-Pin TQFP - Boost Mode

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

1.5V_PRESENT

1.5V_PRESENT

PSWITCH

USB_D-USB_D+

LINE_IN_LLINE_IN_R

LINE_OUT_L

MIC

LINE_OUT_R

LRADC2LRADC1

ONCE_DSI

ONCE_DRN

ONCE_DSOONCE_DSK

GPIO_03

GPIO_01

GPIO_11

I2C_CLK

GPIO_09GPIO_10

GPIO_02

GPIO_19

GPIO_00

GPIO_08

GPIO_18

GPIO_07

SPI_MOSI

GPIO_05

SPI_SCK

GPIO_06

I2C_DATA

GPIO_04

SPI_SS

SPI_MISO

CE3#

GPIO_32

CLE

GPIO_47

GPIO_33

GPIO_49

GPIO_52

GPIO_34

WE#

CE1#

ALE

GPIO_50

GPIO_42

FLASH_RDY

RE#

WP#

GPIO_51

GPIO_48

GPIO_43

GPIO_44

CE0#SE#

GPIO_35

CE2#

GPIO_46

IO1

IO6IO5

IO7

IO3IO4

IO0

IO2

PLAY_SW

PSWITCH

GPIO_00

GPIO_02

GPIO_08

GPIO_01

GPIO_03

VDDIO

GND

GND

VDDD

VDDIO VDDIO_P

GND

VDDD

GNDVDD_BAT

AGND

AGND

VDDA

VDD_BAT

AGND

VDDIO

GND

VDD_BAT

GND

VDDD

GND

VDDIO

GND

AGND

GND

VDDIO

GND

GND

5V_or_1.5V

5V_or_1.5V

GND

VDDIO

GND

GND

VDDIO

GND

VDDDVDDA

GNDAGND

R18320010%

R4120K 10%

Q30Si2305

R4210K10%

L3

600 Ohms @ 100MHz

DCR < 350mOhms

R18747K10%

R184

10K 10%

Y1

24.000MHz

C130.1uF

R647K10%

R141100K 10%

R1047K10%NOPOP

C2722pF

C111uF

C60.1uF

C90.01uF

+ C168uF

R18210K10%

R1247K10%

L2

4.7uH 1 W

C1301uF

C230.001uF

R140100K 10%

C2622pF

C30.1uF

R747K10%

Q28FMMT717

JP21 2

Q16

MMBT3904

+C1468uF

Q27Si2312DS

C200.1uF

C50.1uF

C210.1uF

C421uF

Q31MMBT3904

R847K10%NOPOP

R13

47K 10%

C100.1uF

C161uF

U1

STMP35XX

64

63

6265

76

60

55

56

58

5759

72

7071

73

7574

8081

6

29 28

88 89 90 91 92 93 94 95 82 83 85 8446 52 51 53 98 9986 87

100

1 2 3 4 5

25

40414245

24

4344

11 10

27

89

1213

17

21

141516

181920

3031323334353637

22

23

26

39 38544847 5049

6667

79

76869

61

77

78

96 97

VddHP

VssHP

HPLHPR

VddPLL


MIC

BATT

LRADC1 / MIC_BIAS


VssA1

REF_RESREFp

VddA1

XTALiXTALo

USB_DPUSB_DM

TES

TMO

DE

Vdd

IO1

Vss

IO1

GP

7 / I

2S_D

ataO

2G

P6

/ I2S

_Dat

aO1

GP

5 / I

2S_D

ataO

0G

P4

/ I2S

_BC

LKG

P3

/ I2S

_WC

LKG

P2

/ I2S

_Dat

aI2

GP

1 / I

2S_D

ataI

1G

P0

/ I2S

_Dat

aI0

GP

11G

P9

GP

10G

P8

ON

CE

_DS

IO

NC

E_D

SO

ON

CE

_DS

KO

NC

E_D

Rn

GP

19 /

TIO

1G

P18

/ TI

O0

Vdd

D3

Vss

D3

GP

15 /

SP

I-SS

n

GP

14 /

SP

I_M

OS

I / S

M_W

P2n

GP

13 /

SP

I_M

ISO

GP

12 /

SP

I_S

CK

GP

16 /

I2C

_SC

LG

P17

/ I2

C_S

DA






Vdd

D2

Vss

D2

GP55 / SM_WPn









GP42 / CF_A10


GP54 / SM_WEn

Vdd

D1

Vss

D1

DC

DC

_Mod

e2

DC

DC

_Vdd

D

DC

DC

_Vdd

IO

DC

DC

_Gnd

DC

DC

_Bat

t

VbgVag

PS

WIT

CH


Vdd5V

VddXTAL

VssPLL

Vdd

IO2

Vss

IO2

R1447K10%NOPOP

R326201%

Q29MMBT3904

R142

100K 10%

R3910K 10%

R18610K10%

C41uF

C70.1uF

SW2

SW PUSHBUTTON

R1147K10%NOPOP

R18522K10%

C170.1uF

C1290.1uF

C220.001uF

R1547K10%

R18810K10%

+C868uF

Q15Si2305

R947K10%

C180.1uF

C151uF

Q26Si2305

C120.1uF

C250.1uF

C20.01uF

C190.1uF

L10 Ohm resistor

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FLASH_RDYPullup

Integration

On PageLabels

STMP35XXLabels

STMP35XX CHIP ENABLE ASSIGNMENT

If using a NAND and a MMC Card, it is recommended that the MMC Card use CE3#by default, but this is not required.

If using more than one NAND chip, the firstchip MUST be attached to CE0#, the secondMUST be attached to CE1#, and the thirdMUST be attached to CE2#. The softwarerequires that the NAND chip enables start atCE0# and be consecutive.

L15 and L16 are optional ferrites that maybe required for ESD immunity. If they arenot required, populate a 0-ohm resistor.

MultiMedia Card SocketNAND Flash

WP# Pulldown

CE0# Pullup

Optional Second NAND Flash

CE1# Pullup

3. A pull-up resistor is required on the FLASH_RDYsignal because the flash output is open drain.

2. The CE# pull-up resistor is required to keep theflash de-selected during power transitions.

1. The WP# pull-down resistor is required to protectthe flash memory from inadvertent writes duringpower transitions.

NOTES:

1. The CE# pull-upresistor is required tokeep the flashde-selected duringpower transitions.

NOTES:

B


B


Main Memory - NAND & MMC

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

FLASH_RDY

CE0#

I2C_CLK

MMC_DETECT

IO2

CLE

IO7

RE#

CE0#

I2C_CLK

FLASH_RDY

IO4

IO2IO1

RE#

FLASH_RDY

IO1

I2C_DATA

WE#

MMC_WP

I2C_DATA

IO5

GPIO_32

IO6

CLE

MMC_CS

IO7

IO0

IO3

IO6

WE#

IO3

IO5IO4

IO0

GPIO_52

CE3#

MMC_DATA_OUT

MMC_CLK

SPI_MISO

SPI_SCK

SPI_MOSI

SPI_SSMMC_SS

MMC_DATA_INMMC_SS

MMC_WP

MMC_CLK

MMC_DATA_OUTMMC_DATA_IN

MMC_DETECT

MMC_CS

RE#

WE#

IO4

IO3

FLASH_RDY

IO0

ALE

IO6

CLE

IO5

CE0#

IO7

IO1IO2

WP#WP#

CE0#

WP#WP#

WP# IO1

IO6

IO4

IO2IO3

IO7

ALEWE#

CE1#

IO0

RE#IO5

CLE

FLASH_RDY

CE1#

GND

VDDIO_P

VDDIO_P

VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P VDDIO_P

GND

VDDIO_P VDDIO_P

GND

GND

GND

VDDIO_P

GND

VDDIO_P

GND

GND

VDDIO_P

VDDIO_P

VDDIO_P VDDIO_P

R16847K10%

R2747K10%

C1000.1uF

C1170.1uF

R13847K10%

R19047K10%

R16347K10%

R2910K10%

R18947K10%

U14

FLASH

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748NC

NCNCNCNCSER/BRECENCNCVCCVSSNCNCCLEALEWEWPNCNCNCNCNC NC

NCNCNC

I/O0I/O1I/O2I/O3NCNCNC

VSSVCC

NCNCNC

I/O4I/O5I/O6I/O7NCNCNCNC

R13747K10%

L15

DCR < 350mOhms600 Ohms @ 100MHz

L16

DCR < 350mOhms600 Ohms @ 100MHz

U2

AVX #: 10 5638 009 353 833MMC/SD Socket

1

2

3

4

5

6

7

89

10

11

1213

CS#

DATA_IN

GND

Vdd

SCLK

GND

DATA_OUT

DAT1DAT2

WRITE_PROTECT

CARD_DETECT#

SOCKET_GNDSOCKET_ESD_GND

C400.1uF

R15747K10%

R3510K10%

U3

FLASH

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748NC


NCNCNC


VSSVCC

NCNCNC


C1180.1uF

C410.1uF

R2810K10%

R3047K10%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

On PageLabels

STMP35XXLabels

Integration

If using a NAND and a MMC Card, it is recommended that the MMC Card use CE3#by default, but this is not required.

If using more than one NAND chip, the firstchip MUST be attached to CE0#, the secondMUST be attached to CE1#, and the thirdMUST be attached to CE2#. The softwarerequires that the NAND chip enables start atCE0# and be consecutive.

STMP35XX CHIP ENABLE ASSIGNMENT

1. The WP# pull-down resistor is required to protect theflash memory from inadvertent writes during powertransitions.

FLASH_RDYPullup


NAND Flash

WP# Pulldown

CE0# Pullup

NOTES:


1. The CE# pull-upresistor is required tokeep the flashde-selected duringpower transitions.

CE1# Pullup

Optional Second NAND Flash

NOTES:

A


B


Main Memory - NAND Flash

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

WE#

IO7

CLE

IO1IO0IO1

IO2

IO5

RE#

IO5

WE#

IO6

CE0#

IO6

FLASH_RDY

IO4

IO2

IO7

IO3

IO0

IO3

RE#

CLE

FLASH_RDY

CE0#

IO4

WP# WP#

IO11

IO13IO12

IO15IO14

IO8

IO10IO9

IO10

IO8IO9

IO13IO12IO11

IO15IO14

CE0#

CE0#

IO5

IO1IO2

ALE

FLASH_RDY

CLE

WP#IO3

IO6

RE#

IO7

WE#

FLASH_RDYIO4

WP#IO0

CE1#

CE1#

FLASH_RDY

IO1

IO6

WE#

IO4IO5

IO2

CLE

RE#

IO0

IO7

ALE

WP#

IO3

GND

VDDIO_P

VDDIO_P

GND

VDDIO_P

VDDIO_P

GND

GND

VDDIO_P

VDDIO_P

GND

GND

VDDIO_P

GND

R3510K10%

U3

FLASH

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748NC


NCNCNC


VSSVCC

NCNCNC


R16847K10%

R15747K10%

R16347K10%

C410.1uF

C400.1uF

C1170.1uF C118

0.1uF

U14

FLASH

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748NC


NCNCNC


VSSVCC

NCNCNC


5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Integration

On PageLabels

DOT-MATRIX LCD

STMP35XXLabels

Use for LED-only players.

Optional LEDs

3

Note: To drive the EL backlightusing 3 GPIOs, populate R194and remove R195 and Q37. Ifonly 2 GPIOs are available,populate R195 and Q37, andremove R194.

OPTIONAL PWM EL BACKLIGHT

S2

TOP VIEWSOT-23

D

G

BSS123

1

Optional LED BacklightSize series resistorvalues based of theLED chacteristics

A


B


Display & Backlight

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

GPIO_01

GPIO_07

GPIO_02

GPIO_00

GPIO_06

GPIO_09

GPIO_10

GPIO_04

GPIO_03

GPIO_05

GPIO_08

GPIO_11

LCD_RESET

LCD_D4

LCD_D0

LCD_D5

LCD_D1

LCD_D6

LCD_D7

LCD_DS

LCD_RS

LCD_CS#

LCD_D2

LCD_D3

BL_ON

GPIO_44

LCD_D1LCD_D0

LCD_D5

LCD_CS#

LCD_RS

LCD_D7

LCD_D2

LCD_RESET

LCD_DS

LCD_D3

LCD_D6

LCD_D4

GPIO_05 GPIO_07

GPIO_18

GPIO_19

BL_ON

GPIO_19

GPIO_18

BL_ON

BL_ON

GPIO_18

GPIO_19

GND

VDDIO_P

GND

GND

GND

VDDIO_P

GND

GND

VDDIO

VDDIOGND

VDDIO_P

GND

L23100uH

TDK part #: NLC322522T-101K1 W, 3.7 ohms

R15151010%

Q33BSS123

R19947K10%

GD

S

Q1ZXM61N02FCT3

12

Q32BSS123

J6EL Lamp

12

C45

0.1uF

R5247K10%

R4947K10%

C44

0.1uF

R1921M10%

C46

0.1uF

LTST-C150GKTD12

GREEN LED

Q34BSS123

R19847K10%

R14951010%

Q35BSS123

C491uF

C47

0.1uF

R4751010%

R19347K10%

C520.1uF

C511uF

LTST-C150GKTD10

GREEN LED

D16

DL4148

C501uF

R197

47K 10%

U6

Shing Yih LCD

12

3

4

5

6

7

8

9

10

11

12

1314

15

1617181920212223

2425262728

2930

VddC86

GND

V5

V4

V3

V2

V1

CAP2+

CAP2-

CAP1-

CAP+

CAP3-Vout

GND

DB7DB6DB5DB4DB3DB2DB1DB0

ER/W#A0RES#CS#

NCNC

R1940 Ohm

C48

0.1uF

C1310.1uF100V

R5147K10%

LEDD1

D15

DL4148

R196

47K 10% Q37BSS123

Q36BSS123

C430.1uF

R19510K10%

R1911M10%

D17

DL4148

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VOLUME+

RECORD MODE

ERASEFORWARD A-B

VOLUME-MENU

REVERSE

STOP EQ

Integration

On PageLabels

Buttons

Hold SwitchSTMP35XXLabels

HOLD

PLAY

If a HOLD switch is notrequired, your designMUST either disable theHOLD functionality in thefirmware OR leave the R43pull-down on theHOLD_SW line.

NOTE: If the HOLD switch or certain button SCAN lines are notrequired for your design, you MUST either include pull-downresistors on the HOLD, SCAN_R1, SCAN_R2, and SCAN_R3 lines ORdisable the unused lines in the firmware.

OPTIONAL ROTARY ENCODER

OPTIONAL JOG DIAL

B


B


Buttons

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

SW1SW2

A

B

SCAN_C4SCAN_C3SCAN_C2SCAN_C1

SCAN_R3

SCAN_R2

SCAN_R1

GPIO_43

GPIO_46

GPIO_49

GPIO_42

GPIO_47

GPIO_50

GPIO_34

GPIO_48

PSWITCH

HOLD_SW

SCAN_R2

SCAN_R3

SCAN_R1

SCAN_C3

SCAN_C2

SCAN_C4

SCAN_C1

HOLD_SW

GPIO_35

PLAY_SW

PSWITCH

SCAN_C1SCAN_R3

GPIO_33

CE2#

SCAN_C3

SCAN_R3SCAN_C2

SCAN_C1

GND

VDDIO

GND

GND

VDDIO

GND

GND

VDDIO

GND

GND

SW18

EVE-GA1

Rotary Encoder

5

234

1

678

SW1

BSW1SW2

NC

COMA

NC

R17410K10%

R175

10K 10%

C1210.01uF

R4510K10%

SW12

SW PUSHBUTTON

R4347K10%

SW20

ALPS SLLB120 JogdialRotary Encoder

5

234

1

67

89

10

PUSH

COMCW1CW2

CO

M

CCW2CCW1

GN

DC

H_G

ND

CH

_GN

D

R4610K10%

SW4

SW PUSHBUTTON

R44

10K 10%

SW7

SW PUSHBUTTON

SW13

SW PUSHBUTTON

SW10

SW PUSHBUTTON

SW5

SW PUSHBUTTON

SW6

SW PUSHBUTTON


SW8

SW PUSHBUTTON

R4410K10%

C1220.01uF

SW1SW SLIDE-SPDT

1

3

2

R17210K10%

SW11

SW PUSHBUTTON

R173

10K 10%

SW9

SW PUSHBUTTON

SW3

SW PUSHBUTTON

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Integration

On PageLabels

STMP35XXLabels

Use HP_GND_A as an antenna

NOTE: Currently, the TEA5767 is used in 3-wire mode. Infuture versions of the 35XX SDK, the TEA5767 may beaccessed in I2C mode, which frees up one GPIO. In order tosupport both modes, FM_DATA and FM_CLOCK should havepull-up resistors, and the BUS_MODE pin should have optionsto populate either a pull-up or pull-down resistor.

B


B


FM Tuner - Philips TEA5767HN

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

FM_CLOCK

FM_L

FM_R LINE_IN_R

LINE_IN_L

FM_DATA

SE#BUS_EN

FM_CLOCK

BUS_EN

MPX

FM_R

FM_WEFM_L

FM_DATA

SWP1

SWP1

FM_WE GPIO_51

HP_GND_AI2C_DATA

I2C_CLK

GPIO_33

FM_GND

FM_GND

FM_GND

FM_GND

VDDIO_P

VDDIO_P

VDDIO_P

VDDIO_P

VDDIO_P

AGND

FM_GND

FM_GND

FM_GND

FM_GND

FM_GND

FM_GND

FM_GND

FM_GND

FM_GNDFM_GND

FM_GND

C64330pF

R12547K10%

L8CoilCraft#: 0603CS-R18X_BG180nH @ 100MHz

C62100nF

C5922nF

R61

47K 10%

L11CoilCraft#: 0603CS-33NX_BG33nH @ 250MHz

C6333nF

R592210%

C772.2nF

R582210%

JP3

0 OhmResistorJumper

1 2

D6Philips BB202Varactor

D7Philips BB202Varactor

R12747K10%

C56100nF

C762.2nF

C70

100nF

U9

PHILIPS TEA5767HNFM Tuner

36 35

13

34 33

1

32 3140

14

39

30

38

29

37

2

28

27

15

26

25

3

16

4

17

5

18

6

19

7

20

8

21

9 22

10

23

11

24

12

RFG

ND

RFI

1

BU

SE

N

AV

CC

AG

ND

NC

IFG

AI

NC

NC

SW

P1

LOO

PS

W

NC

TCA

GC

DIFL2

RFI

2

CPOP

DIFL1

TCIFC

SW

P2

VREF

MPXO

VCOT1

XTA

L1

VCOT2

XTA

L2

VCOVCC

PD

LF

DGND

PH

LF

DVCC

NC

DATA

NC

CLOCK LAVO

NC

RAVO

W/R

TMUTE

BU

SM

TP14

C574.7nF

C5447pF

C60

33nF C6133nF

R53100K10%

C5822nF

C6647nF

L12CoilCraft#: 0603CS-33NX_BG33nH @ 250MHz

R12847K10%

C7422pF

C5522pF

+C11422uFTantalum10V

R20047KNOPOP

10%

R5422 10%

C7522nF

R57100K

C53100pF

C731nF

R5610K

C6747nF

R5518K

R12647K10% C69

100nF

X232.768KHzCrystal

R16747K10%

C6847nF

C6533nF

R6033K10%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Optional FM Tuner ModuleThe Panasonic BTF-03 integrates the TEA5767 and most of thediscrete components.

Integration

STMP35XXLabels

On PageLabels

NOTE: Currently, the TEA5767 is used in 3-wire mode. Infuture versions of the 35XX SDK, the TEA5767 may beaccessed in I2C mode, which frees up one GPIO. In order tosupport both modes, FM_DATA and FM_CLOCK should havepull-up resistors, and the BUS_MODE pin should have optionsto populate either a pull-up or pull-down resistor.

Option 2:DA-102 (TEA5767)

B


B


FM Tuner Modules

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

FM_WE

FM_RFM_L

FM_CLOCKBUS_EN FM_DATA

HP_GND_A

SWP1 GPIO_51

LINE_IN_L

LINE_IN_R

BUS_EN

I2C_CLK

I2C_DATA

SWP1

FM_L

FM_R

FM_DATA

FM_CLOCK

GPIO_33

FM_WE

SE#

SWP1

FM_OUT_R

FM_WE

FM_OUT_LFM_CLOCKFM_DATA

BUS_EN

HP_GND_A

FM_GND

GND

VDDIO_P

VDDIO_P

VDDIO_PVDDIO_P

GND

VDDIO_P

GND

AGNDFM_GND

VDDIO_P

VDDIO_P

AGND

VDDIO_P

VDDIO_P

VDDIO_P

FM_GND

R61

47K 10%

R200

47KNOPOP

10%

C126

150pF


U16

DA-102D&A Corporation

12345678 9

10111213141516GND

BUSMODER/WSW1ENABLEDATACLKXTAL GND

OUT-LOUT-R

MPXGNDGNDVCCANT

L54600 Ohms @ 100MHzIND-0805 Ferrite

R12547K10%

R177

22

10%

R16747KRES-0603

10%

C1277pF

R12647K10%

R61

47K 10%

JP3

0 OhmResistorJumper

1 2

Y232.768kHz

C1280.1uF

R12647K10%

R16947K

10%

R16847KRES-0603

10%

U16BTF-03

123456789

1011

12

131415161718

2322212019

24

GNDVCCBUENSW1SW2XTALGNDMPXRIGHTLEFTGND G

ND

GNDRF NGNDGNDGNDGND

GNDCLDAEN

BUS MODE

GN

D

R200

47KNOPOP

10%

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

"FF""PLAY"

2.0V

"RW"

0.5V

"VOL-""VOL+"

1.5V 2.5VVOLTAGE ATLRADC Input=

1.0V

OPTIONAL HEADPHONE REMOTE

Headphone Jack + Remote Control

This circuitry may be built into the headphone cord to provide remote control functionality.

If using this circuit, use the Headphone Jack + Remote Control circuit.

OPTIONAL I2C EEPROM BootUse Microchip 24LCxx-I/P or Equivalent

OPTIONAL ONCE PORT

KEY

Booting from an EEProm requires setting the BootMode to "I2CMaster".

NOTE: Some versions of the LCD controller donot require an external crystal - in that case, Y2,C50, and C51 are not required.

OPTIONAL 16-bit NAND Flash

Optional EL Backlighting

Integration

Note: the voltage on the STMP35XXVDD5V pin needs to be between 4.5Vand 5.25V. If using a DC powersupply greater than 5V, it may benecessary to insert a diode drop tomeet this input voltage requirement.

SEGMENT LCD

To implement this circuit, removethe direct USB_5V connection onthe STMP35XX VDD5V pin, andconnect the USB_5V line througha FET as shown.

NOTE: 16-bit NAND Flash support is only available on the 144BGApackage.

USB Sense

NOTES:

WP# Pulldown

OPTIONAL: Wall Power + USB Power Switch

CE0# Pullup

Place close to SP4423

FLASH_RDYPullup



IMPORTANT: The EL Backlight Driver should have a currentdraw between 5mA and 20mA at 3.0V.

5V DC, 1 A,WallTransformer

1. The WP# pull-down resistor is required to protectthe flash memory from inadvertent writes duringpower transitions.

This circuit allows the STMP35XXto power from an external wallpower supply. In the case wherewall power and USB power areboth connected, the STMP35XXwill power and/or recharge usingthe wall power supply.

B


C


Optional Circuits

Title

Size Rev

Date: Sheet of




SigmaTel, Inc.

Page

HP_CONN_RHP_CONN_L

HP_GND_A

ONDEZ

SEG16

SEG6

SEG2

SEG9SEG0

SEG17

SEG8

SEG10

SEG1SEG15

COM3

SEG13

SEG22 SEG14

SEG17

COM1

COM0

SEG23

SEG3

COM2

SEG20COM1

SEG25SEG26

SEG24SEG23

SEG22

COM0

SEG4

SEG19

SEG21

SEG5

SEG13

SEG1

SEG18

SEG0

SEG16SEG25

SEG15

SEG21

SEG10 SEG2

COM3

SEG3

SEG14

SEG26

COM2

SEG6SEG5

SEG11

SEG9

SEG12

SEG4

SEG18SEG11

SEG24

SEG7

SEG20

SEG7

SEG19

SEG12

SEG8

To LRADC Pin of Heaphone Jack

LRADC1

I2C_CLKI2C_DATA

ONCE_DSI

ONCE_DRN

ONCE_DSO

PSWITCH

ONCE_DSK

GPIO_04

IO11

IO2

CE0#

GPIO_11GPIO_10

IO4IO12

IO14

LCD_CS#LCD_CLK

WP#

BL_ON

IO13IO6

LCD_IRQ# GPIO_05

LCD_IRQ#

CLE

GPIO_33

ALE

CE0#

IO5

LCD_DATA

WP#

LCD_CLK

IO8

USB_5V

FLASH_RDY

WE#

IO15

LCD_DATA

FLASH_RDY

LCD_RD#

IO10

USB_5V

IO9

IO7

IO3

RE#

GPIO_06LCD_RD#

LCD_CS#

IO1

IO0

GND

VDDIO

VDDIO_P

VDDIO

GND

VDDIO_P

VDDIO_P

GND

GNDVDDIO

GND

VDDIO_P

GND

GND

GND

VDDIO_P

GND

GND

VDDIO_P

VDDIO_P

GND

GND

GND

GND

VDDIO_P

VDDIO_P

VDD5V

VDDIO_P

GND

GND

Y2

32.768kHz

R632.2K10%

R6510K

10%

R3510K10%

3412

SW19

Q25Si2305

U12

SP4423

1234 5

678HON

VssCOILEL2 EL1

VddCAP1CAP2

3412

SW20

R170

100K 10%

U6

SEGMENT LCD

123456789

10111213141516171819202122232425262728293031

SEG0SEG1SEG2SEG3SEG4SEG5SEG6SEG7SEG8SEG9SEG10SEG11SEG12SEG13SEG14SEG15SEG16SEG17SEG18SEG19SEG20SEG21SEG22SEG23SEG24SEG25SEG26COM3COM2COM1COM0

3412

SW22

C520.1uF

R5247K10%

R6910K10%

R15747K10%

R17147K 10%

3412

SW21

R642.2K10%

R6610K

10%

R16347K10%

C410.1uF

R18010.0K 5%

R17610.0K1%

C930.1uF

J4PJ-202A-2.0mmPower Jack

1

2

C92180pF

U12

HT1621 - LCD Controller

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748SEG7

SEG6SEG5SEG4SEG3SEG2SEG1SEG0CSRDWRDATAVSSOSCOOSCIVLCDVDDIRQBZBZCOM0COM1COM2COM3 SEG31

SEG30SEG29SEG28SEG27SEG26SEG25SEG24SEG23SEG22SEG21SEG20SEG19SEG18SEG17SEG16SEG15SEG14SEG13SEG12SEG11SEG10

SEG9SEG8

U3

FLASHMP3

123456789

101112131415161718192021222324 25

2627282930313233343536373839404142434445464748NC

NCNCNCNCSER/BRECENCNCVCCVSSNCNCCLEALEWEWPNCNCNCNCNC VSS

I/O0I/O8I/O1I/O9I/O2

I/O10I/O3

I/O11NCNCNC

VCCPRE

NCI/O4

I/O12I/O5

I/O13I/O6

I/O14I/O7

I/O15VSS

J2

HEADER 7X2

1 23 45 67 89 1011 1213 14

L7


J3EL Lamp

12

R1795.1K 5%

R6710K

10%

R16947K 10%

R7010K10%

R1772.0K 5%

3412

SW23

R51 10K10%

L1710mH, 32 ohm

Q24MMBT3904

U10

EEPROM-I2C-8Pin

1234 5

678A0

A1A2Vss SDA

SCLWPVdd

R6810K

10%

C400.1uF

R5047K10%

R18130.0K 5%

R9747K10%

C5122pF

D13

10BQ0151 AmpSchottky

C5022pF

J1

headphone

1234

R1783.01K 5%

C980.1uF

stmp3500 reference sch revb

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