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STMicroelectronics

« Trends in high speed, low power Analog to Digital converters »

Laurent Dugoujon Data-Converters Design Mgr.

LECC2002 9-13 September 2002, Colmar-France

Outline

Introduction/Generalities ADC challenges ST ADC products Power Optimisation Design views ADC Trends Conclusion

STMicroelectronics

Introduction/Generalities

DEFINITIONS


Analog to Digital Converter(ADC)

ANALOGINPUT

D0

D3

D2

D1DIGITALOUTPUT

Ex:4 bits A/D converter.

t

analoginput

SamplingClock signal

TSA04XX

0000

1111

outputbinarycodes

reconstructedsignal

t

010010111…

1

11

16 possible output codes

ADC

Full scale amplitude

LSB=Full scale/2N

62mV for 1V/4bits


ADC MAIN PARAMETERS ADC functionality parameters:

– Number of output bits– Sampling frequency noted FS

– Number of channels

ADC performance parameters:– Static parameters: DNL, INL– Dynamic parameters: SNR, SINAD, ENOB, Analog input

bandwidth.– Power consumption, Area, Package

STMicroelectronics

GeneralitiesADC Market, Applications


ADC Market

Source:WSTS

ADC, DAC, SWITCHES & MUX

Regions US 42% Europe 22% Japan 18% A/P 16%

Year 2000– 1.8B$ total value – 646Mu total volume


High Energy PhysicsElectronic chain

Detector

ADCPADataProcessor

DAQDCS

Sensor Signal formating Events acquisitionStorageControlAnalysis…


Hi-volumes & Hi-tech Applications

Consumer Audio

Industrial Control

Consumer Video

RF/Military

Sampling Frequency

Nbr. bits

HEP

HEP Detectorsrequirements

10

10MHz

+ low Power+ no. channels

AP

Astro-Physics

Telecom

STMicroelectronics

ADC Challenge

ACCURACY and SPEED?


Speed-Accuracy coupling

Fundamental relation (Heisenberg):

h/2.LSBR

Applied to A/D Converter:

R=50 Ohms, 2N.LSB = 1Volt, h=6.626 10-34

2N.Fsamp <= 3.44 1015

ex: 12 bits/840Gsamples/s

Or 18bits/10Gsamples/s

T/2

LSB/2

Vin

Time


Real signals world

How many Gigabit/s on a wire ?

Today commercial 10Gbit/s with ECL levels

Power, EMI, Integrity loss, Package parasitics,.. Are the limiting factors against higher rates !


Clock accuracy problems

Generation of Clock signal:

Clock signal is usually the fastest signal of the acquisition system and determines the sampling instants:

signal

clock

jitter


Low-jitter Clock generation

Clock jitter:It characterizes the Quality of the time reference,

often expressed in ps pk-to-pk or rms.

Available generator technologies:

RC + Logic Xtal, VCXO Sp. Plls Jitter 100-1000ps 10-100ps 0.5-10psCost ~0.1$ ~1$ ~10$


Clock Quality vs ADC specs

Aperture time and Clock jitter for a Nbit ADC sampling an Analog signal of FIN frequency must be less than:

1/(PI x FIN x 2(N+1) )In order not to add degradation in the achieved Signal/Noise

Ratio.

Example: 10 bit conversion of 10MHz input needs less than 16ps jitter. (good quality Xtal oscillator is OK)

12bit of same 10MHz input needs 4ps max jitter !


Accuracy/speed

24

6810

1412

16182022

010K 100K 1M 10M 100M 1G 10G 100G

Heisenberg

1ps jitter

Effect. bits

Samplerate S/s


Sampling rate trend summary

Today best system clock jitter is 1ps Corresponding to 12bit resolution of 40MHz input

signal

Prototypes ADCs reach 0.5ps aperture time (8bit/1.3GHz)

Going beyond 12bit-40MHz will require sub-ps jitter clock generator preferably integrated to the ADC chip for noise, power and cost reductions.


Resolution of real conversion systems is limited by the « noise floor » resulting from differents noise sources: thermal noise, transistors intrinsic noise, …

Input-referred noise can be expressed as:

<vn2> = 4 kTReqFs/2

This should be less than Quantization noise that is:Q2/12, Q=Full scale/2N

Then :

N < Log2{Vfs2/(6kTReqFs)}1/2 – 1Given a 2Volts full scale and 1000ohms Req, it gives 19bit sampling at 100Ksps (or 16bit at 10Msps)

Resolution Problems

RnoiseEquiv.

NoiselessADC

Req

Vin


Accuracy/speed

24

6810

1412

16182022

010K 100K 1M 10M 100M 1G 10G 100G

Heisenberg1Kohm thermal

1ps jitter

Effect. bits

Samplerate S/s


High-speed ADCs ST products & services

TSA0801: 8-bit, single-Channel, 40Msps, 40mW




TSA1203: 12-bit, dual-Channel, 40Msps, 230mW

TSA1204: 12-bit, dual-Channel, 20Msps, 120mW

TSA1005: 10-bits, dual Channel, 40 Msps, 200mW

2.5V supply voltage

TQFP48

+ Evaluation boards, Applications notes, support, IP integration, consulting…


ST ADCs Accuracy/speed

24

6810

1412

16182022

010K 100K 1M 10M 100M 1G 10G 100G

Heisenberg1Kohm thermal

1ps jitter

Effect. bits

Samplerate S/s

products

prototypes


Power optimisation

MeritFig.=2ENOB x Fs / Power ( x 10-11 )

TSA10019.7b, 25Msps35mW

MF=5.9

Closestcompetitor

MF=3.2


MF=8.3

Closestcompetitor

MF=4.2


MF=5.6

Closestcompetitor

MF=4.7

TSA1203 (dual)10.5b, 40Msps230mW

MF=5

Closestcompetitor

MF=2

Closest competitor

MF=1.2


MF=2.4

ADCs Vsupply=2.5V

Competitors Vsupply= 5V or 3.3V…


Designarchitectures

1E+4 1E+5 1E+6 1E+7 1E+8 1E+9

Sampling Frequency (Fs) (Hz)

5

10

15

20

25

30

Res

olu

tio

n (

n)

Sigma Delta Dual

Slope

Audio

SensorsInstrumentation

Successive Approximation Pipelined

Folded

High SpeedBasestation

InstrumentationIF sampling

Flash

Radars,RF


Very High Speed ADC (8bits/2Gsps)

Interleaved SAR ADCs

SA ADC 1

SA ADC 24

SA ADC 13

SA ADC 12

VIN 8

8

8

8M

UX

1

2:1

8M

UX

1

2:1

8

CO

MP

DAC

S/H

Die: 4mm2, IP: 0.45mm224 // unitary SAR ADC

0.18m CMOS


Pipelined ADCs

S/H

2bit 2bit

x2Vi-1 Vi

Digital correction

Output bits

1 pipeline stage


Folded-cascode Amplifier

pol

inpinm

opom

vcp

vcn

VDD

GND

Vtp=Vtn=0.7V

2.5V / 0.25m CMOS

G=90dBTHD=-86dBBW3dB=100MHz


CERN Alice-TPC ALTRO chip


7.7 mm

8.3 mm

Data Memory1K x 40

Pedestal Memory1K x 10

ProcessingLogic

3.8 mm

12 mm

14.1 mm

TQFP 176

24mm

CERN ALTRO chip: Layout and Package

Process STM HCMOS-7 (0.25 µ)Area 64 mm2

Dimensions 7.70 × 8.35 mm2

Transistors 6 MillionEmbedded Memory 800-KbitNo. ADCs 16Supply Voltage 2.5VPower Consumption 260mW @ 10 MSPSPackage TQFP-176


CERN ALTRO ADC results

MAX sampling rate in the TPC BW at PASA outputTPC requirement: ENOB > 9

2.5

k

k

k

k


0

2

4

6

8

10

12

1 10 100 1000

Rpol (k)

bits

0

20

40

60

80

100

120

mW

90 k

12 mW

9.7

ADC Operating Point

Effective Number of Bits

Power Consumption per Channel

ADC Power Consumption

20 k

30 mW

MPW values

Engineering Run values

Measured Analogue Power Consumption: 80 mA

(st.dev = 1.12 mA)

12.5 mW / channel

Optimised ADC power in ALTRO


CERN ALTRO spectrum analysis

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 1 2 3 4 5

f (MHz)

dB

c

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 1 2 3 4 5

f (MHz)

dB

c

Without Readout Clock With Readout Clock

HD2 HD3

HD2HD3

RDOclock

HD4HD4


INPUT SIGNAL AFTER 1st BASELINE CORRECTION

AFTER TAIL CANCELLATION AFTER 2nd BASELINE CORRECTION

ALTRO chip: Digital Processor Performance


ADC Trends Resolution-SpeedParalelism to exploit technology intrinsic speed of successive

generations technology (X2 every 2years)Intensification of integrated Digital Post-processing Number of channelsLower core sizes and power will allow higher integration Associated FunctionsInternal Clock re-generation will appear, Built-In-Self-Test,… PowerNew low-voltage cells/architectures for 1V technology on the

way… PackagesParasitics and size reduction associated to better dissipation


Conclusions

ADCs are used in many applications HEP is not so specific in terms of need Application Environment can degrades ADC perf. High Merit-figure ADC design needs large efforts Multi-ADCs integration is a powerfull path Digital integration is the same natural path We will use Moore’s law to buy resolution.speed

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