stm in the small: trading generality for performance in ......stm overheads •book-keeping done in...
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STM in the Small: Trading Generality for Performance in Software Transactional Memory Aleksandar Dragojević
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Our motivation
• Concurrent data structures
• Hash-tables, skip-lists
– In-memory database indices2
– Key-value stores
[2] Larson et al. “High-performance concurrency control mechanisms for main-memory databases” VLDB Dec. 2011
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Software Transactional Memory
• Simplifies data structures
– Ensures correct implementations
• Enables use of complex data structures
– More complex than when using CAS directly
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What is STM performance like?
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What is STM performance like?
Graph from: Cascaval et al. “Software transactional memory: why is it only a research toy” ACMQ September 2008
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What is STM performance like?
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What is STM performance like?
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What is STM performance like?
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What is STM performance like?
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What is STM performance like?
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CAS
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What is STM performance like?
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CAS
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SpecTM: Specialized STM for Concurrent Data Structures
Ease of programming easy hard
Perf
orm
ance
fa
st
slo
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STM
CAS
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SpecTM: Specialized STM for Concurrent Data Structures
easy hard
Perf
orm
ance
fa
st
slo
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SpecTM
Ease of programming
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CAS
STM
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This talk
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71%
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78%
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This talk
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CAS
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
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STM overheads
• Book-keeping done in software
• Memory accesses become STM calls
• Significant overheads3
– With a single thread 50% overheads
– Requires 4 threads to outperform sequential code in 75% of cases
[3] Dragojević et al. “Why STM Can Be more than a Research Toy” CACM Apr. 2011
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STM API
void StartTx();
void CommitTx();
word_t ReadWord(word_t *addr);
void WriteWord(word_t *addr, word_t val);
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STM read
map(addr)
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STM read
map(addr)
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
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STM read
map(addr)
check RaW
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
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STM read
map(addr)
check RaW
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
[orec idx]
write-set
address-value
orecs
index
… …
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STM read
map(addr)
check RaW
o1 == o2 && !locked
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set read orec
read val
read orec
address-value
orecs
… …
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index
[orec idx]
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STM read (cont’d)
log read
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STM read (cont’d)
log read head curr
count=2
read-set
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STM read (cont’d)
log read head curr
count=3
read-set
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STM read (cont’d)
log read
orec <= validts
head curr
count=3
read-set
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STM read (cont’d)
log read
return val
orec <= validts
head curr
count=3
read-set
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STM read (cont’d)
log read
validate
return val abort
valid
orec <= validts
head curr
count=3
read-set
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STM read (cont’d)
log read
validate
return val abort
valid
orec <= validts
head curr
count=3 read-set
read-set
…
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STM read fast-path
• Significantly more expensive than CPU read instructions
– >10 instructions
• Writes have comparable costs
– Incurs a compare-and-swap at commit time
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
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Short transactions
• Short read-write transactions
• Short read-only transactions
• Single-access transactions
– Read, Write, CAS
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Short read-write transactions
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word_t TxRWRead_1(word_t *addr_1);
word_t TxRWRead_2(word_t *addr_2);
word_t TxRWRead_3(word_t *addr_3);
...
void TxRWCommit_1(word_t val);
void TxRWCommit_2(word_t v1, word_t v2);
void TxRWCommit_3(word_t v1,
word_t v2,
word_t v3);
...
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Short read-write transactions
word_t TxRWRead_1(word_t *addr_1);
word_t TxRWRead_2(word_t *addr_2);
word_t TxRWRead_3(word_t *addr_3);
...
void TxRWCommit_1(word_t val);
void TxRWCommit_2(word_t v1, word_t v2);
void TxRWCommit_3(word_t v1,
word_t v2,
word_t v3);
...
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word_t TxRWRead_1(word_t *addr_1);
word_t TxRWRead_2(word_t *addr_2);
word_t TxRWRead_3(word_t *addr_3);
...
void TxRWCommit_1(word_t val);
void TxRWCommit_2(word_t v1, word_t v2);
void TxRWCommit_3(word_t v1,
word_t v2,
word_t v3);
...
Short read-write transactions
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word_t TxRWRead_1(word_t *addr_1);
word_t TxRWRead_2(word_t *addr_2);
word_t TxRWRead_3(word_t *addr_3);
...
void TxRWCommit_1(word_t val);
void TxRWCommit_2(word_t v1, word_t v2);
void TxRWCommit_3(word_t v1,
word_t v2,
word_t v3);
...
Short read-write transactions
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
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Short transaction optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
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Short transaction optimizations (cont’d)
log read
validate
return val abort
valid
orec <= validts
head curr
count=3 read-set
read-set
…
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Short transaction optimizations (cont’d)
log read
validate
return val abort
valid
orec <= validts
head curr
count=3 read-set
read-set
…
merged with write-set
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static
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Short transaction optimizations (cont’d)
log read
validate
return val abort
valid
orec <= validts
head curr
count=3 read-set
read-set
…
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merged with write-set
static
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Using short transactions
Tx
With “traditional” transactions the whole operation is a single transaction
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Using short transactions
Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
Split operation into a sequence of short transactions
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Using short transactions
Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
“Glue” them together using techniques similar to lock-free algorithms (e.g. pointer marking)
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Using short transactions
Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
“Glue” them together using techniques similar to lock-free algorithms (e.g. pointer marking)
Is this simpler than using CAS directly?
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Using short transactions
Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
“Glue” them together using techniques similar to lock-free algorithms (e.g. pointer marking)
Is this simpler than using CAS directly? Yes: transactions eliminate tricky races
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Mix short and ordinary transactions
Tx1 Tx2 Tx3 Tx4 Tx5 Tx6
Tx
Implement corner cases using ordinary transactions
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Example
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Short read-write transaction to mark the node and unlink it
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CAS
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There might be a race at each of these steps
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We need to make sure other operations clean-up for us
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All interactions between operations have to be handled correctly
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E.g. removal of an element that is still being added to the list
CAS
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
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“Traditional” STM data layout
O1
O2
O3
O4
…
…
W1
W2
W3
W4
application data
…
…
…
orecs
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“Traditional” STM data layout
O1
O2
O3
O4
…
…
W1
W2
W3
W4
application data
…
…
…
General False conflicts Cache misses
orecs
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Collocate data and meta-data
W1
O1
W3
O3
…
…
…
W2
O2
W4
O4
Simplify mapping No false conflicts Same cache line
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Collocated meta-data optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
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Collocated meta-data optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
simplified mapping
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Collocated meta-data optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
simplified mapping
better cache locality
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Pure value-based validation
W1
W2
W3
W4
…
…
… Restrict values Restrict access patterns Single-word operations
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Value-based optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
simplified mapping
better cache locality
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Value-based optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
simplified mapping
better cache locality
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Value-based optimizations
address
orec table
0 0 c 1 2 a b 0
…
…
[c1a2aa]
[c1a2ab]
[c1a2ac]
…
…
write-set
address-value
orecs
… …
static
write-set
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index
[orec idx]
map(addr)
check RaW
read orec
read val
read orec
o1 == o2 && !locked
CAS (from write)
simplified mapping
better cache locality
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API changes
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API changes
word_t ReadWord(TVar *addr);
void WriteWord(TVar *addr, word_t val);
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word_t TVarToWord(TVar addr);
TVar WordToTVar(word_t val);
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API changes
word_t ReadWord(TVar *addr);
void WriteWord(TVar *addr, word_t val);
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Transactions access TVar, not word_t
word_t TVarToWord(TVar addr);
TVar WordToTVar(word_t val);
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API changes
89
Transactions access TVar, not word_t
Calls to update TVar non-transactionally
word_t ReadWord(TVar *addr);
void WriteWord(TVar *addr, word_t val);
word_t TVarToWord(TVar addr);
TVar WordToTVar(word_t val);
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Pure value-based short read-write
read val
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Pure value-based short read-write
!locked
91
read val
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Pure value-based short read-write
CAS
!locked
92
read val
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Pure value-based short read-write
abort
!locked
93
read val
CAS
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Pure value-based short read-write
log
abort
success
!locked
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read val
CAS
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Pure value-based short read-write
write-set
abort
!locked
95
static
read val
log
success
CAS
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Pure value-based short read-write
return val
abort
!locked
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read val
static
write-set
log
success
CAS
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Pure value-based short read-write
return val
abort
!locked
97
read val
static
write-set
log
success
CAS
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STM vs. SpecTM
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STM SpecTM
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Overview
• STM overheads
• SpecTM
– Short-transaction API
– Collocating data and meta-data
– In-word meta-data
• Evaluation
99
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Evaluation
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STM
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CAS
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Evaluation
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Evaluation
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Evaluation
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Conclusions
• Trade generality for performance in SpecTM
– Restrict STM API
– Control data layout
• STM-based data structures perform as well as the ones built directly from CAS
• Do we need SpecTM with upcoming Intel TSX?
– Best-effort limited-size transactions
107
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SpecTM: Specialized STM for Concurrent Data Structures
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