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STC5272 Synchronous Clock for SETS

Data Sheet

Description

The STC5272 is a single chip solution for the timingsource in SDH, SONET network elements. The deviceis fully compliant with ITU-T G.813, and TelcordiaGR1244, and GR253.

The STC5272 accepts 4 reference inputs and generates4 independent synchronized output clocks. Referenceinput frequencies are automatically detected, and inputsare individually monitored of the frequency offset. Activereference may be manually selected via register control.All reference switches are hitless. Synchronized outputsmay be programmed for a wide variety of SONET andSDH frequencies.

Each chip includes a DPLL (Digital Phase-LockedLoop), which may operate in the Freerun, Synchronized,and Holover mode. This operation mode selection ismade by a register control. Beyond the operation modeslection, a standard SPI serial bus interface providesadvanced access to the STC5272’s comprehensive, yetsimple to use internal control and status registers.

The device operates with an external OCXO or TCXO asits MCLK at 20MHz.

The STC5272 may be field upgraded with an optionalexternal EEPROM or via the bus interface.

Data Sheet #: TM108 of 3Preliminary © Copyright the Connor-Winfield Corp. All Rights Reserv

Functional SpecificationFeatures- Suitable for SDH SETS, SONET Stratum 3, 4E, 4

and SMC- Complies with ITU-T G.813, Telcordia GR1244 and

GR253

- Accepts 4 individual clock reference inputs- Reference clock inputs are automatically frequency

detected; each is monitored of the frequency offset- Supports manual reference selection (via register

control)- 4 synchronized output clocks- Hit-less reference switching- Phase rebuild on re-lock and reference switches- Loop bandwidth is programmable, from 100mHz to

103Hz- Supports SPI bus interface for advance control- Field upgrade capability- IEEE 1149.1 JTAG boundary scan- Available in TQFP100 package

Figure 1: Functional Block Diagram

4

OCXOTCXO

Serial BusInterface

Control & StatusRegisters

IEEE 1194.1JTAG

DigitalPhase

Clock

Detector Filter

STC5272Reference Clk

LVPECL 77.76MHz(CLK0)

8kHz(CLK2)

19.44/38.88/77.76MHz(CLK1)

Synthesizer

64 kHz1.544 MHz2.048 MHz19.44 MHz38.88 MHz77.76 MHz

8 kHz

25 MHz50 MHz

6.48 MHz8.192 MHz

16.384 MHz

20MHz

125 MHz Frequency Offset Monitor

1.544/3.088/6.176/12.352/24.704MHz2.048/4.096/8.192/16.384/32.768MHz (CLK3)

4 Rev: P1 Date: March 31, 2009ed Specifications subject to change without notice


Data Sheet

Table of ContentsSTC5272 Pin Diagram (Top View) .................................................................................................................... 4STC5272 Pin Description .................................................................................................................................. 5Absolute Maximum Ratings ............................................................................................................................... 7Operating Conditions and Electrical Characteristics .......................................................................................... 8Register Map ..................................................................................................................................................... 9General Description ......................................................................................................................................... 11Detailed Description ......................................................................................................................................... 12

Chip Master Clock Input ........................................................................................................................... 12Operating Mode General Description ...................................................................................................... 12Operating Mode Details ........................................................................................................................... 12

Freerun Mode ................................................................................................................................... 12Holdover Mode ................................................................................................................................. 12Synchronized Mode ......................................................................................................................... 12

Operating Mode Transition Details .......................................................................................................... 13History Accumulation Details ................................................................................................................... 13Phase-Locked Loop Status Details .......................................................................................................... 13Reference Input Monitoring ...................................................................................................................... 14Reference Selection ................................................................................................................................. 14Output Clocks .......................................................................................................................................... 14Event Interrupts ........................................................................................................................................ 14Configuration Data Load and Field Upgradability .................................................................................... 15

Configuration Pins ............................................................................................................................ 15ROM Mode ....................................................................................................................................... 15Bus Mode ......................................................................................................................................... 15EEPROM Mode ................................................................................................................................ 16

Processor Interface Descriptions ..................................................................................................................... 18Serial Bus Timing ............................................................................................................................. 18

Register Descriptions and Operation ............................................................................................................... 20General Register Operation ..................................................................................................................... 20

Multibyte register reads .................................................................................................................... 20Multibyte register writes ................................................................................................................... 20Clearing bits in the Interrupt Status Register .................................................................................... 20

Noise Transfer Functions ................................................................................................................................. 30Application Notes ............................................................................................................................................. 31

General .................................................................................................................................................... 31Power and Ground ........................................................................................................................... 31Mechanical Specifications ................................................................................................................ 32

Order Information ............................................................................................................................................. 32

Data Sheet #: TM108 of 34 Rev: P1 Date: March 31, 2009Preliminary © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice


Data Sheet
Table of Figures
Figure 1: Functional Block Diagram ................................................................................................................. 1Figure 2: Output Clocks.................................................................................................................................. 14Figure 3: Clock output Phase Alignment ........................................................................................................ 14Figure 4: EEPROM Configuration .................................................................................................................. 17Figure 5: Serial Bus Timing, Read access ..................................................................................................... 18Figure 6: Serial Bus Timing, Write access...................................................................................................... 18Figure 7: Noise Transfer Functions ................................................................................................................ 30Figure 8: Power and Ground .......................................................................................................................... 31



Data Sheet
STC5272 Pin Diagram (Top View)
Note: Pins labeled “Test Pin” must be grounded.

26

76

51

Vss

21

3456789

10111213141516171819202122232425

27 3029 3432 363128 3533 37 38 39 40 41 42 43 44 45 46 47 48 49 50

525354555657585960616263646566676869707172737475

7778798081828384858687909192939495969798 888999100

Vss

VssVss

Vss

Vss

EE

P_S

OV

dd18 NC

NC

NC

Test

_Pin

SP

I_S

DI

SPI_SDONC

NCNC

NC

NCVss

NC

AVss

CLK

0_N

AVdd

18

Vdd

33V

ssTD

O

AVss

RE

SE

T

EV

EN

T_IN

TRE

EP

_CS

EE

P_S

I

NC

SP

I_C

S

Vss

Vss

Ref1

Vdd33Ref3

NC

NC

Vdd18Vdd33

Vdd33NCVssCLK3

PN

C

LM0

Vss

TRS

T

CLK

0_P

TCK

TMS

TDI

Vdd

18C

LK1

Vss

NC

Vdd

33C

LK2

Vss

NC

PNCNC

MC

LK

Ref2

Ref4

VssVdd33

NC

Vss

NC

Vdd

33

EE

P_S

CK

NC

SP

I_S

CK

STC5272Connor-Winfield

Vdd

18AVdd18

Vss

LM1

Vdd18

Test_Pin

Vss

Vdd18

Vss

Vss

Vdd

18 Vss

Vss

Vdd

33

Vdd

18

Vdd18

Vss

Vdd33

NC

Vdd18

Vss

Vdd

33

Vss



Data Sheet
STC5272 Pin DescriptionAll I/O is LVCMOS, except for CLK0, which is LVPECL.
Table 1: Pin Description

Pin Name Pin # I/O Description

Vdd33 6,22,31, 44,59,61, 69,80,87,97

3.3V power input

Vdd18 9,18,27, 38,47,53,60,65,84,92

1.8V power input

Vss 3,10,12, 13,14,15,16,17,19,20,21,23,25,26,29,35,41,56,64,67,71,78,82,88,95

Digital ground

AVdd18 1, 76 1.8V analog power input

AVss 75, 100 Analog ground

TRST 94 I JTAG boundary scan reset, active low

TCK 93 I JTAG boundary scan clock

TMS 91 I JTAG boundary scan mode selection

TDI 90 I JTAG boundary scan data input

TDO 89 O JTAG boundary scan data output

RESET 30 I Active low to reset the chip

MCLK 99 I Master clock input, 20 MHz

SPI_CS 45 I SPI bus chip select (CS)

SPI_SCK 46 I SPI bus clock input (SCLK)

SPI_SDI 50 I SPI bus data input (SDI)

SPI_SDO 51 O SPI bus data output (SDO)

EEP_SO 37 I/O Optional external EEPROM SO

EEP_SI 36 I/O Optional external EEPROM SI

EEP_SCK 34 I/O Optional external EEPROM SCK

EEP_CS 33 I/O Optional external EEPROM CS

EVENT_INTR 32 O Event interrupt

REF1 2 I Reference input 1





Data Sheet

Note 1: CLK0 is LVPECL


CLK0_P 85 O1 77.76MHz LVPECL output

CLK0_N 86 O1 77.76 MHz LVPECL output

CLK1 83 O 19.44/38.88/51.84/77.76MHz

CLK2 79 O 8kHz

CLK3 72 O 2.048/4.096/8.192/16.384/32.768MHz

LM0 96 I Hardware and firmware configuration data mode pin 0

LM1 7 I Hardware and firmware configuration data mode pin 1

NC 24,28,39,40,42,43,48,52,54,55,57,58,62,63,66.68,70,74,77,81,

No connection. Pins are recommended to be tied to ground

PNC 73,98 No connection. Pins can be left open, floating, tied up, or grounded

Test_Pin 11,49 I Test pins, must be grounded for normal operation

Table 1: Pin Description

Pin Name Pin # I/O Description



Data Sheet
Absolute Maximum Ratings
Note 2: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devicesshould not be operated outside the Recommended Operating Conditions.

Table 2: Absolute Maximum Ratings

Symbol Parameter Min. Max Units Notes

Vdd33 Logic power supply voltage, 3.3V -0.5 4.5 volts 2

Vdd18 Logic power supply voltage, 1.8V -0.5 2.5 volts 2

AVdd18 Analog power supply voltage, 1.8V -0.5 2.5 volts 2

VIN Logic input voltage -0.5 5.5 volts 2

TSTG Storage Temperature -65 150 �C 2



Data Sheet
Operating Conditions and Electrical Characteristics
Note 3: LVCMOS 3.3 compatibleNote 4: 50 ohms termination to 1.3 (= Vdd33 - 2.0) volts

Table 3: Recommended Operating Conditions and Electrical Characteristics

Symbol Parameter Min. Nominal Max. Units Notes

Vdd33 3.3V digital power supply voltage 3.0 3.3 3.6 Volts

Vdd18 1.8V digital power supply voltage 1.65 1.8 1.95 Volts

AVdd18 1.8V analog power supply voltage 1.65 1.8 1.95 Volts

CIN Input capacitance 8 pF

TRIP Input reference signal positive pulse width 10 ns

TRIN Input reference signal negative pulse width 10 ns

TJ Operational Junction Temperature 125 �C

TA Operating Ambient Temperature Range (Commercial) 0 70 �C

TA Operating Ambient Temperature Range (Industrial) -40 85 �C

Icc (Vcc) 3.3V digital supply current TBD mA

Icc (AVcc) 3.3V analog supply current TBD mA

Pd Device power dissipation TBD W

VIH (3.3V)

LVC

MO

S

High level input voltage 2.0 5.5 Volts 3

VIL (3.3V) Low level input voltage -0.3 0.8 Volts 3

VOH (3.3V) High level output voltage (IOH = -12mA) 2.4 Volts 3

VOL (3.3V) Low level output voltage (IOL =12mA) 0.4 Volts 3

VT Threshold point 1.45 1.58 1.74 Volts 3

IL Input Leakage Current -10 10 uA 3

Voh

LVP

EC

L

Output voltage high Vdd33 - 1.11

Vdd33 - 0.67

Volts 4

Vol Output voltage low Vdd33 - 2.0

Vdd33 - 1.4

Volts 4

Vod Output differential voltage 0.8 2.66 Volts 4



Data Sheet
Register Map
Table 4: Register Map

Addr Reg Name Bits Type Description

0x00 Chip_ID 15-0 R Chip ID, 0x52720x02 Chip_Rev 7-0 R Chip revision number0x03 Chip_Sub_Rev 7-0 R Chip sub-revision number0x0e Freerun_Cal 10-0 R/W Freerun calibration, -102.4 ~ +102.3ppm0x10 Pullin_Range 9-0 R/W Reference pull-in range, 0 ~ 102.3ppm0x15 Ref_Selector 2-0 R/W Determines which reference data is shown in register 0x160x16 Ref_Frq_Offset 15-0 R Reference frequency and frequency offset of the reference selected

by register 0x150x18 Refs_Activity 3-0 R Reference activity0x1c Control_Mode 5-5 R/W OOP - Follow / Don’t Follow0x1d Bandwidth 4-0 R/W Loop bandwidth selection0x1f Active_Ref 3-0 R/W Selects the active reference0x20 Device_Holdover_History 31-0 R Device Holdover History relative to MCLK0x24 Long_Term_Accu_History 31-0 R Long term Accumulated History relative to MCLK0x28 Short_Term_Accu_History 31-0 R Short term Accumulated History relative to MCLK0x30 History_Ramp 6-0 R/W Bits 6-4, Long term history accumulation bandwidth: 4.9, 2.5, 1.2,

0.62, 0.31, 0.15mHzBit 3-2, Short term history accumulation bandwidth: 1.3, 0.64, 0.32, 0.16HzBits 1-0, Ramp control: none, 1, 1.5, 2ppm/s

0x37 PLL_Status 7-0 R OOP, LOL, LOS, Sync, HHA, AHR, SAP0x38 Accu_Flush 0-0 W 0: Flush/reset the history, 1:Flush/reset both the long term and the

device holdover history0x57 CLK1 3-0 R/W 19.44/38.88/77.76MHz or disable select for CLK10x59 CLK2 5-0 R/W 8kHz output 50% duty cycle or pulse width selection for CLK20x5c CLK3 3-0 R/W 2n x DS1 or 2n x E1 or disable selector for CLK30x5e Intr_Event 1-1 R/W Interrupt event0x60 Intr_Enable 1-1 R/W Interrupt enable0x65 CLK0 1-0 R/W LVPECL 77.76MHz clock enable or disable

Extra Registers if Configuration Data Mode is set as ROM_MODE0x75 ROM_Loader_Status 2-0 R Checksum status of core, hardware and firmware configuration data

Extra Registers if Configuration Data Mode is set as BUS_MODE0x70 Bus_Loader_Status 2-0 R Loading status of the hardware and firmware configuration data0x71 Bus_Loader_Data 7-0 W Data port of the bus loader of the hardware and firmware configura-

tion data0x72 Bus_Loader_Counter 13-0 R Data counter of the bus loader of the hardware and firmware config-

uration data0x75 Bus_Core_Status 0-0 R Checksum status of core configuration data

Extra Registers if Configuration Data Mode is set as EEP_MODE0x70 EEP_Loader_Checksum 0-0 R Checksum status of the EEPROM loader of the hardware and firm-

ware configuration data0x71 EEP_Controller_Mode 7, 0 R/W Mode of the EEPROM controller



Data Sheet
0x72 EEP_Controller_Cmd 1-0 W Command for the EEPROM controller0x73 EEP_Controller_Page 7-0 W Page number for the EEPROM controller0x74 EEP_Controller_Data 7-0 R/W Data port of the EEPROM controller0x75 EEP_Core_Status 0-0 R Checksum status of core configuration data


Data Sheet
General DescriptionThe STC5272 is an integrated single chip solution for the synchronous clock in SDH (SETS), SONET networkelements. Its highly integrated design implements all of the necessary reference selection, monitoring, filtering,synthesis, and control functions. An external OCXO or TCXO at 20 MHz completes a system level solution (seeFunctional Block Diagram, Figure 1).
The STC5272 has one timing generator. The timing generator may be in either external-timing or self-timing mode.In external timing mode, the timing generator may select one of the external reference inputs as its active referenceof its Digital Phase-Locked Loop (DPLL). In self-timing mode, the clock outputs are synthesized from the localoscillator (the external TCXO/OCXO). STC5272 provides 4 snchronized clock outputs.

The timing generator can operate in Freerun, Synchronized, and Holdover mode. In synchronized mode, theDPLL phase-locks to the selected external reference. Phase lock will be in arbitrary phase offset between the activereference and clock outputs. DPLL’s loop bandwidth may be programmed to vary the DPLL’s filtering function.Conversely, both freerun and holdover modes are self-timing. In freerun mode, the clock outputs are synthesizedand calibrated from the local oscillator. In holdover mode, the clock outputs are synthesized with a given frequencyoffset. This frequency offset is a frequency history previously accumulated by STC5272. The stability of freerun andholdover is simply determined by the local oscillator.

Reference frequencies are auto-detected. Each reference input is continuously monitored frequency offset. Theauto-detected frequency and the measured frequency offset may provide the user valuable information.

Active reference may be selected manually under application control.

All reference switches are performed in a hitless manner. When references are switched, the device will minimizephase transitions in the output clocks. A frequency ramp control feature also ensures smooth frequency transitionswhile switch reference, or even into/out of both freerun and holdover mode.

A serial bus interface (SPI) provides application access to the STC5272’s internal control and status registers.

The STC5272 also supports Field Upgradability. The initialization of registers and PLL detailed behavior is definedby the hardware and firmware configuration data. This configuration data may be provided by the internal ROM orexternally. When externally sourced, the data may be pumped either over the bus interface, or from an optionalexternal EEPROM.



Data Sheet

Detailed Description

Chip Master Clock InputThe device operates with an external 20MHz OCXO orTCXO as its master clock, connected to the MCLK input,pin 99.

The freerun clock may be digitally calibrated from MCLKby writing an offset to the Freerun_Cal register, from -102.4 to +102.3 ppm, in 0.1ppm steps, in two’scomplement form. (See Register Descriptions sectionfor details regarding register references in this section.)

Operating Mode General DescriptionThe STC5272 has one timing generator, which includesa DPLL.

In general, a timing generator may be either in external-timing or self-timing mode. In external-timing mode, atiming generator may select any of the externalreferences as the active reference for the DPLL. Theactive reference can be one of the 4 input referenceclocks. In self-timing mode, the clock outputs aresynthesized from the MCLK (the external TCXO/OCXO)(with a programmable calibration) or a given frequencyoffset.

The timing generators may operate in Freerun,Synchronized, or Holdover mode. Operating insynchronized mode is in external-timing mode. Insynchronized mode, the phase relationship between thereference and the clock outputs is arbitrary. The usermay program the DPLL’s loop bandwidth to vary thenoise transfer function.

Holdover mode is analogous to the freerun mode. Bothare self-timing modes. The clock outputs aresynthesized from the local oscillator with aprogrammable calibration or a given frequency offset.The stability in these two modes is simply determined bythe local oscillator.

Operating Mode DetailsThe STC5272 is designed to provide phase andfrequency hit-less clock outputs to downstream devices,even through operating mode change and referenceswitches. Both the phase and frequency transitions willbe continuous. The transfer into the self-timing mode(freerun and holdover) is designed to be frequencybump-less. A frequency ramp control limits the rate offrequency change through operating mode change andreference switches. An application programmablemaximum slew rate of 1, 1.5, and 2 ppm/second (or noslew rate limit) may be enforced, as written to the

Data Sheet #: TM108 PagePreliminary © Copyright the Connor-Winfield Corp. All Rights Rese

Functional SpecificationHistory_Ramp register.

Freerun Mode All the clock outputs (CLK 0-3) are synthesized and maybe calibrated from MCLK and have the stability of theexternal TCXO/OCXO. The calibration offset may beprogrammed by the application by writing to theFreerun_Cal register. The calibration offset may beprogrammed from -102.4 to +102.3 ppm, in 0.1ppmsteps.

Holdover Mode Holdover Mode is analogous to the freerun mode. All theclock outputs (CLK 0-3) are synthesized from MCLKwith a frequency offset. The clock outputs will have thestability of the external TCXO/OCXO. The frequencyoffset is from a device accumulated holdover history.The accumulated holdover history may be forcelyflushed to rebuild by writing to Accu_Flush register. Theuser may read the short-term history of the currentclock outputs from the Short_Term_Accu_Historyregister.

Synchronized ModeIn synchronized mode, the DPLL phase-locks and tracksto the selected input reference. The timing generator isin external-timing mode. All the clock outputs (CLK 0-3)are all synchronized to the selected input reference.

In this mode, the DPLL is running in arbitrary mode,which means the phase relationship between the activeinput reference and the clock outputs is fixed(synchronized) but not aligned (zero). To lock on anexternal reference, the DPLL will initially operate infrequency locking mode in pull-in process. When thefrequency of the reference is determined and locked, theclock output phase relationship relative to the referenceinput will be rebuild and locked. (It should be noted thatoutput-to-reference phase alignment is meaningful onlyin those cases where the output frequency andreference are the same or related by an integer ratio.)

After a reference switch or re-lock (due to loss of signalor loss of lock), the DPLL will be in a pull-in processinitially. The pull-in process will be frequency-lockingonly until the frequencies of the reference and outputmeet. Then, the clock output phase relationship relativeto the reference input will be rebuild and locked.The pull-in process may prologue to 60+ seconds in normalsituation.

The DPLL’s loop bandwidth is programmable from100mHz to 103Hz by writing to the Bandwidth registers.

There are two special cases of the synchronized mode:

12 of 34 Rev: P1 Date: March 31, 2009rved Specifications subject to change without notice


Data Sheet

(a) Zombie mode - If the signal of the active reference islost, the DPLL output is generated according to theshort-term history; (b) Out of Pull-in Range mode - Ifthe selected reference exceeds the pull-in range asprogrammed by the application, the DPLL output may beprogrammed to stay at the pull-in range limit, or to followthe reference. This is programmed by writing the “OOP”bit of the Control_Mode registers, specifying whether tofollow or not follow a reference that has exceeded thepull-in range. The frequency offset is relative to thedigitally calibrated freerun clock.

Operating Mode Transition DetailsThe operating mode is selected by writing to theActive_Ref registers. This forces the timing generatorinto freerun, synchronized, or holdover mode.

On all transitions into freerun or back from freerun, anapplication programmable maximum slew rate of 1, 1.5,or 2 ppm/second (or no slew rate limit) is applied, aswritten to the registers.

History Accumulation DetailsThree holdover histories are built and maintained by thetiming generator: the short-term history, the long-termhistory, and the device holdover history.

1. Short-Term HistoryThis is a short-term average frequency of the DPLL’sclock outputs. The weighted 3rd order low-pass filtermay be programmed for a -3dB point of 1.3Hz, 0.64 Hz,0.32Hz, and 0.16Hz by writing to the History_Rampregister. The short-term history is used in the zombiesub-mode. This history may be read from theShort_Term_Accu_History register.

2. Long-Term HistoryThis is a long-term average frequency of the DPLL’sclock outputs, while synchronized to a selected externalreference. The weighted 3rd order low-pass filter may beprogrammed for a -3dB point of 4.9 mHz, 2.5 mHz, 1.2mHz, 0.62 mHz, 0.31 mHz, and 0.15 mHz by writing tothe History_Ramp register. Internally, an express modeis used after reset by applying a lower time constant forthe first 15 minutes to speed up the history accumulationprocess. This accumulation process will be resetwhenever the selected reference is switched or loss oflock occurs. The accumulation process will then resumeafter synchronization is achieved, as indicated by theassertion of “SYNC” bit in the PLL_Status register.Additionally, the application may flush/rebuild this long-term history by writing either “0” or “1” to theAccu_Flush register. The long-term history may be readfrom the Long_Term_Accu_History register.


Functional Specification3. Device Holdover HistoryWhen the timing generator enters the holdover mode,the history determines all the clcok outputs CLK(0-3).The initial history will begin and be continuously updatedby the long-term history after the completion of the 15minute express mode time. Updating will stop if the longterm history accumulation process is reset as a result ofa reference switch or loss of lock. Thus, the previousholdover history will persist until a new long term historyis accumulated following a reference switch or theattendant re-building of the long term history after loss oflock. The “AHR” bit of the PLL_Status registers is set to“1” during updating, but will revert to “0” when updatingstops. Additionally, the application may reset thisholdover history by writing “1” to the Accu_Flushregister.

Phase-Locked Loop Status DetailsThe PLL_Status register contains the detailed status ofthe DPLLs, including the signal activity of the activereference, the synchronization status, and theavailability of the holdover histories.

Applications can program the Intr_Enable register toenable/disable the interrupts (pin EVENT_INTR) triggedby the status change of the PLL_Status registers.

SYNC bitIn external-timing mode (synchronized mode), this bitindicates the achievement of synchronization. This bitwill not be asserted in self-timing mode (e.g., freerunand holdover modes).

LOS bitIn external-timing mode (synchronized mode), this bitindicates the loss of signal on the active reference. Thisbit will not be asserted in self-timing mode (e.g., freerunand holdover modes).

LOL bitIn external-timing mode (synchronized mode), the DPLLwill set this bit if it fails to achieve or maintain lock to theactive reference. This bit will not be asserted in self-timing mode (e.g., freerun and holdover modes). This bitis also not complementary to the SYNC bit. Both bits willnot be asserted when the DPLL is in the pull-in process.

SAP bitThis bit when set indicates that the DPLL’s output clockshave stopped following the active reference because thefrequency offset of the active reference is out of pull-inrange. The application can write to the Control_Moderegister to program whether the DPLL shall follow theactive reference outside of the specified pull-in range.

AHR bit



Data Sheet

This bit indicates whether the device holdover history istracking on the current active reference (updating by thelong-term history).

HHA bitThis bit indicates the availability of the holdover history.

Reference Input MonitoringThe STC5272 accepts 4 external reference inputs at8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz,38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz,16.384MHz, 25MHz, 50MHz, 62.5MHz, or 125MHz.Input frequencies are detected automatically.

Each input is monitored for frequency offset. Themeasured frequency offset of each reference is relativeto the digitally calibrated freerun clock.

Both the auto detected frequency and the measuredfrequency offset of each reference may be read byselecting the reference in the Ref_Selector register andthen reading the frequency from registerRef_Frq_Offset.

The frequency offset of each reference is relative to thedigitally calibrated freerun clock may be read byselecting the reference in the Ref_Selector register andthen reading the offset value from registerRef_Frq_Offset.

Reference SelectionThe timing generator is operated in manual inputreference selection mode. The reference is selected bywriting to the Active_Ref register.

Output ClocksThe clock output section includes 2 timing synthesizers,an APLL, and 2 dividers, and generates 4 synchronizedclocks, as shown in figure 2.

Figure 2: Output Clocks

DPLL Clk APLL

Divider

Divider

Clk1

Clk0

Clk32nxDS1, 2nxE1

LVPECL 77.76MHz

19.44/38.88/77.76/ 51.84/MHz

8 kHz

Synthesizer

Clk Synthesizer

Clk2


Functional SpecificationThe first synthesizer drives an analog PLL andgenerates two output clocks:

• CLK0: 77.76MHz (LVPECL), selected ordisabled by writing the CLK0 register.

• CLK1: Programmable at 19.44MHz, 38.88MHz,77.76 MHz, and disabled, by writing to theCLK1 register.

• CLK2: 8kHz, 50% duty cycle or programmablepulse width, and may be disabled by writing tothe CLK2 register.

Another synthesizer generates the :

• CLK3: Programmable at 1.544MHz, 3.088MHz,6.176MHz, 12.352MHz, 24.704MHz,2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz,32.768MHz by writing to the CLK3 register.

When a clock output is disabled, the pin is tri-stated.

Figure 3: Clock output Phase Alignment

Note that CLK1,2 and 3 are phase aligned as shown inFigure 3. CLK0 is synchronized but not phase alignedwith CLK1,2 and 3.

Event InterruptsThe STC5272 may indicate the occurrence of a numberof events as an interrupt to the host processor via pinEVENT_INTR (pin 32). The user may enable or disableindividual interrupt by writing to register Intr_Enable.The associated events which trigged interrupts will belatched. After detected the assert of interrupt pin, theapplication may read the list of latched events fromregister Intr_Event. The user may clear the events bywriting a ‘1’ to the bit position of each related event. Thepin EVENT_INTR returns to normal when all events arecleared.

Currently there is only one event that can trigger aninterrupt: the status change of the DPLL of the timinggenerator. The event may be enabled and disabledindividually.

8kHz

19.44MHz

2nx DS1/E1



Data Sheet
Configuration Data Load and Field UpgradabilityFollowing any device reset, either via power-up oroperation of the reset pin, the device needs to be loadedwith the configuration data. The loading procedure hastwo stages. First stage is to load core configuration data(programmed with factory default). Register 0x75 mayprovide the status of the core configuration data loadingprocess. Second stage is to load hardware and firmwareconfiguration data. This data defines the initialization of registersand DPLL detailed behavior. The hardware and firmwareconfiguration data may be loaded from the internal ROM(programmed by factory), an optional externalEEPROM, or from the bus interface. If the load failed,the application must rest the device and repeat the loadprocess. Loading external hardware and firmwareconfiguration data via optional external EEPROM or thebus interface may provide the feature of fieldUpgradability to applications. Hardware and firmwareconfiguration data loading method depends on theconfiguration pins.
Configuration PinsThe configuration pins LM0 and LM1 determine thehardware and firmware configuration data loadingmethod following a power-up or reset. LM0 and LM1also allow the application to switch among the controllerof ROM, EERPOM and Bus interface in run time. Thecombination of configuration pins is shown in Table 5.

Note that the configuration pins should not both be high,as device damage may occur.

ROM ModeWhen the ROM mode is configured via LM0 and LM1following a power-up or reset, the hardware andfirmware configuration data may be loaded automaticallyfrom the internal ROM. The data is programmed bymanufacturer. Hardware and firmware configuration dataloading via the ROM mode is accomplished usingregister ROM_Loader_Status. The register provides the

Table 5: Configuration Pins

LM1 LM0 Description

0 0 ROM mode

0 1 Bus mode

1 0 EEPROM mode

1 1 Reserved - do not use


Functional Specificationstatus of the core, hardware and firmware configurationdata loading process.

Bus ModeWhen the Bus Mode is configured via LM0 and LM1following a power-up or reset, the hardware andfirmware configuration data may be loaded from the SPIbus interface using the registers Bus_Loader_Status,Bus_Loader_Data, Bus_Loader_Counter andBus_Core_Status. The hardware and firmwareconfiguration data is provided to the customer per anagreement with the manufacturer. The application shallfollow the procedure below:

/* --- *The data array data[10496] contains the hardware/firmware configuration data, starting from index 0. * --- */

Procedure Bus_Loadbegin

Label_Repeat:

- busy wait until bit “bus ready” in the Bus_Loader_Status is equal to ‘1’;

- for i: = 0 to 10,495 step 1begin

- write data[i] to register Bus_Loader_Data;- busy wait until bit “bus ready” in register

Bus_Loader_Status is equal to ‘1’;end

- if bit “load complete” in register Bus_Loader_Status is equal to ‘0’begin

/* loading failed */- reset this device by asserting pin RESET;- goto Label_Repeat;

end

- if bit “checksum status” in register Bus_Loader_Status is equal to ‘0’begin

/* loading failed */- reset this device by asserting pin RESET;- goto Label_Repeat;

end

/* Bus Loading Success */

end of procedure Bus Load

The device will assert the “load complete” bit in registerBus_Loader_Status after the application writes 10,496bytes into register Bus_Loader_Data.

After the bit “load complete” is asserted, the applicationshall read and check the bit “checksum status” of



Data Sheet

register Bus_Load_Status. “1” indicates the checksumpassed; “0” indicates a load failure. CRC-16 checksumencryption is used in the hardware/firmwareconfiguration data to assure the detection oftransmission error.

Before the “bus ready” bit is asserted or after the “loadcomplete” bit in register Bus_Loader_Status isasserted, all writes to the Bus_Loader_Data registerwill be ignored.

At any time in the process, the application may read thenumber of bytes that have been written from theBus_Loader_Counter register.

The register Bus_Core_Status provides the status ofcore configuration data loading process.

EEPROM ModeWhen EEPROM mode is configured via the LM0, LM1pins, the device may be prepared for two processes:hardware and firmware configuration data load process,EEPROM upload and read back process. For thehardware and firmware configuration data load process,the data may be loaded from the optional externalEEPROM by the device’s built-in EEPROM loaderautomatically following a power-up or reset. Thehardware and firmware configuration data is provided tothe customer per an agreement with the manufacturer.Read and check the register EEP_CHECKSUM whichindicates the CRC-16 checksum status of the loadingprocess. The register EEP_Core_Status indicates thechecksum status of the core configuration data loadingprocess.

For upload and read back process, the application mayread and write the hardware and firmware configurationdata from/to the external EEPROM via device’sEEPROM controller using the registerEEP_Controller_Mode, EEP_Controller_Cmd,EEP_Controller_Page, and EEP_Controller_Data.

After uploading the complete hardware and firmwareconfiguration data to the external EEPROM, theapplication should read it back and perform thecomparison to ensure no transmission errors havehappened. The uploading and read back procedures areas follow:

Procedure EEP_Uploadbegin

/* --- *The data array data[10496] contains the hardware/firmware configuration data, starting from index 0.

* --- */

- busy wait until bit “ready” in register EEP_Controller_Mode is equal to ‘1’;


Functional Specification- write 0x01 to register EEP_Controller_Mode;

/* turn on the write feature */- write 0x00 to register EEP_Controller_Cmd;

/* reset the page FIFO buffer */- for i = 0 to 163 step 1

begin- write (i) to register EEP_Controller_Page;

/* set the page index */- for j = 0 to 63 step 1

begin- write data[64*i+j] to register

EEP_Controller_Data;end

- write 0x01 to register EEP_Controller_Cmd;/* issue the write command */


end- write 0x00 to register EEP_Controller_Mode;

/* turn off the write feature */end of procedure EEP_Write

Procedure EEP_Readbackbegin


- for i = 0 to 163 step 1begin

- write (i) to register EEP_Controller_Page;/* set the page index */

- write 0x02 to register EEP_Controller_Cmd;/* issue the read command */


- for j = 0 to 63 step 1begin

- read and copy the value of register EEP_Controller_Data into data[64*i+j];

endend

/* --- *The data array data[10496] is then carrying the hard-ware/firmware configuration data, starting from index 0.

* --- */end of procedure EEP_Read

Table 6 is the recommended list of compatible EEPROMfor applications and Figure 10 is the EEPROMinterfaces:

Table 6: Compatible EEPROM

Manufacturer Part Number

ATMEL AT25128A



Data Sheet

Figure 4: EEPROM Configuration

STC5272EEPROM

CS

SCK

SI

SO

EEP_SCK

EEP_SI

EEP_SO

EEP_CS

ATMELAT25128A

Both WP and HOLD have to be tied high



Data Sheet
Processor Interface DescriptionsThe STC5272 supports the serial SPI bus interface. The description of the SPI bus’s interface timing is following:
The SPI interface bus mode uses the BUS_CS, BUS_ALE, BUS_RDB, and BUS_RDY pins, corresponding to CS,SCLK, SDI, and SDO respectively, with timing as shown in figures 5 and 6:

Serial Bus Timing

Figure 5: Serial Bus Timing, Read access

Figure 6: Serial Bus Timing, Write access

A0

CS

SCLK

SDI

1 2 3 4

A6 A5 A4 A3 A2 A1

5 6 7 8 13 14 15 169 10 11 12

1

D7

LSBMSB

SDOMSB LSB

tDRDY

tCH tCL

tCS

tDs tDh

tCSMIN

tDHLD

D6 D5 D4 D3 D2 D1 D0

tCSHLDtCSTRI

CS

SCLK

SDI

tDs

1 2 3 4

A6 A5 A4 A3 A2 A1 A0

5 6 7 8 13 14 15 169 10 11 12

0

tDh

LSBMSB

tCH tCL

tCS

D7 D6 D5 D4 D3 D2 D1 D0LSBMSB

tCSMINtCSHLD



Data Sheet

Table 7: Serial Bus Timing

Symbol Description Min Max Unit

tCS CS low to SCLK high 10 ns

tCH SCLK high time 25 ns

tCL SCLK low time 25 ns

tDs Data setup time 10 ns

tDh Data hold time 10 ns

tDRDY Data ready 7 ns

tDHLD Data hold 3 ns

tCSHLD Chip select hold 30 ns

tCSTRI Chip select to data tri-state 5 ns

tCSMIN Minimum delay between successive accesses 50 ns



Data Sheet
Register Descriptions and Operation
General Register OperationThe STC5272 device has 1, 2, 3, and 4 byte registers. One-byte registers are read and written directly. Multiple -byteregisters must be read and written in a specific manner and order, as follows:

Multibyte register readsA multibyte register read must commence with a read of the least significant byte first. This triggers a transfer of theremaining byte(s) to a holding register, ensuring that the remaining data will not change with the continuing operationof the device. The remaining byte(s) must be read consecutively with no intervening read/writes from/to otherregisters.

Multibyte register writesA multibyte register write must commence with a write to the least significant byte first. Subsequent writes to theremaining byte(s) must be performed in ascending byte order, consecutively, with no intervening read/writes from/toother registers, but with no timing restrictions. Multibyte register writes are temporarily stored in a holding register,and are transferred to the target register when the most significant byte is written.

Clearing bits in the Interrupt Status RegisterInterrupt event register (Intr_Event) bits are cleared by writing a “1” to the bit position to be cleared. Interrupt bitpositions to be left as is are written with a “0”.

Chip_ID, 0x00 (R)

Chip_Rev, 0x02 (R)

Chip_Sub_Rev, 0x03 (R)

Freerun_Cal, 0x0e (R/W)

Freerun calibration, from -102.4 to +102.3 ppm, in 0.1ppm steps, two’s complement.Default value: 0

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

0x00 0x720x01 0x52


0x02 Revision Number


0x03 Sub-Revision Number


0x0e Lower 8 bits0x0f Not used Upper 3 bits



Data Sheet
Pullin_Range, 0x10 (R/W)
Reference pull-in range, from 0 to +102.3ppm, in 0.1ppm steps. Default value: 110 (range = 11.0ppm)

Ref_Selector, 0x15 (R/W)

Determines which reference data is displayed in register 0x16 and 0x17. Valid values from 1 to 4. Invalid values willnot be written to the register.Default value: 1

Ref_Frq_Offset, 0x16 (R)

Displays the frequency offset and reference frequency for the reference selected by the Ref_Selector (0x15)register. Frequency offset is from -204.7 to +204.7 ppm relative to calibrated freerun, in 0.1 ppm steps, two’scomplement. A value of -2048 indicates the reference is out of range.

The reference frequency is determined as follows (“Unknown” indicates a signal is present, but frequency isundetermined):


0x10 Lower 8 bits0x11 Not used Upper 2 bits


0x15 Not used 1~4 (0x1 ~0x4)


0x16 Lower 8 bits of frequency offset0x17 Reference frequency Upper 4 bits of frequency offset

0x17, bits 7 ~ 4 Frequency

0 No signal1 8 kHz2 64 kHz3 1.544 MHz4 2.048 MHz5 19.44 MHz6 38.88 MHz7 77.76 MHz8 6.48MHz9 8.192MHz10 16.384MHz11 25 MHz12 50 MHz13 125 MHz14 Unknown15 Reserved



Data Sheet
Refs_Activity, 0x18 (R)
Reference activity indicator, 0 = no activity, 1 = activity.

Control_Mode, 0x1c (R/W)

Mode control bits.

OOP When the selected active reference is out of the pull-in range, as specified in registerPullin_Range (0x10). OOP will determine if the reference is to be followed, 0 = Follow, 1= Don’t follow.

Default value: 0

Bandwidth, 0x1d (R/W)

Sets the loop bandwidth:

Default value: 6

Active_Ref, 0x1f (R/W)

Selects the active reference in manual reference select mode.


0x18 Not used Ref 4 Ref 3 Ref 2 Ref 1


0x1c Not used OOP: Out of Pull-in range:

0=Follow1=Don’t fol-

low

Reserved


0x1d Not used Bandwidth select

0x1d, bits 4 ~ 0 Bandwidth, Hz

0 1031 522 273 134 6.75 3.46 1.77 0.848 0.429 0.2110 0.10

31 ~ 11 Reserved


0x1f Not used Selection



Data Sheet

Default value: 0

Device_Holdover_History, 0x20 (R)

Device holdover history relative to MCLK. 2’s complement. Resolution is 0.745x10-3ppb.Default value: 0

Long_Term_Accu_History, 0x24 (R)

Long term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10- 3 ppb.

Short_Term_Accu_History, 0x28 (R)

Short term accumulated history relative to MCLK. 2’s complement. Resolution is 0.745x10-3 ppb.

History_Ramp, 0x30 (R/W)

Holdover bandwidth and ramp controls:

Bit 3 ~ Bit 0 Selection

0 Freerun1 ~ 4 Sync with Ref 1 ~ Ref 45~12 Reserved

13 Holdover14, 15 Reserved


0x20 Bits 0 - 7 of 32 bit Device Holdover History0x21 Bits 8 - 15 of 32 bit Device Holdover History0x22 Bits 16 - 23 of 32 bit Device Holdover History0x23 Bits 24 - 31 of 32 bit Device Holdover History


0x24 Bits 0 - 7 of 32 bit Long Term History0x25 Bits 8 - 15 of 32 bit Long Term History0x26 Bits 16 - 23 of 32 bit Long Term History0x27 Bits 24 - 31 of 32 bit Long Term History


0x28 Bits 0 - 7 of 32 bit Short Term History0x29 Bits 8 - 15 of 32 bit Short Term History0x2a Bits 16 - 23 of 32 bit Short Term History0x2b Bits 24 - 31 of 32 bit Short Term History


0x30 Not used Long Term History Bandwidth Short Term History Band-width

Ramp control



Data Sheet

Default value: 0x27 (1.2mHz; 0.64Hz; 2ppm/sec)

PLL_Status, 0x37 (R)

SYNC Indicates synchronization has been achievedLOS Loss of signal of the active referenceLOL Loss of lock (Failure to achieve or maintain lock)OOP Out of pull-in rangeAHR Active Holdover History ReadyHHA Holdover History AvailableSAP Indicates the output clocks have stopped following the selected reference, caused by out of pull-

in range

0x30, bits 6 ~ 4Long Term

History -3dB Bandwidth

000 4.9 mHz001 2.5 mHz010 1.2 mHz011 0.62 mHz100 0.31 mHz101 0.15 mHz

110, 111 Reserved

0x30, bits 3 ~ 2Short Term

History -3dB Bandwidth

00 1.3 Hz01 0.64 Hz10 0.32 Hz11 0.16 Hz

0x30, bits 1 ~ 0 Ramp control

00 No Control01 1.0 ppm/sec10 1.5 ppm/sec11 2.0 ppm/sec


0x37 HHA 1=Available

0=Not available

AHR 1=Ready

0=Not ready

Reserved SAP1=Stop at

pull-in range

0=Follow-ing

OOP1=Out of

pull-in range

0=In range

LOL0=No LOL

1=LOL

LOS0=No LOS

1=LOS

SYNC:0=No Sync

1=Sync

HHA AHR Holdover Status

1 1 Holdover History available: Device Holdover History tracking on the current active reference1 0 Holdover History available: Device Holdover History based on last available history0 0 Holdover History not available0 1 Not applicable



Data Sheet
Accu_Flush, 0x38 (W)
Writing to this register will perform a flush of the accumulated history. The value of bit zero determines whichhistories are flushed. Bit 0 = 0, Flush and reset long term history only; bit 0 = 1, flush/reset both long term history andthe device holdover history.

CLK1, 0x57 (R/W)

Selects or disables the CLK1 output.

Default value: 3

CLK2, 0x59 (R/W)

Selects or disables the CLK2 output. In variable pulse width, the width may be selected from 1 to 62 times the periodof the 155.52MHz output (~6.43ns to 399ns).

Default value: 63

CLK3, 0x5c (R/W)

Selects or disables the CLK3 output.


0x38 Not used HO flush


0x57 Not used CLK1 Select

0x57, bits 3 ~ 0 CLK1 output

0 Disabled1 19.44MHz2 38.88MHz3 77.76MHz

4~15 Reserved



0x59, bits 5 ~ 0 CLK3 8kHz output

0 Disabled1 ~ 62 Pulse width 1 to 62 cycles of 155.52MHz

63 50% duty cycle


0x5c Not used CLK3 Select

0x5c, bits 3 ~ 0 CLK6 output

0 Disabled1 2.048MHz2 4.096MHz3 8.192MHz4 16.384MHz5 32.768MHz



Data Sheet

Default value: 3

Intr_Event, 0x5e (R/W)

Interrupt event, 0 = no event, 1 = event occurred. The interrupt is cleared by writing “1’s” to the bit positions to becleared (See General Register Operation, Clearing bits in the Interrupt Status Register section).

Intr_Enable, 0x60 (R/W)

Interrupt disable/enable, 0 = disable, 1 = enable. Default value: 0

CLK0, 0x65 (R/W)

Selects or disables the CLK0 output. Default value: 0

6, 7, 8 Reserved9 1.544MHz10 3.088MHz11 6.176MHz12 12.352MHz13 24.704MHz

14, 15 Reserved


0x5e Reserved Event 1: DPLL status

changed

Reserved


0x60 Reserved Intr 1Enable

Reserved



0x65, bits 1 ~ 0 CLK8 output

0 Disabled1 77.76MHz2 Reserved3 Reserved

0x5c, bits 3 ~ 0 CLK6 output



Data Sheet
ROM_Core_Status, 0x75 (R)
If ROM mode has been selected with pins LM0,1, this register indicates the status of core, hardware and firmwareconfiguration data loading via internal ROM.

core configuration checksum Set to 1 when the core configuration data loading process is complete andpassed.

Hardware and configuration checksum

Bus_Loader_Status, 0x70 (R)

If bus mode has been selected with pins LM0,1, this register indicates the loader’s status.

load complete Set to 1 when the loading process is complete in the bus mode.bus ready Set to 1 when the device is ready to load data in the bus mode.checksum status Set to 1 if the hardware and firmware configuration data load is successful (CRC-16

checksum over the 10,496 bytes of hardware and firmware configuration data passes) inthe bus mode. The “checksum status” bit is valid only after the “load complete” bit hasbeen set.

Bus_Loader_Data, 0x71 (W)

If bus mode has been selected with pins LM0,1, the hardware and firmware configuration data is written to thisregister.

Bus_Loader_Counter, 0x72 (R)

If bus load data mode has been selected with pins LM0,1, this register indicates the number of bytes that have beenwritten to the Bus_Loader_Data register.


0x75 Not used Hardware and Firmware Configuration Checksum

Core Con-figuration

Checksum

Bit2 Bit1 Status

0 0 Fail0 1 Fail1 0 Fail1 1 Pass


0x70 Not used load complete

bus ready Checksum status


0x71 Data


0x72 Bits 0 -70x73 Not used Bits 8 - 13



Data Sheet

Bus_Core_Status, 0x75 (R)

If bus load data mode has been selected with pins LM0,1, this register indicates the checksum status of the coreconfiguration data loading process from the bus interface.

checksum status Set to 1 if the core configuration data loading is successful in the Bus interface mode.

EEP_Loader_Checksum, 0x70 (R)

If EEPROM mode has been selected with pins LM0,1, this register indicates the checksum status of the hardwareand firmware configuration data loading process from the external EEPROM.

checksum status Set to 1 if the hardware and firmware configuration data load is successful (ensured bythe CRC-16 checksum encryption over the 10,496 bytes of hardware and firmwareconfiguration data) in the EEPROM mode.

EEP_Controller_Mode, 0x71 (R/W)

If EEPROM mode has been selected with pins LM0,1, this register indicates the readiness of the EEPROM controllerand can be used to turn on and off the writing feature to the external EEPROM.

ready Set to 1 when the controller’s page FIFO buffer is ready to be used for further read and write datafrom/to the external EEPROM.

writable This bit is used to enable/disable the writing feature to the external EEPROM. Write ‘1’ to this bitmakes the EEROM writable. Writing ‘0’ to this bit makes the EEPROM not writable.

EEP_Controller_Cmd, 0x72 (W)

If EEPROM mode has been selected with pins LM0,1, this register is used to issue the reset, write, and readcommands to the EEPROM controller.

command=0 reset and clear the page FIFO buffer.command=1 trigger the EEPROM controller to write the contents in the 64-byte page FIFO buffer to a page of

the external EEPROM.command=2 trigger the EEPROM controller to read and copy the 64-byte content of a page of the external

EEPROM into the page FIFO buffer.command=3 reserved


0x75 Not used Checksum status




0x71 ready Not used writable


0x72 Not used command



Data Sheet

EEP_Controller_Page, 0x73 (W)

If EEPROM mode has been selected with pins LM0,1, this register is used to specify the index of the page of theEEPROM for the subsequent read or write command. Valid values are from 0 to 163.

EEP_Controller_Data, 0x74 (R/W)

If EEPROM mode has been selected with pins LM0,1, the data is read and written from/to the page FIFO buffer viathis register.

EEP_Core_Status, 0x75 (R)

If EEPROM mode has been selected with pins LM0,1, this register indicates the checksum status of the coreconfiguration data loading process from optional external EEPROM.

checksum status Set to 1 if the core configuration data load is successful in the EEPROM mode.


0x73 Page number


0x74 data





Data Sheet
Noise Transfer FunctionsThe user may write to Bandwidth registers to set the loop bandwidth of the DPLL of the timing generator. The noisetransfer function of the DPLL filter is determined by the loop bandwidth. Figure 7 shows the noise transfer functionsas the loop bandwidths vary from 100mHz to 103Hz.
Figure 7: Noise Transfer Functions

-80 dB

-60 dB

-40 dB

-20 dB

0 dB

20 dB

10 mHz 100 mHz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz

Tran

sfer

Atte

nuat

ion

Noise Frequency

0.10 Hz0.21 Hz0.42 Hz0.84 Hz

1.7 Hz3.4 Hz6.7 Hz13 Hz27 Hz52 Hz

103 Hz

-3dB



Data Sheet
Application NotesThis section describes typical application use of the STC5272 device. The General section applies to all applicationvariations.
General

Power and GroundWell-planned noise-minimizing power and ground are essential to achieving the best performance of the device. Thedevice requires 3.3 and 1.8V digital power and 1.8V analog power input. All digital I/O is at 3.3V, LVTTL compatible,except for the two pairs of LVPECL clock outputs.

It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power inputleads, subject to board space and layout constraints. On power-up, it is desirable to have the 3.3V either lead or becoincident with, but not lag the application of both 1.8V supplies.

Digital ground should be provided by as continuous a ground plane as possible. A separated analog ground plane isrecommended.

Note: Un-used reference inputs must be grounded.

Figure 8: Power and Ground

The external 20MHz TCXO/OCXO master oscillator is connected to the MCLK pin.

3.3V digitalpowerinputs

1.8V digitalpowerinputs

Digital ground

Analog ground1.8V analogpowerinputs

STC5272

Vdd33 (10)

Vdd18 (10)

AVdd18 (2)

(x) Number of pins

MCLK OCXO/TCXO

Vss (16) AVss (2)

20MHz



Data Sheet
Mechanical Specifications
Controlling dimensions are in millimeters

Order InformationPart Number DescriptionSTC5272 Commercial Temperature Range ModelSTC5272-I Industrial Temperature Range Model

7 °3.5 °0°7 °3.5 °0°θ0.0030.08Y

0.039 REF1.00 REFL10.0300.0240.0180.750.600.45L

0.551 BSC14.00 BSCE10.551 BSC14.00 BSCD10.020 BSC0.50 BSCe0.630 BSC16.00 BSCE0.630 BSC16.00 BSCD

0.0080.0040.200.09c0.0110.0090.0070.270.220.17b0.0410.0390.0371.051.000.95A20.0060.0020.150.05A10.0471.20AMAXNOMMINMAXNOMMIN

InchMillimeterSymbol

7 °3.5 °0°7 °3.5 °0°θ0.0030.08Y

0.039 REF1.00 REFL10.0300.0240.0180.750.600.45L

0.551 BSC14.00 BSCE10.551 BSC14.00 BSCD10.020 BSC0.50 BSCe0.630 BSC16.00 BSCE0.630 BSC16.00 BSCD

0.0080.0040.200.09c0.0110.0090.0070.270.220.17b0.0410.0390.0371.051.000.95A20.0060.0020.150.05A10.0471.20AMAXNOMMINMAXNOMMIN

InchMillimeterSymbol



Data Sheet

Data Sheet #: TM108 ofPreliminary © Copyright the Connor-Winfield Corp. All Rights Reserv

Functional Specification

Information furnished by Connor-Winfield is believed to be accurate and reliable. However, no responsibility is assumed by Connor-Winfield for its use, nor for any infringements of patents or other rights of third parties that my result from its use. Specifications subject tochange without notice.

For more information, contact: 2111 Comprehensive DRAurora, IL. 60505, USA630-851-4722630-851-5040 FAXwww.conwin.com


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