status and trends of sige bicmos...

Communications R&D Center

Status and Trends of SiGe BiCMOS Technology

David HarameManager SiGe BiCMOS Simulation,

Modeling, Design Automation,Verification, and Release Department

IBM Communications Research and Development Center Essex Junction, VT

GGF 12/8/99


Outline - IntroductionIntroduction

IBM Technology overview

Total Technology Support

SiGe BiCMOS production circuits

Summary

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Graded Base SiGe HBTNarrow bandgap baseBase "quasi-electric field"Small ∆∆∆∆EG at E-B jct.

Ger

man

ium

C

onte

nt

Emitter Base Collector

Ener

gy(e

v)

N P N

SiSiGe

EF

EV

EC

e-e-

e-

High emitter dopingMedium base dopingPolysilicon emitter

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Key Technology Enablers and Issues

Key Enablers: CMOS integration + PassivesHigh Level Integration differentiates BiCMOS from III-V

CMOS in BiCMOS must exactly match “base” CMOSHIgh Q passives differentiate technology providers

Monolithic circuits require high Q passives

Key issues: Process IntegrationConflicting CMOS / HBT thermal budget requirements

Addressed with integration methodologyShrinking CMOS interconnects non-optimal for RF

Specialized metal systems for RF

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Outline - SiGe TechnologyIntroduction

Technology overviewSiGe HBT BiCMOS integrationSiGe HBT DifferentiatorsPassives

Total Technology Support


Summary

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"Base-after-gate" integration flowMajor thermal cycles prior to base depositionLow thermal-cycle HBT module

CMOS / Common Bipolar/Analog

Ref: S. St Onge, BCTM 99

Shallow Trench Isolation

FET Well ImplantsDual Gate Oxide & Gate FormationLDD Implants & AnnealsSpacer Formation

Silicide & ContactsStandard 2 to 6 Metal Layers

– Includes MIM Capacitor

Subcollector & n-EPI Deep Trench Isolation

Collector Plug Implant

Thick Metal Add-On Module

pFET S/D/G Implants nFET S/D/G Implants

HBT Module: Bipolar Window Open SiGe Epi Base Growth Extrinsic Base, Collector & Emitter Formation

Source/Drain and Emitter Anneal

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Process Flow for 0.25µµµµm SiGe BiCMOS

Poly Resistor

N-N+NWellN+

P-

NN+

P-

N+

P-

N- EpiN+

P-

N+N- Epi

Single Crystal UHV/CVD SiGe Window Poly protect

P-

N-N+N

N+

P-

NWELL

N+

Gate Poly

P-

N-N+N

N+

P-

NWELL

N+

P P

NPN PFET

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Poly ResistorNPN PFET

P-

N-N+N

N+

P-

NWELL

N+

P P

P-

N-N+NN+

P-

NWELLN+

P P

P-

N-N+N

N+

P-

NWELL

N+

P P

P P

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Poly ResistorNPN PFET

P-

N-N+N

N+

P-

NWELL

N+

P P

P P

P-

N-N+N

N+

P-

NWELL

N+

P P

P P

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SiGe HBT Cross Section (0.25µµµµm SiGe BiCMOS)

Deep Trench

Extrinsic Base

Collector

EmitterIntrinsic

Base

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fT comparison0.18µµµµm generation performance increase 2.5XVertical + lateral scaling gives higher performance at lower power

1E-5 0.0001 0.001 0.01 0.1Ic (Amps)

0

20

40

60

80

100

120

140

fT, G

Hz

0.5 µm generation1µm2

VCB = 1V0.18um generation1µm2

0.16µm2

0.25 µm generation0.35µm2

Lateralscaling

Verticalscaling

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HBT MAG and h21120 GHz fT

100 GHz fMAX (fit to MAG @ 40-70GHz)

h212

MAG

0.18x4 junction areaVBE=0.90V VCB=1V

10 100

Freq (GHz)

1

10

100

MAG

, h21

**2

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SiGe Bipolar/BiCMOS Roadmap3 generations of SiGe Production

Production

1997 1998 1999 2000 2001 2002 2003

Main Technology Derivative High Speed NPN Ft / BVceo

High Breakdown NPN Ft / BVceo

Bipolar

CMOS

0.5um3.3v

0.5um3.3, 5v

0.25um2.5v

0.18um1.8v

0.13um1.2v

45 GHz / 3.3v25 GHz / 5.5v

19971996

50 GHz / 3.3v19 GHz / 7.8v

5B0

5MR20 GHz / 9.5v

50 GHz / 3.3v29 GHz / 5.5v

5HP

6HP50 GHz / 3.3v29 GHz / 5.5v

7HP120 GHz / 2.0v50 GHz / 3.3v25 GHz / 5.5v

> 150 GHz / 2.0Vtbd / tbd 8T

BiCMOS Production

5HE Bipolar Production

Base During Gate Integration

Base After Gate Integration

End Of Life

BiCMOS Production

BiCMOS Production

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Technology Summary Table

Lithography µµµµm 0.5 0.25 0.18NPN fT (Hi BV/HP) GHz 28/45 28/45 30/120

NPN fMAX GHz 50/60 50/60 50/100NPN BVCEO V 5.5/3.3 5.5/3.3 5.0/2.1NPN Density relative 1x 1.15x 1.52xEmitter Width µµµµm 0.42 0.3 0.18NFMIN dB 0.8 0.8 0.4CMOS Supply V 3.3 2.5/ 3.3 1.8/ 3.3

CMOS Pwr mW/MHz/gt 0.3 0.1 0.03CMOS Gate Delay ps 90 50 33CMOS Density relative 1x 4x 7.5x

BEOL M1 Current Density

relative 1x 0.94x 1.5x

BEOL Metal Material Al Al Cu

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Differentiator: Performance - fT Range Epi base and SiGe grading enable 150-200Ghz. HBT performance.Generations of HBT's are selected by market needs, eg.BVceo.fT & fmax alone provide no information as to technology advancement.

Johnson Limit

Peak F (Ghz)0 20 40 60 80 100 120

0

2

4

6

8

10

BVc

eo(V

olts

)

t

Gen 5&6 HBT

SiGe HBT'sSi BJT's

Gen 7 HBT

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Differentiator: Linearity

Linearity efficiency = OIP3 / PDC

Technology OIP3 (dBm) PDC (mW) Linearity Eff.

IBM SiGe HBT 25 16.2 19.5GaAs HBT 25 29.1 11GaAs HEMT 23 20 10GaAs MESFET 20 60 2Si BJT (max. linearity) 27 46 11

Si BJT (max. fT) 22 40 4

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Differentiator: Noise Performance Excellent NFMIN

Noise improvements into 0.18µµµµm generation

0 1 2 3 4 5 6 7 8 9 10 110.00.20.40.60.81.01.21.41.61.82.02.22.42.62.8

Present (34 µm2, 3 mA, 3 V) Next (56 µm2, 10.7 mA, 2 V)

Min

. Noi

se F

igur

e (d

B)

Frequency (GHz)

0

2

4

6

8

10

12

14

16

18

20

solid lines = model

Associated Gain (dB)

Ref: D.R.Greenberg IMS 2000GGF 12/8/99


Passives DevelopmentTwo Modes of Development

New Technology DevelopmentEnhancements on existing technologies

Device Type Issues SolutionsInductors Spiral Q Thick dielectric module

Thick metal10-20 Ω-cm substrates

Capacitors Poly-Ins-Single xtalPoly-Ins-PolyMetal-Ins-Metal

DensityReliability (Voltage rating)

VCCQ

Optimize processesOffer variety

Resistors PolysiliconBEOL thin filmSingle-crystal diff'n

ToleranceTCRParasitic CCurrent rating

Process controlOffer varietyLayout options for low C

Varactor JunctionMOS accumulation

Tuning rangeQLinearity

Offer varietyLayout tradeoffs captured in models

Interconnect Transmission lineLocal interconnect

CMOS compat.ElectromigrationLoss

Low levels - CMOSUpper levels - thickCopper

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Metal Layer Stack Comparison0.25µµµµm BiCMOS

DTSTI

M1

MT

M2

M3

AM

0.5µµµµm BiCMOS

M1

M2

LM

DTSTI DT

LY

M1

M2

M3

M4

STI

AM

0.18µµµµm BiCMOS

"Analog" metallevels

CMOS ASIC compatiblelevels

CMOSscaling

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Typical spiral cross-section and model topology

Silicon

Inductor Spiral

Via

UnderpassSi02dielectric

height

(P-)

SPICE model

L1: spiral inductance

R1: spiral series resistance

C3: spiral to underpass +turn-to-turn capacitance

C1&C2: spiral to substratecapacitance

R2&R3: substrate resistance

C4&C5: substrate capacitance

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Thick metal/dielectric add-on module100% increase in metal thickness (2µµµµm to 4µµµµm)

75% increase in dielectric thickness (5µµµµm to 8.7µµµµm)

4µm

3µm

P- substrate (15Ω-cm)

Standardmetal

Achieves inductor Q values approaching 20

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MOM simulation of multi-turn spiral current flow

Current crowding more pronounced in multi-turn coils

Additional metal thicknessallows more "sidewall" for current flow, reducing effective resistance

Edge Current

More even distribution

Edge current

Spiral line with current crowding

Expected areaof sidewallcurrent flow

4µµµµm

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Outline - Total Technology Support

Introduction

Technology overviewTotal Technology Support

OverviewModelsDesign Automation


Future directions

Summary

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Total technology supportFoundry and internal designs supported by IBM

ModelsAccurate, scalable & statistical RF models including matching, temperature, frequency, & bias

Cadence and ADS based design environmentsTime Domain and Frequency Domaing simulation

Application support organizationsTechnical specialists for analog and CMOS ASICTraining in technology & design environment

Product engineering organizationSupports customer through manufacturing environment

First-pass design success

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IBM BiCMOS Model Methodology

Advanced Advanced Models for Models for Advanced Advanced

DesignDesign

Process Based Statistics!"Optimal Prediction of Manufacturing Line"

Scalable Models!"Optimal Design Flexibility"

Scalable Scalable Statistical Statistical

ModelModel

Physical Physical LayoutLayout

Device Scaling Device Scaling EquationsEquations

In-line In-line Electrical Electrical

DataData

Statistical Statistical Process Process

DescriptionDescription

Nominal LotNominal LotCharacterizationCharacterization

Split LotSplit LotCharacterizationCharacterization

DesignDesignRulesRules

DeviceDevicePhysicsPhysics

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Characterization Data Inputs to Final Model

Physical & Physical & ProcessProcess

Simulation Simulation DataData

Final Final ModelModel

In-LineIn-LineElectrical Electrical

DataData

Test SiteTest SiteHardwareHardware

DataData

RcW/2 XATAN

Arc Edge

Body

Ldra

wn

Leff

1E-4 1E-3 1E-2 1E-1Ic (A)

0

50

100

150

200

fT (G

Hz)

0.25x5µm2

0.5V VCB

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Important Modeling Aspects

Physics/process based models simplify development of new features or extensionsUse of industry standard models allows support for multiple vendor simulators

e.g. HSPICE, SPECTRE, HP-ADS

Model GenerationParameter extraction using near-nominal hardwar

Nominal models re-centeredSalability across range of device geometriesStatistical tolerances based on in-line data and process split lots

Model VerificationDevice /Model across bias, temperature conditionsReview parameter correlations with process splitsEnsure corner definitions maintain proper physical relationsVerify Monte Carlo analysis results against process specs Ensure Kit Integration correct

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GeneralDefine Gaussian distributions to represent process/lithography variations/some extracted parametersFirst order correlations based on physical relationships or common/shared process steps

e.g. NPN Ic and Va correlated with base pinch resistanceDevice models include localized device mis-match

Monte CarloRandom variation of all defined process distributionsModel parameters recalculated for each combination ("case")Each "case" represents one point of expected process range Gives best approximation of manufacturing process variationMost time consuming but best analysis

Corner ModelsSpecific skew of dominant parameters assumedRepresents typical "up" / "down" device performanceDefault "up" / "down" may not be valid for all bias, temperature conditions or circuit applications

Statistical Philosophy - Monte Carlo/Corners

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RF CMOS (MOSFETs) Models

Current MOSFET models:AC characterized to 50 GHzExtrinsic gate and substrate resistance elements added to BSIM3v3.2 core for improved frequency responseScalable width, length and multiple gate finger geometriesUse of the BSIM3v3 thermal and 1/f noise equationsNon-quasi-static (NQS) model, device temperature differences, and adjacent Vth mis-match f(W,L)

Future Enhancements:Migration from BSIM3 to BSIM4 modelNoise figure / large signal measurements & correlation g

Rgate Rsub Simplest Case

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Resistor Model Topology

Distributed R-C subcircuit improves accuracy at higher frequencies over single lumped R-C elementsTypical resistance model accuracy within 5% across -55C to +125C range (body and end R separate T coef)Additional parasitic diiode element included for resistor within NWELL or NS, as neededScalable width and length geometries

Rend/2 Rbody/2 Rbody/2 Rend/2

Cpar/6 2Cpar/3 Cpar/6

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Advanced SiGe HBT VBIC Models

Advanced VBIC model topology includes separate elements:

Current source for impact ionizationSelf-heating networkFixed oxide capacitances (E-B, C-B)Extrinsic series resistancesParasitic PNP to substrate

Separate impact ionization current source required to properly model high-breakdown type NPN

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SiGe HBT Future Model Growth

Evaluation / extraction for other advanced BJT models:HiCUM (Schroter)MEXTRAM (Phillips)

Extend model and measurement correlation for:Noise figure data and Large signal data

GGF 12/8/99


SiGe Design Methodology

Frequency Domain SimulationAgilent ADSHarmonic Balance/HF SpiceCircuit Envelope

Schematic CaptureCadence Composer

LayoutParameterized Cells (PCells)Virtuoso-XL/DLE LayoutEditor

IDF

Res

imul

atio

n

IBM SiGe Design KitScaleable VBIC HBT ModelPFET, NFETSpiral inductors, Stacked MIM, Resistors, Varactor, ESD

Parasitic ExtractionCoeffgen, PRE, LPESequence Columbus RF (1Q01)Cadence RCX (2Q01)

Time Domain SimulationCadence Analog ArtistSpectre Direct

Design VerificationLVS/DRCHierarchical Checking DIVA & Assura

Res

imul

atio

n

GDS II

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Outline - SiGe Production Circuits

Introduction

Technology overview

Total Technology SupportSiGe BiCMOS production circuits

WirelessWiredStorage

Future directions

Summary

GGF 12/8/99


Tri-Band LNA/Image Reject Mixer Product

Tri-band GSM Image Reject Mixer with LNA Features

900MHz, 1.8GHz and 1.9GHz operationLow power with sleep mode and single supply (3.0V) operationFully integrated differential design including LNA for improved performanceIntegrated IF phase shifter/combiner and LO quadrature generator which simplifies useFlexible design with external low sensitivity matchingCMOS compatible band select logic control

RCpoly-phasefilter

IF+

IF-

DCSLO

GSMLO

LOQuadGen.

4:1RF+

4:1

RF-

RF-

RF+

Band Control

Band sel.

Bias Control

VccLNA

VccMix

Sleep

LO LO LO LO

Frequency (MHz) 935-960 MHz (GSM)1.8-2.0GHz (DCS/PCS)

Cascade Gain 22 dB

NF 3.5 dBRF Input VSWR < 2:1

LO Input VSWR < 2:1

IIP3 -14 dBmLO Power 200mVp ECLSupply Voltage 2.7-3.3 V

Supply Current < 30 mA

Port Isolation (min) 20 dB (all ports)

Image Rejection > 30 dB

IF Frequency 400 MHzIF Load Impedance 600 Ω

Package TSSOP24Temperature -40 to +85C

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IBM Measured "Typical"

GaAs Data Sheet

”Typical”AMPSPOUT 31 32Gain 27 26PAE 53% 50%NADCPOUT 29.5 30Gain 29.5 28PAE 48 45ACPR -26 -28ALT -48 -48Ruggedness 10:1@5V 10:1@5

V

TDMA Power AmpCompetitive specs to GaAsIntegration potential, lower cost

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2.5 GHz Frequency SynthesizerExample of non scaling in Analog & RF chips

Wirebond pad counts and passives do not scale with reducing lithography dimensions

Pad count detemining peripheral chip dimensionsLarge passives dominate space consumption

40% of space determined by two capacitorsLarge area inductors

3.8x2.0 mm2M. Soyuer, IBMYorktown Hts., NY

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Intersil Wireless LAN ChipsetCommercial product

2.4 GHz (ISM Band)3 SiGe BICMOS + 1 CMOS chipsReplaces 8 chips (some GaAs) + board components

> 2 Million chip sets shipped

Block Diagram, I/Q Modulator/ Demodulator

CAL ENABLE

IF DETECTOR OUTRECEIVE AGCBASEBAND RXI

BASEBAND RXQ

OFFSETCAL

I

Q

Σ

TRANSMIT IF AGCBASEBAND TXQBASEBAND TXI

IF_IN

IF_OUT

0/ 90 PLL MODULE IF 2X LO/VCO INCHARGE PUMP OUT3-WIRE INTERFACEREF IN

O

Specification HFA 3726 (old) HFA 3783 (new-SiGe)Pin Count 80 48Radio Bit Rate 2 MBit/ s 11 MBit/ sReceiver Icc 70 mA 36 mA2x Loc. Osc. Freq. 20-800 MHz 160-1200 MHzGain Control Limiter Tx and Rx AGCRX Phase Balance +/- 4 degrees +/- 2 degreesTx Carrier Suppression -28 dBc max -30 dBc maxPhase detector Icc 0.8 mA 0.1 mABaseband Coupling AC DC w/ internal offset

correction

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Digital Network SwitchHighest level of HBT integration published (1997) (highest integration today > 150K - not published)

GGF 12/8/99


Production PRML Read Channel First SiGe product at 0.25µµµµm

1200 SiGe HBT's300K Gates 0.25µµµµm CMOS Logic (>1,000,000 Transistors)>75 200mm wafers/day in production at IBM Burlington

GGF 12/8/99

Alcatel 10Gbit/sec SONETτ 10 and 40 Gbps Circuits with IBM SiGe

First Experimental Multi Chip Reticle 18 x 18 mm²• All 10 Gbps circuits were first time right• The chips have been moved to production directly• The average circuit yield is > 90%

10 Gbps Clock and Data Recovery Multi Chip Module

8:1 MUX 13 Gbps5 V, 2.5 W2000 Tr.3 x 3 mm²

GGF 12/8/99


68 x 69 differential crosspoint switchNRZ data rates up to 3.2 GbpsRise/fall times of 85 picoseconds1.8 picoseconds typical RMS jitter accumulationBandwidth-to-power ratio over 30 gigabits per watt

SAN DIEGO, August 22, 2000 - Applied Micro Circuits Corp. (AMCC) [NASDAQ:AMCC], a leader in high-bandwidth silicon connectivity solutions for the world's optical networks, today announced the S2090, the industry's first very high-speed Silicon Germanium (SiGe) 68 x 69 differential crosspoint switch with full broadcast switching capability. Ideal for use in high-speed applications such as Dense Wavelength Division Multiplexing (DWDM) switching, digital video, high-speed automatic test equipment (ATE), and datacom or telecom switches, the S2090 can handle NRZ data rates up to 3.2 Gbps per channel with corresponding output rise/fall times of 85 picoseconds. Furthermore, the S2090 also demonstrates and unprecedented 1.8 picoseconds typical Root Mean Square (RMS) jitter accumulation and sports power optimization features, which can achieve typical power dissipation as low as 7 Watts.

68x69 Cross-Point SwitchAMCC Introduces Industry's First Silicon Germanium 68 x 69 Differential Crosspoint Switch with over 200 Gbps Switching Capacity

GGF 12/8/99


POS/ATM SONET MapperSingle chip OC-48c SONET/SDH Mapper with integrated serializer / deserializer, integrated clock recovery (CDR), clock synthesis (CSU)Highly integrated HBT and ASIC methodology

1.2M CMOS devices6K SiGe HBTsDie size 10.84x10.84 mm2

65 percent reduction in board real estate compared to existing solutions3.3V technology with 3.4W of typical power

GGF 12/8/99


Outline - IntroductionIntroduction

Technology overview

Total Technology Solution


Summary

GGF 12/8/99


SummarySiGe HBT BiCMOS is integrated into a wide range mainstream products today

Key differentiators for the SiGe HBThigh integration : HBT count and CMOSpower, linearity, noise

Volume products in wired, wireless, storage, test and other applications

Two generations of SiGe BiCMOS in productionHighly integrated parts with > 1.6 M FETs, 150K HBTs

Roadmap to continuous improvementsPassives and interonnect improvements are central

Models and Design Kits -> tools for circuit designersAccurate statistical models across T, Freq., BiasRobust design platforms with state of the art point tools

GGF 12/8/99

status and trends of sige bicmos...

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