static crosstalk-noise analysis

STATIC CROSSTALK-NOISEANALYSIS

For Deep Sub-Micron Digital Designs

STATIC CROSSTALK-NOISEANALYSIS

For Deep Sub-Micron Digital Designs

by

Pinhong ChenCadence Design Systems, Inc.

Desmond A. KirkpatrickIntel Corporation

Kurt KeutzerUniversity of California, Berkeley

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Contents

List of Figures

List of Tables

Preface

INTRODUCTION

Motivation

Process Trends

CMOS Circuitry

Background and Crosstalk Effects

Static Timing Analysis

Crosstalk Effects

Functional Failure

Timing Variation

Search Space Pruning

Spatial Pruning

Electrical Pruning

Temporal Pruning

Functional Pruning

Problem Complexity v.s. Accuracy

Overview

1.

1

1.1

1.2

2

2.1

2.2

2.3

2.4

3

3.1

3.2

3.3

3.4

3.5

4

xi

xv

xvii

1

1

2

3

4

4

5

6

7

8

8

9

10

11

12

13

vi STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

MILLER FACTOR COMPUTATIONFOR COUPLING DELAY

Introduction

Gate Driving and Coupling Model

Nonlinearity of Driver Model

Driver Modeling

Decoupling Approximation

Coupling Model

Bounds

Simple Iterative Approach

Convergence of the Simple Iterative Approach25

Newton-Raphson Iteration for Miller Factor

Multiple Miller Factors for Multiple CouplingNets

Slew Rate (Transition Time) Calculation

Nonzero Initial Voltage Correction

Glitch Waveform Approximation

Experimental Results

Review of Conservativism

Conclusion

CONVERGENCE OF SWITCHINGWINDOW COMPUTATION

Introduction

Background

Simple Upper and Lower Bounds for SwitchingWindows

Fixed Point Computation

Formulation

2.

1

2

2.1

2.2

3

3.1

3.1.1

3.2

3.2.1

3.3

3.4

3.5

4

4.1

5

6

7

3.

1

2

2.1

3

3.1

15

15

18

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21

21

22

22

24

26

28

30

30

31

32

33

34

37

37

39

41

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42

Contents vii

Fixed Point Iteration for Switching WindowsComputation

Multiple Convergence Points and UnstableFixed Point

Tightening Bounds

Coupling Models

Noise Calculation Model

Switching Windows Overlapping Model

Discontinuity in Discrete Models

Error Bound between Discrete and ContinuousModels

Non-Monotone Property

Convergence of Switching Windows Computation

Proof of Convergence

Computational Complexity

Convergence Rate

Least Evaluation of Coupling RC Networks

Speed-up of Convergence

Conclusion

SPEEDING-UP SWITCHINGWINDOW COMPUTATION

Introduction

Background and Definitions

Piecewise Linear Waveform

Multiple Aggressor Alignment Problem

Coupling Delay Computation in Presence of CrosstalkNoise

Algorithm

Convergence of Our Algorithm

Properties of Our Algorithm

3.2

3.3

3.4

4

4.1

4.2

4.3

4.4

4.5

5

5.1

5.2

5.3

5.4

5.5

6

4.

1

2

2.1

3

4

4.1

4.2

4.3

43

46

47

49

50

51

52

53

54

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55

57

58

59

60

60

61

61

62

64

65

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67

69

72

viii STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

Event Pruning

Scheduling Technique


Review of Conservativism

Conclusion

REFINEMENT OFSWITCHING WINDOWS

Introduction

Formulation and Algorithm

Arrival Time Uncertainty in Interconnect

Switching Window Density

Input Timing Uncertainty

Complexity

Implementation Consideration

Resolution and Truncation Errors


Consideration of Slew Rates

Property of Time Slots and Conservativism

Conclusion

FUNCTIONAL CROSSTALKANALYSIS

Introduction

Approaches and Related Work

Vector Pair Searching Algorithm

Overview

BCOP: Boolean Constrained OptimizationProblem

Constructing Circuit via SAT

4.4

4.5

5

6

7

5.

1

2

2.1

2.2

2.3

2.4

2.5

3

4

5

6

7

6.

1

2

3

3.1

3.2

3.3

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84

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85

85

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89

89

91

91

92

94

94

94

95

Contents ix

Maximum Noise under the Zero-Delay Model96

Fixed Delay Circuit Construction via SAT

Using Timed Boolean Variables

Translation of Maximum Coupling Effectsinto an Objective Function

Boolean Constrained Optimization Problem

Discrete Required Time Analysis

Structural Hashing

Coarse Quantum Time

Boolean Constraint Relaxation


Future Work

Conservativism Consideration

Conclusions

CONCLUSIONS

References

3.4

3.5

3.5.1

3.5.2

3.5.3

3.5.4

3.5.5

3.5.6

3.5.7

4

5

6

7

7.

97

98

99

100

101

101

102

102

102

104

105

106

107

109

List of Figures

Metal Wire Aspect Ratio Change over Tech-nologies

Metal Wire Aspect Ratio Change over Tech-nologies

Input-Output Transfer Curve of a CMOS Inverter

AC current injected from an aggressor

Crosstalk inducing functional failure

Crosstalk inducing timing variation

Switching window example

Noise Level Model

Temporal Relationship between Victim Netand Aggressor Nets

Complexity of Crosstalk Noise Analysis

Complexity of Crosstalk Noise Analysis

Miller Effect Circuit

Coupling Circuit

Linear Driver Model

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

2.1

2.2

2.3

2

3

4

5

6

7

8

9

11

13

13

16

18

19

xii STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

(a) Nonlinear conductance varies during sig-nal transition over time for different load-ings. (b)Nonlinear conductance vs. outputvoltage during signal transition for differ-ent loadings

Original victim waveform and varying noisedue to varying aggressor arrival times

Decoupling Approximation Circuit

(a) used to calculate the Miller factorfor the coupling delay. (b) de-noted as where accounts forthe time difference between the rise(fall)time of the victim and the aggressor.

Miller factor vs. effective capacitance, as-suming

Comparison of the number of iterations ofSimple Iterative Approach and Newton-Raphsoniteration

A case for Simple Iterative Approach totake 43 iterations to converge.

Comparison of the number of iterations forSimple Iterative Approach and Newton-RaphsonIterations with 2 coupling nets.

Comparison of the number of iterations forSimple Iterative Approach and Newton-RaphsonIterations with 4 coupling nets.

(a)Undershoot Waveform (b)Undershoot Circuit

Experiment for Undershoot Modeling

Victim delay vs. aggressor’s arrival time

Victim delay vs. aggressor’s ramp time

Example of waveform response

function to represent the overlapping

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

3.1

20

20

21

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25

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List of Figures xiii

Variables to represent delays in a couplingsubcircuit

Bounds for switching window

A circuit example for multiple convergence points

Realizable arrival time function

Multiple convergence points

Determination of the worst delta delay causedby crosstalk noise

Discontinuity in noise when using adiscrete model

Error incurred due to a discrete model

Reducing a gate delay resulting in a longerpath delay

Floating mode delay model

A decreasing portion resulting in non-convergence

Extending the aggressor’s switching win-dow to infinity

Local divergence

Min/Max Timing

Propagation/Coupled Delay

Sensitive Min/Max Windows

Maximum Delay under Coupling Effect

Sliding Noise and Envelope Waveform

Coupling/Driving Events

Transitive Fanout as an Aggressor

Function of and convergence

Convergence of and

Function of

Continuous Switching Windows

Discontinuous Switching Windows

Gate delay and interconnect delay variables

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

5.1

5.2

5.3

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xiv STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

Finer slot gets more noise violations

Signal Integrity and Delay Degradation

Characteristic Function of an AND Gate

Conjunction of Characteristic Functions

Timed Boolean Variable Example

Waveform of Example Circuit in Figure 6.8

Variable Reuse for an Inverter

Variable Reuse

5.4

6.1

6.2

6.3

6.4

6.5

6.6

6.7

86

94

95

96

98

99

101

102

List of Tables

Result for ISCAS85 Combinational Circuits

Initial values affects the number of cou-pling computations

Performance for Different Scheduling Approaches

Results for process implementa-tion of ISCAS85 combinational circuits

Slot size effect on the number of noise violations.

Comparison of continuous switching win-dow and time slot approach on the numberof noise violations.

Comparison of Maximum Noise Bound(Maximum

)

4.1

4.2

4.3

4.4

5.1

5.2

6.1

75

75

76

76

86

87

104

Preface

As the feature sizes decrease in deep sub-micron circuit designs,coupling capacitance dominates total capacitance, and crosstalknoise problems become significant and responsible for major tim-ing variations and signal integrity issues.

Timing analysis is an important method to verify that a chip canmeet performance requirements. Given a circuit network and itscomponent models, timing analysis calculates signal propagationdelay to verify whether the results can be delivered on time at theoutputs. Unlike dynamic timing analysis, static timing analysisuses a vectorless approach to analyze the network topology with-out simulation. Traditional static timing analysis ignores crosscoupling effects between wires, or approximates the coupling ca-pacitance by a 2X (Miller factor) grounded decoupled capacitanceto account for the worst case delay. This approach not only reducesdelay calculation accuracy, but can also be shown to underestimatethe delay in certain scenarios. We propose an efficient method toestimate this Miller factor so that the delay response of a decou-pled circuit model can emulate the original coupling circuit. Underthe assumptions of zero initial voltage, equal charge transfer, and

as the switching threshold voltage, an upper bound of 3Xfor maximum delay and a lower bound of -1X for minimum delayis proven.

xviii STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

Crosstalk coupling is also very sensitive to switching windows,in which signal nets can make transitions. It is the signal switchingthat causes the wire to inject extra current to its neighboring wiresand affect their signal delay or arrival times. Thus, it is impor-tant to capture the switching windows for evaluating the crosstalkeffect. However, the switching windows again depends on the sig-nal arrival times. The way to resolve this mutual dependency isthrough iterations. We will build the theoretical foundation to ana-lyze the nature of these iterations considering modeling, accuracy,and mathematical properties and also propose effective ways toconverge these iterations. A time slot approach is used to reducepessimism of crosstalk analysis.

Crosstalk is also subject to functional correlation which is simi-lar to the false path problem (i.e., the neighboring wires might notswitch all at the same time in the same direction due to logic cor-relation). To evaluate a maximum crosstalk noise, we must searchand compute the logic condition that produces the maximum peaknoise. A conservative approach assumes every net can switch at thesame time in the same direction, while the approach we propose caneliminate this false switching combination. A similar idea arises intiming analysis to eliminate false paths. However, the maximumcrosstalk problem is even more complicated due to its optimizationnature and interaction across a large set of signals.

The goal of this work is to achieve a computationally efficient,accurate, but conservative approach to crosstalk analysis for digitalcircuits.

Chapter 1

INTRODUCTION

1. MotivationThis work addresses how to analyze the digital noise effects and

their impact on static timing analysis (STA). These issues havedesign integrity impact but are typically ignored in older technolo-gies because of the high noise immunity of CMOS circuitry, andthe process technologies. However, as the feature size decreasesin the deep sub-micron (DSM) era, the aspect ratio of metal wiresincreases (i.e., the thickness of a metal wire is increased and thepitch width is reduced, and as a result, coupling capacitance domi-nates the total capacitance). Thus, noise is easily coupled from theneighboring nets and becomes a signal integrity issue. Moreover,timing is also affected by this coupling, since it injects extra ACcurrent into a coupled net. These are called crosstalk effects.

Traditional chip design focuses on how to meet the timing con-straints of a circuit specification and to reduce its area. Thanksto CMOS circuitry, several analog circuit design issues have beenavoided or simplified. Therefore, more and more switching com-ponents are allowed to integrate onto a single chip, and eventuallya system on chip (SOC) can be realized. However, the currentprocess technology introduces a large amount of switching digitalnoise, making the design process more difficult, and more similarto an analog design.

2 STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS

We are motivated to study the effects of digital crosstalk noise,focusing on how to analyze them on the SOC designs, includingtiming variation and its associated signal integrity issue. The goalof this work is to develop accurate and computationally efficientapproaches to calculating the influence of coupling capacitance instatic CMOS digital circuits.

1.1 Process TrendsThe increasing wire aspect ratio was originally expected to re-

duce interconnect delay in DSM technology. Figure 1.1 shows thedifference of the metal wire profiling between the old technologiesand the DSM technologies. The lateral or side-wall capacitance

becomes a dominant factor for the total capacitance calculation.Figure 1.2 (ITRS report, 1998 version) shows the change of themetal aspect ratio over time. As technologies advance, routingpitch decreases and the aspect ratio increases. Note that couplingcapacitance over substrate capacitance ratio also increases. Thisside-wall or coupling capacitance links neighboring nets’ switch-ing to a signal net electrically; hence, the crosstalk effects occurnaturally.

Introduction 3

1.2 CMOS CircuitryA static CMOS circuit typically has a very good noise rejection

capability. Figure 1.3 shows an input-output transfer curve. Aninput signal is considered logic 1 if the voltage level is aboveor logic 0 if the voltage level is below Due to the CMOScircuitry, input voltage tolerance is rather large. It also impliesbetter noise tolerance compared with analog circuitry. However, ifany noise can pull the input voltage up over the output voltageis easy to saturate and changes into a false state [Kir97].

However, as CMOS technologies lower down the supply voltageas well as the threshold voltage of a transistor, which is equivalent


to reducing the noise margin, digital designs are more and moresusceptible to noise.

Dynamic CMOS circuitry is another circuit family that is sensi-tive to glitches. Using pre-charging approach, it lacks the capabilityof static CMOS to restore a logic level back once when there is anycoupled noise.

2. Background and Crosstalk Effects

Timing analysis is an important method to verify if a chip canmeet performance requirements. Given a circuit network and itscomponent models, timing analysis calculates signal propagationdelay to verify whether the results can be delivered on time at theoutputs. Unlike dynamic timing analysis, static timing analysis

2.1 Static Timing Analysis

Introduction 5

uses a static approach to analyze the network topology withoutexhaustive simulation of all possible input paths. Although it isconservative and pessimistic, STA is still very efficient even formulti-million-gate designs, compared with dynamic simulation ap-proaches. Therefore, the current design trend employs STA in astandard flow during the chip design process.

2.2 Crosstalk EffectsConventionally, a victim is a net that suffers from noise effects,

and an aggressor is a net that contributes the noise. These rolescan change depending on the context. Consider Figure 1.4, where

the victim receives AC current from the aggressor, which makes atransition from 0 to 1. The current is written as:

where C is the coupling capacitance, and and are the voltageof the aggressor and the victim, respectively.

If the victim is not switching, is restored to its original state,and its waveform becomes a glitch propagating forward. If thevictim is switching, depending on the direction of this switching,there is almost no current injecting to the victim (i.e., the couplingC is negligible if is changing in the same direction as


otherwise, the coupling C might have a “double” capacitance ef-fect, if they are switching in the opposite directions). Thus, wehave two crosstalk effects: glitch and timing variation. Signal in-tegrity degradation or glitching occurs when the noise couples toa static signal, causing an erroneous logic voltage level. For pre-charge logic, this is a deleterious effect. Timing variation occurswhen the noise couples to a switching signal, causing delay degra-dation or speed-up. Many approaches have been proposed to takethese effects into account in static timing analysis [Sap99,TCE00, ARP00, CKK00b, XCMS00, ZSN01, CKTK02].

2.3 Functional FailureCrosstalk might induce functional failure or glitch effects[She98a]

[Kir97]. For example, considering Figure 1.5, the glitch inducedon the victim net could propagate to a latch and change its state,creating a functional failure. Note that glitch propagation is alsorelated a sensitization problem. Typically, a glitch diminishes veryquickly across a CMOS gate or it saturates as a full swing waveformquickly depending on the glitch voltage and its waveform width,and the CMOS gate’s AC noise rejection characteristics. This kind

of failure is an important issue for signal integrity. Later, we willdiscuss how to detect the maximum voltage glitch.

Introduction 7

2.4 Timing VariationCrosstalk noise can cause timing variations in two ways. If two

nets switch at about the same time in the same direction, the delayis decreased, and for switching in the opposite directions, the delayis increased. Delay decrease is a concern because it may cause holdtime violations, while delay increase is also a concern because itmy cause setup time violations. Consider Figure 1.6, where the

aggressor’s coupling noise can add extra delay to the signal prop-agation. If the adjacent nets are quiet, there is no delay variation.Therefore, it is important to identify when a net can possibly switchfrom one state to another. Thus, a switching window is defined asa timing duration in which a net or a timing node can possibly maketransitions. Figure 1.7 shows an example where node z has severaltiming paths, one of which creates the earliest arrival time, whilethe other creates the latest arrival time. The interval between thesetwo time points forms a switching window. Identifying overlap-ping between switching windows can reduce pessimism involvedin crosstalk noise analysis, because no timing variation can be in-duced between two nets when there is no overlap of the switchingwindows.


3. Search Space PruningIn practice, the space for possible signal interaction of crosstalk

coupling noise is too large to search efficiently. The spatial, electri-cal, temporal, and functional properties of a circuit [Kir97] closelyinteract to result in significant crosstalk noise. These properties aredescribed in the following sections.

Since the only concern is significant noise which is greater thanan allowable margin, these properties can then be used to reduce thesearch space by excluding some of the conditions which apparentlydo not cause any significant noise on a victim net.

3.1 Spatial PruningIntuitively, two adjacent nets in the layout are potential candi-

dates for capacitive coupling. This gives us a first level of pruning:only adjacent nets may have crosstalk coupling effects. Conven-tional parasitics extraction provides a very good tool to filter outsignificant crosstalk effects by extracting coupling capacitance onlybetween any adjacent nets. Any capacitive coupling effect acrossmore than one metal wire is insignificant in modern processes andis typically ignored.

Introduction 9

3.2 Electrical PruningUsing a simplified lumped RC model, the noise level on the

victim due to an aggressor can be calculated as Eq. 1.1. Consider-ing a pair of victim and aggressor nets in the physical layout, thewaveform on the victim net can be computed as [RIZK94]:

where See Figure 1.8, where are thecapacitance of the victim net, aggressor net, and coupling capaci-tance, respectively; is the resistance of the victim net. If multiple

aggressor nets have coupling effects on the victim net, shouldbe modified as the sum of and all the coupling capacitances.Assuming linearity, the total coupling effect can be calculated as a


superposition of each coupling effect using Eq. 1.1– that is:

where is each coupling capacitance to the aggressor net isthe time when the aggressor net begins to fall, and is the fall timeof the aggressor net The maximum value of occurs whenall of the are equal. This value is used in a simple worstcase model, where one assumes the extreme case might happenregardless of timing edge alignment or functionality.

Moreover, to address the timing variation due to crosstalk, Chap-ter 2 provides a method to calculate delay considering couplingbased on Miller factors to decouple a coupling circuit model.

3.3 Temporal PruningThe crosstalk noise is also related to the timing window of each

net. For example, in Figure 1.9, the net V’s timing window overlapsthe net A1’s timing window, which means that net V might beattacked by net Al, while the timing window of net A2 is far fromthat of net V and unlikely to have any crosstalk noise on net V.This approach is reflected in the static noise analysis model, wherethe functional information is ignored but the timing informationis included. In this model, if an aggressor signal shares a validtiming window with respect to a victim signal, then one makes theconservative assumption that the transitions are correlated to createmaximum crosstalk.

Chapter 3 will provides mathematical formulation and analysisfor how to compute these switching windows conservatively, effi-ciently and robustly considering different coupling models. Chap-ter 4 also proposes an event-driven algorithm to speed up this com-

Introduction 11

putation. Chapter 5 has an approach reducing the pessimism ofthis static approach.

3.4 Functional PruningApplying temporal and electrical pruning alone might be inad-

equate. Just as functional pruning can be used in static timinganalysis to eliminate paths that are never responsible for the delayof the circuit, functional pruning can be used in noise analysis toeliminate those signals/paths that can never be responsible for noiseproblems because of their functional relationship. By exploring thefunctional space, we can search for a pair of input vectors whosefunction allows them to create the maximum noise. This approachis reflected in the zero-delay model, where temporal informationis ignored but functional information is included. In this model,if an aggressor signal transitions against a victim signal within aclock cycle, then one makes the conservative assumption that thetransitions were correlated so as to create maximum crosstalk.

Chapter 6 focuses on how to formulate this problem and translateit into a Boolean constrained optimization problem.


3.5 Problem Complexity v.s. Accuracy

The maximum crosstalk noise depends on the electrical, tempo-ral, and functional aspects of a circuit, so it is generally not easyto be determined exactly. Several techniques have been proposed[SNEZ97b, YCGS97, Kir97] for bounding the maximum crosstalknoise. In general, the electrical information can be easily consid-ered.

In the floating mode delay model [DKM93], the prior state ofboth the victim and aggressor signals are ignored. In this model,both signals are initially assumed to be in an indeterminate state. Ifthere is a vector that causes multiple aggressors to arrive at the samevalues with temporal correlation, then the conservative assumptionis made that the prior state of each signal (before the single vec-tor was applied) will set up the signals for maximum crosstalk.Finally, the fixed-delay 2-vector model considers both timing andfunctional completely.

The waveform of each method might look like Figure 1.11. Inthe simple worst case, only electrical pruning is used so that everyaggressor is assumed to switch in the opposite direction of thevictim net V. The zero-delay model ignores the timing effects, whilethe static approach ignores the functional effects. The fixed-delaymodel considers the timing and functional effects at the same time.

The relationship between these techniques is shown in Figure1.10. The maximum accuracy results from the maximum inte-gration of functional and timing information. Thus the 2-vectorapproach is more accurate than the others. The relative accuracybetween the other approaches varies from circuit to circuit.

Excluding timing information, such as the zero-delay model, westill get a Boolean Constrained Optimization Problem (BCOP),which is equivalent to the Binate Covering Problem (BCP). Thestatic analysis method can result in a linear programming prob-lem [She98a]. However, when the functional aspect is involved, itbecomes a BCOP.

Introduction 13

4. OverviewThe goal of this work is to develop techniques to analyze digital

crosstalk effects with a robust, efficient, accurate and conservativeapproach for use in STA.


To address delay calculation considering crosstalk effects, inChapter 2, we propose a method to take this coupling effect intoaccount with a simple extention to traditional delay calculation. Atraditional method makes the worst case assumption where twicethe coupling capacitance is used to capture this opposite-directioncoupling effect. This forms a decoupled version of the circuit foreach node, where capacitances are replaced by their Miller equiv-alent. However, this approach can limit the design space dramati-cally and lead to a very pessimistic design. Chapter 2 proposes amethod based on Miller factors to decouple a circuit such that thetraditional approach to calculating timing delay is still valid andoffers a good approximation.

In Chapter 3, we focus on the timing aspect, including couplingeffects. A formal model is proposed and discussed. The theoreticalfoundation of switching windows calculation, including couplingnoise analysis will be discussed. This is a pure static approach totemporal pruning. Most of the theoretical problems can be solvedusing this framework.

In Chapter 4, we propose an event-driven algorithm to computethe whole-chip timing in the presence of crosstalk. The event-driven algorithm using different scheduling approaches is com-pared and explored.

In Chapter 5, we further refine our switching window model intoa discrete type to reduce analysis pessimism. Because the numberof timing paths is finite, the switching events in a switching windowshould be discrete. We propose the creation of time slots in aswitching window to accurately analyze an aggressor alignmentproblem.

In Chapter 6, we discuss functional aspects of crosstalk effectsanalysis. Although the computation comes with high computa-tional complexity, it is still valuable to formulate and solve thefunctional noise analysis problem. A vector-pair search algorithmis explored to search for the maximum crosstalk noise problem.

Chapter 2

MILLER FACTOR COMPUTATIONFOR COUPLING DELAY

In coupling delay computation, a Miller factor of more than2X might be necessary to account for active coupling capacitancewhen modeling the delay of deep submicron circuitry[YCGS97].We propose an efficient method to estimate this factor, such thatthe delay response of a decoupled circuit model can emulate theoriginal coupled circuit. Under the assumptions of zero initialvoltage, equal charge transfer, and as the switching thresh-old voltage, an upper bound of 3X for maximum delay and a lowerbound of - 1X for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computingthe Miller factor or effective capacitance on a coupled model fordecoupling. This result is highly applicable to crosstalk couplingdelay calculation in deep submicron gate-level static timing anal-ysis. Detailed analysis and approximation are presented. SPICEsimulations demonstrate high correlation with these approxima-tions.

1. Introduction

Using a Miller factor is a very convenient method to reduce ahighly-coupled circuit to a simpler decoupled approximation (e.g.


a second order system to a first order one). If a coupling capacitor isconnected between two nodes, as shown in Figure 2.1, the effectivecoupling capacitances are equal to and groundedcapacitance, respectively, where the two nodes have a voltage gain

In digital designs, is conventionally estimated as 2 for the

opposite direction switching between two coupling nets, and 0 forthe same direction switching. However, more than 2X factor hasreported [YCGS97]. In this chapter, we present a detailed analysisfor how the 2X Miller factor is not an upper bound for couplingdelay calculation, and provide a more accurate method to estimatethe coupling effect by a decoupling approximation. The factor canbe proved as large as 3X under reasonable assumptions. A simpleiterative approach and Newton-Raphson iterations are proposed tofind these factors. HSPICE simulations are used to demonstratethe accuracy of these factors. Moreover, because the overshootor undershoot waveform can also affect circuit delay, a correctionmethod is proposed to approximate the effect of overshoot or un-dershoot.

Our method is crucial for the underlying coupling model fordelay calculation in deep submicron circuitry. The Miller factorcan be used to approximate a coupling capacitor by two groundedcapacitors so that the conventional delay calculation mechanismremains unaltered. Due to the mutual dependency between switch-ing windows and timing delays, the static timing analysis approachmust iterate in order to calculate full chip delays in the presenceof crosstalk TCE00]. An efficient and accurate estima-tion of the coupling effect is crucial for fast convergence. Fixed

Miller Factor Computation for Coupling Delay 17

Miller factors (2X for the opposite direction switching, and 0 forthe same direction switching) are not accurate enough for calculat-ing coupling delay as shown in this chapter. These factors provideneither a bound guarantee nor a good approximation of delay undercoupling.

In [YCGS97], the authors show that 2X factor is not an upperbound for crosstalk delay and slew rate, but they do not providea more accurate factor or prove a new bound. In [DP97], the au-thors present an iterative algorithm based on [DMP96] to calculategate delay by approximating the gate response waveform and RCinterconnect response. They address how to find an effective ca-pacitance and nonlinear driver model. This can be very accuratefor waveform approximation, although it is time-consuming be-cause Newton-Raphson iterations are needed. Moreover, Newton-Raphson iteration with high dimension matrices can be very slowor divergent as it is tricky to find an initial starting point in theconvergence region. In contrast with their approach, our approachshows how to decouple the coupling capacitance in a circuit whilemaintaining delay accuracy. Our method is independent of thedriver model. Many analytical models with a linear driver re-sistance have been proposed, such as [KMV99][BH00][CGB97][XMS00a]. These models are useful to analyze the crosstalk delayand noise pulse for first level screening. However, as shown in Sec-tion 2.2, the linear model might not be accurate enough due to thedriver’s significant nonlinearity. [SNEZ97a] and [Dev97] reportalgorithms to calculate the coupling interconnects. In addition,

provides an industrial example of how the crosstalkdelay and noise are estimated.

Because the primary use of this work is STA, complete waveformaccuracy is not required for static timing analysis – we need onlythe accuracy up to the switching threshold point to approximatedelay accurately. Therefore, we use a decoupling approximation,as shown in Figure 2.1, to emulate and match the circuit responseat the switching threshold point. In addition, a decoupling factor


like the Miller factor is easy to use and integrate into an existingtiming analysis flow.

In this chapter, we introduce a gate driving model and show whysuperposition or the single driver resistance model is not suitablefor crosstalk coupling computation. In Section 2.3, we discusshow to derive a Miller factor for the delay calculation matchedat the switching threshold point, and present efficient methods tocalculate Miller factors and resolve the convergence issue. Due tothe overshoot/undershoot waveform or noise glitch coupled fromaggressors, the initial voltage can be quite different from zero. InSection 2.4, we propose a correction factor to fix this problem. Itis also useful for glitch waveform estimation. In Section 2.5, weshow experimental results from HSPICE simulations.

2. Gate Driving and Coupling ModelSuppose we have a coupling circuit, as shown in Figure 2.2,

where we lump all the interconnect resistance of the victim as

all the grounded interconnect capacitance of the victim net asand all the coupling capacitance as Note that we refer to thesetwo nets as one for victim and the other for aggressor for easeof reference. We calculate the delay impact for a victim net asits aggressor nets contribute noise. Without loss of generality, we


assume a rising waveform on the victim net throughout this chapter.It is symmetric for the case with a falling waveform.

2.1 Nonlinearity of Driver ModelMany previous works propose a linear driver model [CGB97]

in which the driver is connected with a seriesresistance and a voltage source– for example, a Thevenin equiva-lent circuit, as shown in Figure 2.3 [DMP96][DP97]. It is useful

to obtain an analytical formula for delay or noise peak analysis.However, this might not be accurate. In Figure 2.4(a), we showhow the driver conductance on a victim net can be nonlinear duringthe signal transition. It is actually not fixed over time and can varysignificantly. The conductance vs. output voltage is also nonlinear,as shown in Figure 2.4(b).

The nonlinear driver resistance prevents superposition of wave-forms. In Figure 2.5, we show how a coupling noise can vary withdifferent arrival times of the aggressor. As the aggressor’s arrivaltime is varied, we calculate the coupled noise on the victim netby subtracting the original victim’s waveform from the victim’scoupled response. If superposition works in these cases, the noisepeaks should be the same shape with shifted positions. However,Figure 2.5 shows that the noise peaks can vary according to thearrival times of the aggressor. Therefore, the single resistance as-sumption for the driver or superposition for waveform estimationmight not be accurate for crosstalk delay or noise calculation.


We model the driver resistance as a time-varying and voltage-dependent current source to avoid the inaccuracy of using lineardriver model.


2.2 Driver ModelingWe model the time-varying voltage-dependent current source

for a victim driver. For a CMOS transistor, the drain current isdependent on the drain-to-source voltage and gate-to-sourcevoltage It is can be written as Becausethe gate-to-source voltage depends on the input waveform, and thedrain-to-source voltage is dependent on the output, we model thedriving current as a function

3. Decoupling ApproximationIt is usually difficult to analyze a coupling circuit like the one in

Figure 2.2. If we can replace a coupling circuit with a decoupledcircuit using Miller factors to multiply the decoupled capacitors, itis much easier to calculate the delay. Therefore, the objective ofdecoupling approximation is as follows.

Objective of Decoupling ApproximationThe victim’s transition interval from 0 to is the target transitioninterval we intend to approximate, and the delay value measured at

of the transition point (starting from zero voltage) of the decou-pled circuit, shown in Figure 2.6, should approximate the responseof the original coupling circuit (Figure 2.2). The term inFigure 2.6 is called the Miller factor.

In some cases, the initial voltage might not be zero due to the


early arrival of the aggressor signal. We defer this discussion toSection 3.4.

3.1 Coupling ModelCombining the driver model above, the circuit equation for Fig-

ure 2.2 can be written as

For simplicity, assume the switching threshold point is at 50% ofin this chapter. Integrating it over the period from the rising

time of the victim, to the switching threshold point, for thedelay computation of 50% transition, we have:

This can be simplified as, where and

Eq. 2.4 implies a factor

to approximate the coupling capacitance assuming equal chargetransfer at this period. We can find an aggressors’ voltage differ-ence in the period of the victim’s transition from 0 to (e.g.Figure 2.7(a)) to calculate the Miller factor.

3.1.1 Bounds

Assuming equal charge transfer from zero voltage to on thevictim net, we have a theorem for bounds of the Miller factor for


coupling delay calculation.TheoremUnder the assumption of zero initial voltage and themaximum Miller factor of the opposite direction switching is 3 forcoupling delay calculation measured at the 50% transition. Theminimum Miller factor is -1 for the same direction switching at the50% transition.

Proof: From Eq. 2.4, the bounds are easily derived. If the aggres-sor and the victim switch in the opposite directions, we can have anupper bound 3, when is equal to and


If the aggressor and the victim switch in the same direction, wecan have as a lower bound of -1, when is equal to and

3.2 Simple Iterative Approachis actually unknown before the coupling delay is calculated,

so the Miller factor cannot be estimated accurately beforethe delay is calculated. A simple approach can iterate onuntil it converges. For ease of notation, we drop the index for thefollowing discussion wherever there is no confusion. Consider afixed ramp waveform on an aggressor and the victim switchesat the opposite direction. versus the victim’s ramp time isshown in Figure 2.7(b). Some notations are defined as:

the effective capacitance which is

as the function of effective capacitance, which is theramp time or slew rate response at the node that the couplingdelay measured at the switching threshold point is to be matched,and

as the function of as shown in Figure 2.7(b).

So a composite function can be defined to compute a newgiven

Simple iterative approach just combines Eq. 2.5 and Eq. 2.6, i.e.


to iterate until it converges. We note that the convergence rate ofthis approach is linear.

3.2.1 Convergence of the Simple Iterative Approach

The curves for the Miller factor versus the effective capacitanceshows how this algorithm converges. Four possible curves are

shown in Figure 2.8. The dashed line is the mapping from the Millerfactor calculated by Eq. 2.6, and the solid line is the Miller factorby Eq. 2.5. Starting from the Miller factor equal to 3, Figure 2.8(a),

(b) and (c) can converge to point M. The algorithm is equivalentto starting from an initial Miller factor, mapping it to an effectivecapacitance along the solid line (Eq. 2.5), and then computinga new Miller factor according to Eq. 2.6 along the dashed line.This process repeats until it converges to point M. In (d) theremight be 2 points M and M’ that the algorithm can converge to,


depending on the initial point. The conservative approach is to takethe initial value as 3 to converge to the upper point M. Physically,this condition corresponds to a very weak victim driver and a verysharp aggressor transition. Most of the cases result in a spike,which is not easy to approximate by this method.

3.3 Newton-Raphson Iteration for Miller FactorThe convergence rate can be improved by using the Newton-

Raphson iteration. The key is to compute the derivative of Byusing Eq. 2.7, the Newton-Raphson iteration is set to find the rootof:

The derivative of is:

where can be calculated and found by a simple tablelookup from the conventional characterization data of a standardcell library. The Newton-Raphson iteration can therefore be writtenas:

Note that if is equal to 0, simplifying Eq. 2.10, we have:

This is equivalent to the simple iterative approach from Eq. 2.7.The strength of this approach is the quadratic convergence rate of

Newton-Raphson iteration and the convergent initial value is easyto find because the value of is between -2 to 2 ifand hence the value of is between and


Note that strictly speaking, (defined in Section 2.3.2) doesnot only depend on but also depends on the relative delay be-tween the aggressor and the victim, which is in turn dependenton There is no explicit analytic formula available to accu-rately describe the relation. Conventionally, is describedby a two dimensional table pre-characterized for the driving cells.However, the derivative can be relaxed by finite difference approx-imation. Empirically, the derivative function can be wellapproximated by the finite difference because the original function

is very close to a linear function.The number of iterations versus the ratio of coupling capaci-

tance to grounded capacitance for two approaches are comparedand shown in Figure 2.9, where the convergence criterion is such

that the relative error is less than The peak in Figure 2.9is a case for which the simple iterative approach takes 43 itera-tions to converge. The trace for both approaches for this specialcase is shown in Figure 2.10. It shows that the simple iterative ap-proach has to iterate more steps around the convergent point, whileNewton-Raphson takes few steps to converge.


3.4 Multiple Miller Factors for Multiple CouplingNets

For multiple nets coupling together, the simple iterative approachbecomes

However, multiple values can be found in a single Newton-Raphson run. There is one for each coupling net. Onceis known, can be computed, and hence the Miller factors.Unlike the approach in [DP97], we address how to use a decoupledcircuit to emulate the original one, while [DP97] addresses how tofind and the gate delay. Our model is independent of the drivermodel used. Actually, the gate driver model and RC interconnectdelay are encapsulated in the function where and

are the effective capacitance and ramp time, respectively, at thenode where the coupling delay should be matched.

For completeness of this chapter, we derive the Newton-Raphsoniteration in the following equations. Suppose we have:


set to find the roots, where the superscript denotes the relatedvariable at net and net has net as a coupling net with couplingcapacitance The partial derivative of is

where

which is nonzero only whenWe test this algorithm on a case of two coupling nets with a rising

ramp on both nets. The result is shown in Figure 2.11, where isequal to 0.05pF. Note the difference between this and the previoussection is that neither of the nets has a fixed output waveform. Thesimple iterative approach fails to converge within 200 steps belowthe capacitance ratio 1.75. We also test a case with four coupling

nets with a rising ramp on each net. The result is as shown in Figure2.12.


3.5 Slew Rate (Transition Time) CalculationSlew rate (transition time or ramp time) is another factor that

affects the delay calculation. However, if the effective couplingfactors are used to approximate the slew rate, we have to match upto the upper point of transition (typically 90% or 80% of transition)or down to the lower point of transition (typically 10% or 20% oftransition). It might need more than one Miller factor to calculate.The difference is to make in Eq. 2.4 for the upperpoint of transition at 90% of or for the lowerpoint of transition at 10% of

4. Nonzero Initial Voltage CorrectionSome waveforms might not start from zero voltage. This leads

to another source of errors for the Miller factor approximation. Weshow how to correct this problem in this section.


4.1 Glitch Waveform ApproximationConsider a case when an aggressor is making transition before a

victim, such that an undershoot waveform occurs on the victim net,as shown in Figure 2.13(a). The victim’s initial voltage being zero

is not exactly accurate due to the glitch coupled from the aggressor.Consider a falling aggressor with a ramp waveform. A simplifiedmodel is used as shown in Figure 2.13(b). We have

Assume and by averaging approxi-mation. It can be rewritten as

If multiple aggressors are present, and the initial voltage of isnonzero we can extend it as

where is 1 if the aggressor is falling, or -1 if the aggressor is ris-ing, and zero otherwise. This equation also applies when multipleaggressors join in different time points.


This modeling is verified with HSPICE simulations. One ex-ample is shown in Figure 2.14. The victim’s driver resistance is856 ohm, the aggressor has a perfect falling slope of 0.5ns, is0.02pf, is 0.01pf, and is 3.3v. It shows that at the cornersof the curve this model has some small errors.

5. Experimental ResultsWe verify the estimated Miller factors by HSPICE simulation on

a simple circuit with a fixed ramp input on an aggressor net, and apure capacitive loading on the victim net with some coupling capac-itance. In Figure 2.15, we vary the aggressor’s arrival time to see theeffect of the delay variation on the victim net. The estimated Millerfactor is calculated using the decoupling approximation, describedin Section 2.3, and the undershoot correction is also computed. Us-ing this factor, HSPICE simulation is performed on the decoupledcircuit again to measure the delay. The same procedure is repeatedfor 2X Miller factor. Our method (marked as decoupling approxi-mation) closely follows the original coupling circuit within 7.5%,while the 2X Miller factor can be farther(18.2%) off. In addition,


it shows that 2X is not an upper bound. In Figure 2.16, we vary

the aggressor’s ramp time to see the effect of delay variation onthe victim net. Our method (marked as decoupling approximation)closely follows the original coupling circuit, while the 2X Millerfactor can be farther off. Typical waveform response is shown inFigure 2.17.

6. Review of ConservativismThe approach proposed in this chapter is a good approximation to

coupling delay, although it is not strictly conservative (see Figure2.15). Some of the approximated delays may under-estimate orover-estimate. It may be combined with temporal pruning methodsas described in Chapter 3 and 4 to give better accuracy.


7. ConclusionIn this chapter, we have proposed a simple and accurate method

to estimate the Miller factor for approximating a coupling circuit bya decoupled circuit. It is well-suited for coupling delay calculationin very deep submicron designs. An efficient Newton-Raphsonmethod is proposed to find the Miller factors or effective capaci-tance. In addition, we prove an upper bound of 3X for the oppositedirection switching, and a lower bound of -1X for the same di-rection switching. The conventional 2X factor is shown clearlynot to be a bound and can be very inaccurate for coupling delaycalculation.

Chapter 3

CONVERGENCE OF SWITCHINGWINDOW COMPUTATION

Detecting the overlap of switching windows between couplednets is an important static technique to accurately locate crosstalknoise. The amount of coupling noise depends on extent of over-lap between switching windows, but the coupling noise also af-fects signal switching times (and therefore switching windows).Hence, there is a mutual dependency between switching windows,so computing the coupling effect requires iterations to converge.In this chapter, we discuss the issues and provide answers to theimportant questions involved in convergence and numerical prop-erties, including the effect of coupling models, multiple conver-gence points, convergence rate, computational complexity, non-monotonicity, continuity and the effectiveness of bounds. Numer-ical fixed point computation results are used to explain these prop-erties. Our contribution here builds a theoretical foundation forstatic crosstalk noise analysis.

1. Introduction

With crosstalk noise, switching windows are considered mutu-ally dependent in static timing analysis (STA), and the computa-tion cannot be completed in a single traversal of nets in general


[Sap99, TCE00, ARP00, CKK00b, XCMS00, ZSN01].Iterations are therefore needed to resolve the mutual dependency.Thus, the following questions arise:

Does it always converge? What coupling or overlapping modelslead to divergence?

Is there a unique convergence point independent of an initialcondition? Is it physically realizable or just a bound?

At most how many iterations are needed? What is the compu-tational complexity? How fast does the process converge?

If a gate delay is reduced, is a circuit’s longest path delay con-sidering crosstalk noise reduced as well?

If a gate delay is increased continuously, will the crosstalk noisealso be monotonically increased?

In [ZSN01], the authors suggest the use of a lattice theory toprove convergence of switching windows computation and showthat there are multiple convergence points depending on the ini-tial condition. However, the coupling model they used is veryprimitive and is not accurate due to its discrete nature. We willtackle this problem from a different point of view using a numer-ical fixed point computation perspective [EMU96]. We will alsoexamine the impact of discrete and continuous coupling models onconvergence and numerical properties of switching windows com-putation. Moreover, the questions listed above will be studied inthis chapter.

The remainder of this chapter is organized as follows. In Section3.2, we introduce some definitions used in the chapter, and give theupper and the lower bounds. In Section 3.3, we address fixedpoint computation applied to switching windows computation. InSection 3.4, we examine the underlying models used in switchingwindows computation. In Section 3.5, we discuss convergence andefficiency issues.

Convergence of Switching Window Computation 39

2. BackgroundA quantity is said to be noisy if crosstalk noise effects have been

included. In contrast, a quantity is said to be noiseless or nom-inal if the crosstalk noise effects are not included. For example,a noisy delay is the nominal delay plus the extra delay inducedby crosstalk effects. Similarly, a noisy switching window is thenominal switching window including the extra path delay (timingvariation) induced by crosstalk effects.

A coupling edge exists from the victim to the aggressor in theSTA timing graph if there is a coupling capacitance linked betweenthem. A coupling edge is said to be active if the delta delay inducedby this edge has been included in its victim’s noisy switching win-dow. In the process of switching windows computation, a couplingedge can change its state from inactive to active due to overlappingof noisy switching windows, or vice versa.

For simplicity, we assume a single delay value on interconnectfor all of the fanouts of each net in the following discussion. Letand be the latest arrival time of net and the earliest arrival timeof net respectively. Let be a switching window

overlapping function of time difference. Figure 3.1 is an exampleof function If the switching windows donot overlap, and resulting in no coupling noise. Asthe coupling noise begins to show and eventually saturates at anormalized value of 1.0. The delta delay induced from aggressornet to victim net is thus written as:


where is the maximum delta delay induced from ag-gressor net to victim net

An index set denotes a collection of net indices, representing asubset of all nets. Let be the interconnect delay of net bean index set of aggressor nets of net be an index set of faninnets of net driving gate, and be the gate delay froma fanin net to net Figure 3.2 relates these variables to a circuit

diagram. and are written as

and

respectively. Note that and are not exactly the samefunction. To simplify the notation, we denote it as because itcan be distinguished by the context to use for or for

respectively.A quantity associated with no coupling effect is unconditionally

realizable. For example, a noisy arrival time in Eq. (3.1) of avictim net is said to be realizable if and are all realizable.Starting from inputs of a circuit, the longest and the shortest noisydelay to each net have to be realizable in order to achieve realizableswitching windows for the entire circuit.


2.1 Simple Upper and Lower Bounds forSwitching Windows

What are the possible latest and earliest arrival times thatconsider crosstalk noise? When all crosstalk noises are active andinduce the maximum extra delay to increase the latest arrival timeand reduce the earliest arrival time, this is the largest switchingwindow (i.e. the upper bound), that can be achieved with crosstalknoise. The upper bounds are written as

and

On the contrary, when all crosstalk noises are excluded, the nom-inal switching window gives the lower bound (i.e. the smallestpossible switching window). The lower bounds are written as


and

The relationship between the bounds and the final switching win-dow are illustrated in Figure 3.3.

3. Fixed Point ComputationFixed point computation provides a convenient vehicle to explore

the underlying properties of how the computation precedes. In thissection, we propose the formulation and point out some importantproperties.

3.1 FormulationLet be a switching window configuration, where N is

the number of nets or timing nodes in switching windows computa-tion. For N nets, we need 2N variables to represent the latest arrivaltimes, and the earliest arrival times, respectively (if riseand fall switching windows are considered separately, 4N variablesare needed). Let f : be a mapping or transformationfrom x to a new switching window configuration consideringthe crosstalk noise based on the switching windows’ overlappingcalculated according to x.

The objective of switching windows computation thus can be for-mulated as finding a fixed point, such that [ZSN01 ].Specifically, iteration equations are written as

and


With an initial guess, we can perform fixed point iterationsas

until it converges. This process is usually referred to as a fixedpoint computation [EMU96].

3.2 Fixed Point Iteration for Switching WindowsComputation

Let D be a closed and bounded domain in and letfor all For any two points if there exists aconstant L, such that

where denotes a norm for the vector space D, f(x) is called aLipschitz function, and L is called a Lipschitz constant. Using thefixed point computation [EMU96], if the fixed point it-eration converges and guarantees a unique convergence point (fixedpoint), given any initial This is a sufficient condition forexistence, convergence and uniqueness [EMU96].

In practice, for the one dimensional case, L is roughly estimatedas

and

where sup is an upper bound (maximum value) function, isthe maximum noise induced by an aggressor and and are theslew time of a victim and an aggressor, respectively. In general, Lis not bounded by 1.0. It depends on the underlying models, whichare discussed in Section 3.4. If a ramp waveform is assumed,sup can be estimated as since the victimstarts to change when the aggressor waveform overlaps with the


50% point of the victim waveform, and saturates as 1 whenthe aggressor ramp doesn’t overlap with the 50% point of thevictim waveform. The time interval is equal to and the slope istherefore

To give an example L > 1, consider the electrical model used in1.3.2. We can estimate:

so we have:

It is not difficult to find real design values that make the L abovegreater than 1. Consider an example circuit in Figure 3.4. Supposethe aggressor net G is driven by a very strong AND gate, so itsswitching window is not affected by the weak aggressor net H. Wecan calculate and as:

and

where is shown in Figure 3.4. If starts from 2.9ns, we canget the final as 2.9ns. If starts from we can get the final

as 3.1ns. This shows that we can have multiple convergencepoints depending on the initial switching window configuration.

For a one dimensional iteration function in Figure 3.5, wecan see:


where and are the lower and the upper bounds describedin Section 3.2.1, and victim net and two aggressors andtogether create function where and are the fixedpoints. A repeated substitution procedure that replaces the argu-


ment with its output value can be used to converge the se-quence. For the one dimensional case and a continuous function,a sufficient condition for convergence is given as Forf (x), the sufficient condition [EMU96] is where J is theJacobian matrix of f(x).

3.3 Multiple Convergence Points and UnstableFixed Point

Since L is not generally bounded by 1.0, it is easy to produce mul-tiple convergence points in switching windows computation pro-cess. The actual convergence point depends on the initial switchingwindows [ZSN01].

For fixed point computation, a unique convergence point requiresa Lipschitz constant L less than 1.0. In switching windows compu-tation, L is not bounded for discrete models introduced in Section3.4, and therefore there can be multiple fixed points. Even for a

continuous model, it is possible for L to be greater than 1.0. Forexample, in Figure 3.6, points and are all fixed points, andthe initial condition determines which fixed point the iteration con-verges to. Notice that point is unstable becauseA small perturbation can drive convergence toward points orUnstable fixed points cannot be obtained through fixed point com-putation.


3.4 Tightening BoundsA conventional convergence scenario uses infinite switching win-

dows for the initial condition to include all the noise effects in thebeginning and shrinks the switching windows in the subsequentiterations [ARP00, XCMS00]. [ZSN01] shows that starting fromthe infinite switching windows, the process can converge to a looserupper bound of switching windows.

Using Eq. (3.1) and (3.2), we can prove this monotonicity byinduction as follows.

THEOREM 3.1 If in the initial two steps, and

for all then forms a monotonically non-increasing se-quence, and forms a monotonically non-decreasing sequence.

Proof: The proof is by induction on the iteration number. The basecase is clearly

Assume that

so

is a non-decreasing function, so we have

Also

Therefore,


Similarly, the sequence can be proved symmetrically.Corollary 1.1 If the initial configuration starts from the maximumswitching windows, forms a monotonically non-increasing se-

quence, and forms a monotonically non-decreasing sequence.This result actually shows that the switching window shrinks start-ing from the maximum switching window – that is, the upper boundis reduced in each iteration. Thus, the accuracy of the noisy switch-ing windows’ bound computation depends on how much run timecan be afforded. The results are still valid upper bounds of switch-ing windows even before convergence. This is a strictly conserva-tive process.

Similarly, using the minimum switching windows as the initialcondition, the lower bound increases as the convergence processprecedes. We have the following theorem and the corollary.

THEOREM 3.2 If in the initial two steps, and

for any forms a monotonically non-decreasing se-quence, and forms a monotonically non-increasing sequence.

Proof: The proof is by induction on the iteration number. The basecase is clearly

Assume that

so

is a non-decreasing function, so we have

Also


Therefore,

Similarly, the sequence can be proved symmetrically.Corollary 2.1 If the initial configuration starts from the noise-less(smallest) switching windows, forms a monotonically non-decreasing sequence, and forms a monotonically non-increasingsequence.This corollary actually provides a method to obtain the tightestswitching windows defined in Section 3.2.

These results create a monotonic transformation during fixedpoint iteration suggested by [ZSN01].

4. Coupling ModelsIn this section, we consider the underlying models for calculat-

ing noise. Discrete models are easier and faster to calculate and,in general, give a bound for crosstalk noise. However, the errorbound can be far off from the correct noise bound computed usinga continuous model.

Crosstalk noise induces a voltage glitch on a victim and causes atiming variation. The amount of the delta delay in a timing calcu-lation can be determined by aligning the noise peak with the victimwaveform so that the superimposed waveform peak reaches theswitching threshold (usually 50% of power rail voltage) [GRP98].Figure 3.7 shows this method. If the victim’s waveform is simpli-fied as an ideal ramp with a slew time the maximum delta delay

can be written as


4.1 Noise Calculation ModelTraditional STA often ignores all the coupling effects and re-

places any coupling capacitance with a grounded one. Conven-tionally, to calculate the coupling delay on each interconnect, adiscrete coupling factor model uses 1X grounded capacitancewhen the neighboring net is quiet, 2X for the opposite directionswitching, and 0 for the same direction switching [Sap00, ZSN01].Determining which factor to use depends on two nets’ switchingtime and the directions. However, Chapter 2 has been shown thatthe coupling noise can result in as much as a 3X capacitance effectwhen calculating the coupling delay [KMS00, CKK00a]. Besides,a discrete coupling factor model has a discontinuity between theboundaries when a coupling factor is changed to another factor.On the contrary, a continuous coupling factor model can be usedto avoid this discontinuity on the boundaries and increase accu-racy [KMS00, CKK00a]. Chapter 2 has a detailed discussion ofhow to determine this continuous coupling factor. However, theconvergence rate of discrete coupling factor model is faster than acontinuous one in practice.

More accurate models have been proposed using superpositionto calculate the total crosstalk noise without using any coupling


factor or decoupling the coupling capacitance, such as [ARP00, TCE00].

In [CKK00b] and Chapter 4, we propose a model, in which in-stead of direct substitution of in Eq. (3.1) to evaluate the crosstalknoise, they decompose an arrival time into a component that is con-tributed from the driving gate as

and, based on these arrival times and evaluate the noisy arrivaltimes as

and

It avoids pessimistically taking the noisy arrival time into accountfor switching windows’ overlapping. This model can still be cal-culated using fixed point computation.

4.2 Switching Windows Overlapping ModelFor multiple aggressors, the worst case noise should be calcu-

lated based on the switching window constraints – that is, due tothe path delays, the aggressors’ switching window might not beable to align arbitrarily to create the maximum noise.

In [SNEZ97c], the authors have proposed a mixed integer pro-gramming technique to find the worst possible noise. This modelassumes “sharpness” of the noise peaks and it is considered a dis-crete overlapping model, which only allows either a completenoise contribution or zero noise. That is to say, is a step func-tion in Eq. (3.1) and Eq. (3.2). Figure 3.8 shows a noise func-tion in such models. On the contrary, a continuous overlappingmodel allows the noise contribution to be fractional according tothe noise glitch waveform on the victim net and the overlappingrange. Figure 3.1 is an example of representing a continuous


model. Many efficient methods have been proposed to find themaximum noise or the maximum delta delay using these types ofmodels. For example, [TCE00, CKK00b] have proposed envelopewaveform methods, [XMS00b, CMS01] formulate it as a weightedchannel density problem and give an algorithm with O(M log M)complexity, where M is the number of aggressors.

Note that if an infinite slope is assumed on the boundary ofswitching windows, a continuous overlapping model becomes adiscrete overlapping model.

4.3 Discontinuity in Discrete Models

All of the discrete models mentioned above suffer from a draw-back of discontinuity on the boundary when a discrete factor ischanged to another discrete factor, or when the overlapping con-dition is changed. The noise is discontinuous when increasing ordecreasing gate delays. Figure 3.8 shows an example of disconti-nuity at and when using a discrete overlapping model.

If the discrete model is designed carefully, it can be an upperbound of crosstalk noise, which is considered to be very usefulin STA. The example in Figure 3.9 shows that the discrete modelconverges at point while the continuous model converges at point

which is bounded by point


4.4 Error Bound between Discrete and ContinuousModels

After convergence of switching windows, suppose no error wasincurred in the previous stage delay for a single pair of couplingnets. The error incurred due to the use of a discrete model can be aslarge as the maximum delta delay between a victim and an

aggressor net pair given the same initial configuration of switchingwindows. The error can be written as:

where is the continuous overlapping function, and isthe discrete overlapping function. Figure 3.9 shows an examplewhere the discrete model converges to point and the continuousmodel converges to point If every aggressor aligns exactly atthe same time, the error bound can be as large as the sum of themaximum delta delays:

Moreover, the error can propagate forward along a timing path andaccumulate to include all the maximum delta delays induced fromall the aggressors. Therefore, the error bound for a noisy longestpath delay is equal to the difference between the upper bound and


the lower bound of the ending net’s switching window of the path:

and similarly, the error bound for a noisy shortest path delay isequal to:

4.5 Non-Monotone PropertyOrdinarily, when delay of a gate in a circuit decreases, the longest

delay of the circuit will also decrease or remain the same. In thecase of crosstalk, the noisy longest delay of a circuit might increase.For example, consider a case in Figure 3.10, where if the arrivaltime of switching window is reduced, net might start to attacknet due to the overlapping of switching windows, resulting ina delay increase in net In terms of Eq. (3.1), as decreases,

increases, resulting in an increase of on the left handside. Using just one operational condition to determine andcan result in an optimistic evaluation of crosstalk noise.

Using a floating delay model [DKM93] (e.g. see Figure 3.11),which assumes zero for any earliest arrival time, i.e. in Eq.(3.1), it is still impossible to solve this problem. If we setEq. (3.1) becomes


which does not provide any useful information about switchingwindows.

5. Convergence of Switching WindowsComputation

In this section, we argue the convergence of switching windowscomputation.

5.1 Proof of ConvergenceTHEOREM 3.3 The iteration in Eq. (3.11) converges to a fixed point

given the initial switching window configuration asor

Proof: Convergence of the iteration can be proved by the followingfacts [ARP00, ZSN01]:

1

2

and have an upper and a lower bounds, as shown inSection 3.2.1.

If starting from by Corollary 2.1, forms a non-decreasing sequence and forms a non-increasing sequence.The iteration converges, since the sequences are bounded.


3 Using Corollary 1.1, we can prove similarly for the initial con-dition starting from

Some switching-window overlapping models might not havemonotonicity for f (x) with respect to For example, when anaggressor’s latest arrival time is much less than a victim’s arrivaltime, the switching window of the victim is not affected. This ef-fect can be captured by adding an extra term to Eq.(3.1) as:

However, as shown in Figure 3.12, Eq. (3.19) has a decreasing por-tion, leading to oscillation among points and so the iterationcannot converge. To remedy the decreasing portion, the aggressor’s

switching window must be extended to infinity, as shown in Figure3.13, when calculating crosstalk noise between coupling nets, andhence Eq. (3.1) is mostly used. Without the decreasing portion, Eq.(3.1) is monotonically increasing for and and monotonicallydecreasing for Theorem 3 equivalently shows there is at leastone fixed point in D. The next step is to see if if there is somelooping structure in Eq. (3.1) (i.e. oscillation among points in the


iteration):

THEOREM 3.4 Given any initial conditions with

and the iteration in Eq. (3.11) converges.

Proof sketch: Without loss of generality, we assume affectsand affects and affects in Eq. (3.1). Any increase in

leads to decrease in and subsequently increase in whichin turns increases This excludes the possibility of oscillationin the iteration – that is, the iteration converges given any initialconditions with and

5.2 Computational ComplexityFor a discrete overlapping model, we have at most

O(L) coupling edges, where N is the number of nets, M is themaximum number of aggressor nets for any victim net, and L is thetotal number of the coupling edges in a circuit. In each pass of cal-culation of f (x), at least one coupling edge’s state is finalized suchthat the edge either contributes noise to its victim or not for all thesubsequent passes. If no coupling edge changes its state, there is noupdate to the noisy switching windows, so the iteration converges.For each pass, we need to examine O(N) nets against their O(M)aggressors to identify switching windows that overlap. Thus, the


total complexity is or. In [Sap00], an algo-rithm with complexity is suggested without counting thecost of checking against O(M) aggressors for detecting overlapson each net. In practice, this algorithm converges quite fast within3 to 5 iterations.

If an event-driven style of computation is used [CKK00b] (orChapter 4), the total complexity is still the same because there areO(N) nets in an STA timing graph to update, and for each updateto a switching window, we need to check it against O(M) aggres-sors to detect overlapping and trigger new update events. Thereare O(L) coupling edges, thus we need O(NML) operations foran event-driven style of computation. They conclude with an effi-cient algorithm similar to the approach of using the Gauss-Seidelmethod.

5.3 Convergence RateFor fixed point computation under a continuous overlapping

model, the convergence rate must be considered. For some lo-cal regions, there is a local Lipschitz constant L, such that L < 1,and the fixed point iteration converges. The convergence rate is de-termined by this local Lipschitz constant L. Provided is closeenough to the error is bounded by [EMU96]:

or

Since L can be greater than 1.0 in some local areas (see Section3.3.2), it could have some local divergent sequences as shown inFigure 3.14 for one dimensional case. However, the ending gameof convergence is still dominated by the convergent L value, whichis closest to 1.0.


5.4 Least Evaluation of Coupling RC NetworksIn practice, the computation of coupling RC networks is the per-

formance bottleneck for switching windows computation. DetailedRC extraction can generate an RC network for a net with over thou-sands of nodes. Efficient RC reduction and efficient coupling noisecalculations are required to speed up the calculation. However, aninitial switching window configuration also affects the number ofRC calculations. If each switching window starts from its noiseless(nominal) switching window, and the iteration process changes thecoupling edges’ state one-by-one as switching windows increase,no coupling RC network calculations performed during iterationfor noise will be wasted. In case of the initial condition startingfrom the maximum noisy switching windows, all of the couplingRC networks must be computed for the maximum delta delays.However, some of coupling edges might change its state from ac-tive to inactive in the process of iteration. The coupling RC networkcalculations for these edges are wasted compared with the noiselessinitial condition.


5.5 Speed-up of ConvergenceA number of speed-up methods for convergence have been pro-

posed [XCMS00, CKK00b, Sap00, ZSN01]. Most of the tech-niques are similar to Gauss-Jordan, Gauss-Seidel, or update (event)-driven calculations. A Gauss-Seidel style calculation for fixedpoint computation uses any updated information as soon as avail-able. For example, the iteration function can be modified as

Usually, is used if is not available at the moment whencalculating Techniques are thus focused on how to maxi-mize the use of instead of and the use of instead

ofAnother speed-up method is to replace the fixed point compu-

tation by a Newton-Raphson iteration, which has a quadratic con-vergence rate. However, computing each Jacobian matrix elementneeds O(N) operations, and the total complexity to build the Jaco-bian matrix is Inverting the Jacobian matrix might need asmany as operations besides the original computation cost off(x). Moreover, singularity problem should be handled with care.Aitken method [EMU96] can be applied to each arrival time toquickly achieve local convergence. But neither of the two methodsguarantees finding the tightest noisy switching windows.

6. ConclusionSwitching windows computation can be well-controlled by care-

ful selection of the underlying models. In this chapter, we show,formulate, and prove the various numerical properties from a nu-merical fixed point computation perspective. These could serve asa theoretical foundation for switching windows computation.

Chapter 4

SPEEDING-UP SWITCHINGWINDOW COMPUTATION

After spatial and electrical pruning, temporal pruning may be ap-plied. The key element of temporal pruning is to compute switchingwindows, which are an important technique to accurately calculatecrosstalk effects as discussed in Chapter 3. In this chapter, wepresent and compare multiple scheduling algorithms to computeswitching windows for static timing analysis in the presence ofcrosstalk noise. We also introduce an efficient technique to evalu-ate the worst case alignment of multiple aggressors.

1. Introduction

Static timing analysis has been studied for more than a decade[Sas93, DKMW94, DKM93]; however, these studies have not in-volved any crosstalk coupling analysis. Recently, [She98b] pro-vides a design methodology to avoid coupling noise and addressesstatic analysis of noise at the transistor level. [Kir97] analyzes thefunctional aspect of how signals couple together. In [CK99], a for-mulation is proposed to calculate the maximum noise, but it onlyapplies to small circuits due its complexity. [GRP98] proposes analgorithm to calculate the worst case aggressor alignment due tocoupling. [CKK00c] shows that the Miller factor upper bound is


3X instead of 2X for the maximum coupling delay. For a designin DSM, the functional aspect of crosstalk coupling is almost im-practical to analyze. STA with crosstalk coupling effects serves avery practical and efficient way to verify a circuit design that willnot violate any timing constraints TCE00].

In this chapter, we address the problem of static timing analysisby considering coupling effects. Unlike traditional STA, the criticalpath delay cannot be obtained simply by topological traversal andfunctional analysis of false paths. Switching windows, withinwhich a node makes transitions, are key to determining whether thecoupling noise can affect timing. Only when two coupling nodeshave overlapping switching windows can their timing change due totheir coupling. However, switching windows depend on the signaltiming itself, so there is a circular problem to resolve. Therefore, wepropose an event-driven algorithm to solve this mutual dependencyproblem, resolving cycles through causality. We assume a singleworst case driver resistance and apply superposition of waveformsextensively. This is a conservative assumption. The result is anupper bound of the actual switching window.

This chapter is organized as follows: First, we review necessarybackground and definitions. In Section 4.3, we discuss the align-ment of multiple aggressors for worst-case delay. In Section 4.4,we present an event-driven algorithm in detail, including proof,event scheduling techniques, complexity analysis, and efficiencyissues. In Section 4.5, we show some experimental results.

2. Background and DefinitionsRecall that for a pair of coupling nodes, a node which suffers

from the coupling noise is called a victim node, and other nodesthat contribute the noise are called aggressor nodes. The worstcase delay of a node(Figure 4.1) is the minimum or maximumdelay considering all topological minimum or maximum delay de-pendencies, and the worst case crosstalk coupling. For example,

Speeding-Up Switching Window Computation 63

the worst case timing can be computed using zero coupling capac-itance for min delay and 3X coupling capacitance for max delay,respectively. The nominal delay of a node is defined as the delaycalculated when each aggressor is quiet – that is, using 1X couplingcapacitance for delay calculation. The worst case switching win-dow (Figure 4.1) thus forms the outer bound of the actual switchingwindow, and the nominal case switching window forms the innerbound.

The coupled delay of a node (Figure 4.2) is the delay due tothe aggressors’ coupling of the node. It is computed from theaggressor’s maximum coupling noise to achieve the min or maxdelay. The propagation delay of a node (Figure 4.2) is the delaydue to the previous stage delay. It is computed from the previousstage coupled delay plus the cell delay.


Given a node the min propagation delay is

and the max propagation delay is

where denotes the min(max) propagation delay,is the set of fanins of node is the min(max) node-

to-node delay, and denotes the min(max) coupleddelay of node

Suppose the driving resistance of the aggressor is linear. Coupleddelay can be calculated as a superposition of the victim waveformand the coupling noise waveform from the aggressor nodes.

The min sensitive window (Figure 4.3) of a node for the mindelay is from the rising point to the threshold point of the transition.In this period, the coupling noise can speed up the transition andthe delay might be reduced. This period is used to determine themin delay variation because the possible range for a signal to besped up is just within this window. Similarly, the max sensitivewindow of a node for the max delay is from the threshold point tothe end point of the transition. In this period, the coupling noisemight slow down the transition and the delay can be increased.

2.1 Piecewise Linear WaveformFor ease of calculation, we assume piecewise linear waveforms.

The number of linear segments can be used to trade accuracy and


run time for modeling waveforms from circuit level characteriza-tion. Moreover, they can be manipulated to do waveform superpo-sition and compute an envelope waveform, as described in Section4.4. All of the computational complexity is proportional to thenumber of linear segments in the waveforms.

3. Multiple Aggressor Alignment ProblemIn this section, we will discuss how to determine the worst case

alignment given multiple aggressor waveforms and a victim wave-form. The problem is to align aggressor waveforms to get themaximum or the minimum delay on the victim node. Becauseeach node has a switching window, it restricts the time for a nodeto make transitions. These switching window constraints restrictthe range where a worst case alignment can occur to the rangeswhere these windows line up. In [GRP98], the authors prove thatthe worst case delay for a pair of aggressor and victim nodes is whenthe peak noise of the victim aligns up to the switching threshold ofthe victim’s transition waveform. Based on their result, we addressthe case where multiple aggressors are aligned, which is commonin any STA scenario. We propose an envelope waveform to performthis computation, something relatively easy to compute where thecomplexity is simply proportional to the number of linear segmentsin all of the waveforms.

In a physical layout, there could be several aggressors couplingto a victim node, and each of these is constrained by some switchingwindow.

Consider the waveforms of two nodes switching in opposite di-rections, as shown in Figure 4.4. The problem is equivalent to slid-ing or convolving the aggressor waveform subject to the switchingwindow constraint to achieve the maximum delay on the victimnode. Specifically, we have to find the scenario that maximizes the

point in Figure 4.4 [GRP98]. At this point, the waveform of thevictim touches the threshold point of the next stage logic gate, mak-


ing a sharp transition between logic states. If the coupling noisewaveform continuously slides from the left bound of the aggres-sor switching window to the right bound, as shown in Figure 4.5,this waveform envelope forms a range and magnitude of noise thatcould possibly affect the victim waveform. After superposition ofthis envelope and the victim waveform, the resulting waveform isthe worst case waveform envelope of the victim node. The worstcase delay can be found on the last point crossing the switchingthreshold (usually 0.5 Vdd). The bold lines in Figure 4.5 show thenoise peak and the corresponding aggressor transition to create thisworst case timing.


THEOREM 4.1 The technique described above can find the worstcase alignment which creates the worst case delay on a victim node,given the switching window constraints of multiple aggressors.

(Proof sketch:) The victim envelope waveform actually depicts theminimum voltage values that the victim waveform can possiblyreach over time. Due to the superposition assumption, we can su-perpose each aggressor envelope waveform on the victim envelopewaveform one by one. The resulting waveform envelope is the finalworst case voltage that can be reached over time. By tracing thisenvelope waveform, the worst case delay can be obtained.

4. Coupling Delay Computation in Presence ofCrosstalk Noise

In today’s technology, RC delay calculation consumes a majorportion of the total computation time for delay calculation. Typi-cal RC delay calculation algorithm involves effective capacitancecomputation [QPP94] and model order reduction of the RC inter-connect [SNEZ97a]. Cell delay computation is a relatively simplecomputation often via a table lookup. Waveform superposition isanother complexity that adds to the whole coupling computation.Therefore, our algorithm is optimized toward reducing the numberof coupling computations.

4.1 AlgorithmThere are two types of events in our event-driving algorithm. A

coupling event is the event triggering calculation of the couplingwaveform envelope based on the victim and aggressors’ waveformsto derive the coupled delay. A driving event is the event triggeringcalculation of the propagation delay based on the previous stages’coupled delays.

Given a circuit with the coupling noise for each victim and ag-gressor pair, and the waveform that has been characterized, we


propose the following event-driven algorithm to compute effec-tive circuit delay: Coupling Delay Calculation by Event-Driven

Updating

1

2

Schedule a coupling event for each node.

Pop an earliest event until the queue is empty according to thecurrent status of the circuit

(a) If it is a coupling event from node B to node A, as shown inFigure 4.6, compute the superposition coupling waveformto get the coupled delay of node A. Schedule the next stagedriving events for node D.

(b) If it is a driving event from node C to node A, update thepropagation delay of the current node A, schedule a drivingevent from node A to node D, force a coupling event onnode A to recompute the coupling effect, and check if nodeA attacks the adjacent nodes again. Schedule the couplingevents for attacked adjacent nodes – for example, a couplingevent from node A to node B.

Our algorithm keeps track of all old delay values. If a coupling or adriving condition does not change, it is not necessary to recomputeor schedule an event.


4.2 Convergence of Our AlgorithmIntuitively, our algorithm tries to maintain a consistent system

that each node has its propagation min and propagation max delays,as defined by Eq. 4.1 and 4.2, and the coupled delay conforms tothe worst case alignment of its aggressor waveforms, as describedin Section 4.4. Our algorithm corrects the local inconsistency ofdelays, and issues the related delay perturbation event to the nextstage delays or the adjacent coupling delays.

THEOREM 4.2 Given an accuracy requirement, the algorithm de-scribed above converges to a consistent value for each delay in acircuit using a finite number of steps.

(Proof:) If there is a coupled delay inconsistency or a driving delayinconsistency on a node, our algorithm, as described in Section 4.4and Eq. (1) or (2), recomputes it according to the coupling nodes orthe incoming driving delays. This algorithm updates its coupled orpropagation delay, and issues events for updating related couplingnodes and the next stage nodes. This maintains local consistency.Note that we assume each isolated sub-circuit group has at leastone input to initiate the event-driven process. Initially, we assumethe propagation delay for each primary input is fixed.

We now prove the algorithm’s convergence. Supposing there isno coupling, we can compute the propagation delays in a topologi-cal order in one single pass. However, due to crosstalk coupling, avictim node might have coupling from its transitive fanouts whoseswitching windows cannot be finalized at the time when we cal-culate the propagation delay of the victim. Suppose one of theaggressor nodes is a transitive fanout of a victim node and theirswitching windows overlap each other. Figure 4.7 shows thesewaveforms. We will prove these converge to a single point. Asaggressor moves from left to right, we can plot as a func-tion of as shown in Figure 4.8, where T is a shorthand for

is the peak noise from aggressor is a transitivedelay from node to node and the propagation delay of node


is equal to:

This function means that it can be sped up to the lower bound ofand it has an upper bound of T, which is not sped up. In

addition, Eq. 4.3 has a lower bound when is equal to zero. Thisconvergence process is shown in Figure 4.9. If at first isat point a, the value of can be obtained by Eq. 4.3. Then,

the value of is obtained by the function shown inFigure 4.8, which is point b. It will continue this process to pointsc, d, and e, until it converges to the cross point z, which meets theaccuracy requirement.

Moreover, the slope of the middle linear segment of func-tion can be shown to be greater than 1, which means we can haveonly one cross point, since Eq. 4.3 is also linear. Thus, the itera-tion process must be able to improve towards convergence. Withan accuracy requirement, we can reach this requirement in a finitenumber of steps.

Note that the iteration occurs when the aggressor’s sensitive win-dow overlaps the victim’s switching threshold point, and the ag-gressor is one of the transitive fanouts of the victim. As the transi-


live delay is shorter and the aggressor’s slew is longer, it is likelyto overlap and increase the computation time.

For the max delay, because of the conservative assumption thatthe aggressor can switch at any time point within the switching win-dow to create the worst case coupling, the result of the event-drivenalgorithm always takes the worst case timing, which is conservativeand no iteration is necessary. The function has two types,as shown in Figure 4.10.


4.3 Properties of Our AlgorithmIt is interesting to note that our algorithm can reach the same

result even if the initial values (propagation and coupled delay)are completely different. That is to say, our algorithm results in avery robust calculation. Different initial value settings only affectthe number of events and calculation time. Typically if the initialvalues are closer to the final converged result, the computation timeis reduced, because the algorithm converges in fewer steps.

4.4 Event PruningAny event causes a series of computations to update the whole

system. However, coupling and driving events might not be neces-sary if they will not change any delay value of a circuit. Therefore,it is desirable to reduce the number of events issued to speed up thecomputation.


Coupling could be considered harmless if two signals switch withnon-overlapping timing windows – that is, due to the temporal iso-lation, the two nodes that are physically coupled will result in nocrosstalk noise effect. We can also compute the lower bound of mindelay and upper bound of max delay by 0 or 3X coupling capac-itance. It can be done before running the event-driven algorithm,and provides valuable information for pruning events.

When a node changes its propagation delay, our algorithm issuesevents based on the following facts:

1

2

If the coupling computation in some previous event still keepsthe same condition for coupling, it does not need to schedulethis event, since the same coupling condition results in the sameamount of coupling noise.

When the coupling condition changes, a coupling event mustbe issued to update the corresponding coupling nodes, and thepropagation delay of a next stage can change accordingly, so adriving event is issued.

The event-driven type of calculation makes the computation veryrobust and efficient with reduced re-computation.

4.5 Scheduling TechniqueScheduling is a key for the efficiency of convergence. We can

reduce complexity by an order of magnitude with careful arrange-ment of events. We identify the following scheduling approaches:

Dynamic Event Time We schedule events based on the right handbound of sensitive windows, defined in Section 4.2, and dynami-cally sort the events according to the current circuit status (delayvalue). Intuitively, it forms a sweep timing line across the cir-cuit. If any event occurs earlier in the event time, our eventalgorithm schedules it first and continues iterating on its relatedevents until it converges.


Static Event Time We schedule events based on the right handbound of sensitive windows. No dynamic sorting of events isperformed. When two events have the same time, we scheduleevents based on the topological order of the nodes.

Smart Global We maintain a flag to identify whether one nodemust be updated or not. At each pass, each node is examinedand processed if necessary. The updated delay will propagate toits coupling nodes and next stages. The event pruning techniqueis also used to reduce the number of updates. If no update isneeded throughout a pass, the computation has converged.

5. Experimental ResultsWe demonstrate our algorithm on a 233MHz PC with 64M bytes

of memory running the Linux operating system. We benchmarkour algorithm on the ISCAS85 combinational circuits. For everycircuit, each node is presumed to have four randomly chosen cou-pling nodes. The coupling noise between each pair of aggressorsand victims, and the slew on each node are pre-characterized or es-timated. We also vary these parameters with different schedulingapproaches to test the efficiency of our algorithm.

The total run time for all of the ISCAS85 11 combinational cir-cuits takes only 7.09 seconds. It is observed that 21.9% of thenodes, on average, are recomputed for coupling calculation, whichmeans only 21.9% of the nodes have to be calculated twice for thecoupling to obtain to the final delay value. Table 4.1 shows thisresult, where the first column is the name of circuit, the second col-umn is the number of nodes, the third column is the total number offanouts, which is equal to the number of driving edges, the fourthcolumn is the number of coupling computations, the fifth column isthe percentage of re-computation of coupling, and the last columnis the run time.


With different initial values, the number of coupling compu-tations can have a 22% difference, as shown in Table 4.2. Thefirst column shows “W”: factor, which is the factor of how closethe initial value is to the worst case value: 0.0 represents usingthe nominal delay value, and 1.0 represents using the worst casevalue for initial values. The second column is the total numberof coupling computations for all 11 combinational circuits fromISCAS85. The third column is the percentage of re-computations,and the last column is the run time.


We also implement the ISCAS combinational circuits in atechnology. The result is as shown in Table 4.4, where the first col-umn shows the circuit name, the second column is the number ofnodes in the circuit, the third column is the number of propagationedges, the fourth column is the number of the coupling edges, thefifth column is the number of coupling computations, and the lastcolumn is the run time. In Table 4.3, we compare different schedul-ing approaches in terms of total run time on all of these circuits.The Smart Global scheduling approach is the winner among all ofthe scheduling approaches.


6. Review of ConservativismIf the initial switching windows are infinity, according to Section

3.3.4, we can get upper bounds or conservative results through outthe iterations and converge into a final solution. The schedulingmethods proposed in this chapter can speed up the iterations. If theinitial switching windows begin from the nominal ones, we cannotget any valid upper bound until the iteration reach the fixed pointdescribed in Chapter 3.

7. ConclusionUsing a flexible and practical waveform model, We propose a

robust and efficient algorithm to compute the coupling delay effecton static timing analysis. This approach can be directly imple-mented in a very practical industrial tool for advanced static timinganalysis targeting very deep submicron designs.

Chapter 5

REFINEMENT OFSWITCHING WINDOWS

Chapter 4 introduced a technique to compute switching windowsto improve the computation time of crosstalk calculation. In thischapter, we introduce a method to further reduce pessimism ofcrosstalk analysis based on time slots. For crosstalk noise calcula-tions, computing switching windows of a net helps identify noisesources accurately. Traditional approaches use a single continu-ous switching window for a net. Under this model, it is assumedthat signal switching happens at any time within the window. Al-though conservative and sound, this model can result in too muchpessimism because the exact timing of signal switching is deter-mined by a path delay up to the net (i.e. the underlying circuitstructure does not always allow signal switching at arbitrary timeswithin the continuous switching window). To address this inher-ent inaccuracy of the continuous switching window, we propose arefinement of the traditional approaches, such that signal switch-ing is characterized by a set of discontinuous switching windowsinstead of a single continuous window. Each continuous switchingwindow is divided into multiple windows, called time slots, andthe signal switching activity of each slot is analyzed separately tocalculate the maximum noise more accurately. By controlling thesize of a time slot, we can trade off accuracy and runtime, whichmakes this approach scalable for large designs. We have confirmed


by experiments on industrial circuits that up to 90% of the noiseviolations detected by the traditional approach can be unreal.

1. IntroductionRecall that crosstalk noise affects timing by either decreasing

or increasing the delay. If the adjacent nets are quiet, there is nocrosstalk noise. Therefore, it is important to identify the switch-ing window (or timing windows), so that if there is no overlap ofswitching windows between two coupling nodes, we can immedi-ately conclude that there is no timing variation, thereby reducingthe analysis pessimism.

Typically, the switching windows considered in the literature[Sap99, , TCE00, ARP00, CKK00b, XCMS00, ZSN01,CKTK02] are continuous (see Figure 5.1). They are a timing in-terval from the earliest arrival time to the latest arrival time of anet. However, because the number of possible timing paths to anet is bounded by the number of topological circuit paths, the ar-rival times are typically not continuous inside a switching window(see Figure 5.2); instead, they are discrete arrival times. ConsiderFigures 5.1 and 5.2. Figure 5.2 captures switching activity moreaccurately by discontinuous windows, while Figure 5.1 is an ap-proximation of Figure 5.2 by a continuous window. Suppose net Aand net B are aggressors to be aligned for the maximum noise. Asshown in Figure 5.2, there is no switching window overlap. How-ever, if Figure 5.2 is approximated by Figure 5.1; the two windowshave overlap, resulting in a false alignment and a pessimistic noiseestimation. The goal of this chapter is to take advantage of dis-continuous switching windows to calculate crosstalk noise moreaccurately.

Using a fixed delay model, the maximum number of discrete ar-rival times at a net is equal to the number of topological paths tothe net. To simplify the analysis, we ignore functional dependencyin the following discussion throughout this chapter. To avoid han-

Refinement of Switching Windows 81

dling a potentially exponential number of discrete arrival times, weuse a time slot approach, where a continuous switching window isrefined as a set of time slots of the same size. Thus, the size of atime slot is an effective scaling factor to trade off analysis accuracyversus speed and capacity. As the analysis resolution gets finer,more maximum noise can be precisely justified.

The rest of this chapter is organized as follows. In Section 5.2, weintroduce the formulation and algorithmic aspects of our approach,and discuss the theory behind it. In Section 5.3, we address theresolution issues. In Section 5.4, we show the experimental re-sults. In Section 5.5, we investigate a refinement of the proposedmethod, where slew effects on the maximum noise are modeledmore accurately.

2. Formulation and AlgorithmRecall that victim is a net that suffers from a noise effect, and an

aggressor is a net that contributes noise. Their roles can changedepending on the context. Using the notations of Chapter 3, Thelatest and the earliest arrival times of net can be written as:


and:

respectively, as shown in Figure 5.3. The traditional continuous

switching window model defines the switching window from timeto timeLet be the size of a time slot, and be a Boolean

variable defined as follows:

is used to record if net has any signal arriving at time slotFor multiple arrival times of a net the corresponding arenon-zero. It can be recursively computed as:

where is a logical “OR” operator and This isto say is non-zero if any of preceding stages has an arrival timewithin appropriate time slots. Strictly speaking, we have to checktwo time slots:

If the gate delay is considered within a range thetime slots to check are:


The nets are visited in the same order as in the continuous switch-ing window calculation or longest path calculation: a depth-firsttraversal of the direct acyclic graph (DAG). Assuming that aggres-sors in the same time slot can align to create the maximum noiseon the victim net we can then calculate the maximum noise atnet as:

where L is the longest path delay or the maximum arrival time ofthe circuit, and is the noise effect from the aggressor netto the victim net Although the slew rate of net might not be thesame for all the time slots, is calculated using the fastest slewavailable on net to ensure a pessimistic analysis. We can further

reduce the search range down to the interval whereis the minimum arrival time of all the aggressors of net andis the maximum arrival time of all the aggressors of net –

that is, Eq. 5.4 becomes:

2.1 Arrival Time Uncertainty in InterconnectDue to a signal transition through an interconnect, arrival times

can be quite different between the driver and the receivers of a net.This interconnect delay can be captured as uncertainty of the arrivaltime for the net. Thus, the switching window of a net must be spreadout to cover the uncertainty in interconnect signal propagation. Forexample, suppose the arrival time is l000ps at the driver of a net, ifthe interconnect can take up to the maximum of 200ps to propagateto a receiver of the net, we have to mark the arrival time slots froml000ps to 1200ns in the switching window of the net. During thistime interval, the victims of this net might have crosstalk effects.


Let be the maximum interconnect delay on net We mustspread out the interconnect as:

where is the modified arrival time slot for net The maxi-mum noise is thus revised as:

Eq. 5.1 needs to be revised as:

Note that still remains the same, and does not affect the earliestarrival time.

2.2 Switching Window DensityCompared with the traditional approach using continuous switch-

ing windows, the time slot approach can help reduce analysis pes-simism. The effectiveness strongly depends on the switching win-dows’ density, which can be defined as the ratio of the number ofnon-zero time slots to the total number of time slots in a switch-ing window. The traditional continuous switching windows have adensity of 1 by definition. This density measure is a very good met-ric of how effective the time slot approach reduces the pessimismof noise analysis. If the density is close to 0, the switching windowtends to be very sparse, and the time slot approach can cut downmost of the pessimism in the maximum crosstalk noise calculation.

2.3 Input Timing UncertaintyTypically, the arrival time of an input pin of a chip is given not as

a constant but a bounded timing range. It could represent the timinguncertainty due to the process, voltage, or temperature variation.


Let I be the index set of input nets. For we have

where and are the earliest arrival time and the latest arrivaltime, respectively. The larger the timing uncertainty, the denser theswitching windows. Therefore, reducing the timing uncertainty atthe inputs can increase the effectiveness of our approach.

2.4 ComplexityGiven the N nets and the total M fanouts of nets in a circuit (simi-

lar to a direct acyclic graph with N vertices and M edges), the com-plexity of calculating the arrival time slots is by Eq.5.3. The dominant operation is actually the maximum noise cal-culation by Eq. 5.5, which has the complexity whereP is the maximum number of aggressors of a net, or equivalentlythe maximum cardinality of where

2.5 Implementation ConsiderationSince are Boolean variables, we can compact them into a

32-bit integer. can be easily represented by a bit map. The timeslot ranges from to for a net This approach has veryefficient memory usage with a slight speed penalty.

3. Resolution and Truncation ErrorsThe size of the time slot is an important factor for the analysis

accuracy. We test different slot sizes on a small circuit with 8828nets and 7956 cell instances using technology, and checkthe maximum noise peak over 20% of power voltage. Table 5.1shows the slot size effect, where the first column shows the slotsize, the second column shows the number of noise violations andthe third column shows the switching window density. The second


“Continuous” row is the traditional continuous switching windowmethod. In general, a smaller slot size can result in fewer noiseviolations. However, notice that the slot size 90ps generates moreviolations than the slot size l00ps.

Consider the case in Figure 5.4, where the time slot sizes are20ps and 30ps, respectively. Suppose the two aggressors’ arrivaltimes are 25ps and 35ps, respectively. If the time slot size 20ps isused, we can align these two aggressors by assumption. If the timeslot size 30ps is used, these two aggressors cannot align to createthe maximum noise. Therefore, the finer time slot does not always


imply fewer noise violations. However, if the size of a coarser timeslot is a multiple of a finer time slot’s size, this can be avoided. So,as long as the time slot size is continuously divided evenly, as inTable 5.2 (l000ps l00ps 10ps), this problem disappears.

4. Experimental ResultsWe conducted experiments on several industrial circuits of sig-

nificant size. Table 5.2 shows the results. The first column is thecircuit name. The second column is the number of nets in that cir-


cuit. The third column is the number of cell instances. The fourthcolumn is the time slot size, where “Cont.” represents the tradi-tional continuous switching window approach. The fifth column isthe switching window density. The sixth column shows the num-ber of noise violations, where 40% of VDD is the threshold. Thelast column shows the run time on a Linux machine with 1.26GHzCPU.

From Table 5.2, the number of noise violations can be reduceddramatically by 90% for designW and 43% for design A. The runtime penalty was a slight increase. In fact, the continuous switchingwindow approach could take a longer run time due to the processingof an excess of noise violations. A finer time slot can reduce thenumber of the noise violations. However, the amount of reductiontends to decrease significantly after some finer time slots.

5. Consideration of Slew RatesThe approach proposed above uses the fastest slew at net in the

computation of Basically, we then assume that this maximumnoise effect is achievable in any time slot in the entire switchingwindow. This is a conservative assumption, but a slew at net couldbe much larger than the fastest slew in some time slots, resultingin pessimism. We can incorporate this effect by propagating, andmaintaining the fastest slew of each time slot, and computingof each slot based on the slew. Let be the minimum orfastest slew in time slot of net The propagated slew model isthus written as:

where The maximum noise is calculated as:

where is a noise peak function of slew rate, repre-senting the noise effect from the aggressor net to the victim net


Note that this approach has a heavy speed and space penaltybecause the bit pattern representation for cannot be used anylonger and we must record slew information in each time slot.The number of computations of interconnect and gate delay is pro-portional to This is not considered practical for multimillion-gate designs.

6. Property of Time Slots and Conservativism

The approach in this chapter is actually discretization of a switch-ing window. If this approach is applied to switching window cal-culation as we did in Chapter 3 and 4, clearly, it can create multiplesolutions and even oscillate during the switching window calcula-tion, because we use a Boolean variable to record if a signal arrivesat a time slot. A possible improvement is to use multiple con-tinuous switching windows for a net. The overlapping switchingwindows should be merged to reduce the complexity. However,as the number of possible timing paths may be exponential, thisapproach implies a costly run time penalty.

To make this time slot approach conservative, we need to makesure every timing uncertainty source (e.g. Section 5.2, 5.2.1 and5.2.3) is considered in the time slot marking procedure. For exam-ple, if a net has a transition time which is larger than the time slotsize, we need to mark every time slot that has overlapping with thetransition. Another option is to store a fractional number instead ofa Boolean variable in each time slot to record this partial transitioninformation.

7. Conclusion

Switching windows can be refined by time slots to improve ac-curacy. Our experiments show that up to 90% of potential noiseviolations detected by continuous switching windows can be ex-


cluded by this approach. Moreover, the size of a time slot canbe controlled to trade off accuracy for speed and capacity, whichmakes this algorithm scalable for industrial-sized circuits.

Chapter 6

FUNCTIONAL CROSSTALKANALYSIS

We now consider the use of functional information in crosstalkanalysis. The goal of this chapter is to develop an algorithm andnoise analysis flow that provide an accurate and conservative ap-proach to functional crosstalk analysis. In particular, this chapterproposes an approach to identifying a pair of vectors that exercisesthe maximum crosstalk noise.

1. Introduction

The current approaches to interconnect crosstalk analysis are basedon identifying the spatial relationship between two coupling sig-nals, and then adding a static analysis of the temporal relation-ship [She98a][Kir97]. The use of static timing information in thismethodology is similar to the static timing analysis without false-path elimination, so it might lead to an overly pessimistic estimationof the actual noise in the circuit. In the case of false noise analysis,the practical impact is wires’ re-routing or signal drivers’ modifi-cation. On the other hand, a greater drawback of static analysisapproach is that it might fail to correctly analyze signal glitches,which can also be responsible for erroneous switching in the circuit.


One key to improving the accuracy in static timing analysis is toadd functional information and thereby compute the “true delay”of the circuit. Similarly, we believe the key to improving noiseanalysis is also to add functional information to the temporal. Byanalogy, we call this computing the “true noise” of the circuit.

In this chapter, we will present a method for searching for thevector pair which maximizes the crosstalk noise on a given net for acombinational sub-circuit. This search uses the timing informationfor the relevant signals together with the functional information ofthe gates computing the signals. These two together form a tighterupper bound, and the input vectors that exercise the maximumcrosstalk noise can be identified.

In Section 2, we review some useful methods and related workfor crosstalk analysis. In Section 3, we introduce some techniquesto prune this large vector search space. In addition, we will discussseveral models with respect to their complexity, efficiency, andaccuracy for computing the noise bound. In Section 3, we explainthe vector search algorithm for the maximum crosstalk noise isexplained. Section 4 shows the experimental results, and in Section5, some areas for improvement are discussed.

2. Approaches and Related WorkThe most straightforward approach to finding a vector pair thatmaximizes the noise on a given net is to exhaustively simulate allinput vector pairs. This is rarely computationally feasible. There-fore, an accurate and computationally efficient method needs tofind the vector pair that stimulates the maximum noise. Insteadof exhaustive logic simulation, we formulate this problem as aBoolean Constrained Optimization Problem (BCOP) to solve itexactly. Moreover, our approach can be extended to a generalvector-search scheme, which can be used to search for the vectorscausing the maximum IR drop or the maximum power consumption[DKW92].

Functional Crosstalk Analysis 93

We will begin by reviewing prior work that has some elementsin common with the the problem of maximum noise analysis. In[RIZK94], the authors propose a multiple-value logic to generatean input vector to test cross coupling faults. However, there is notiming involved, and thus it is unable to find the real noise bound– only a pair of vectors for circuit testing.

In [DKW92], the authors provide an approach to finding a vectorpair which maximizes power dissipation. This problem shares acouple of elements in common with our own: function and timingmust be integrated, and failure to analyze glitches will lead to anon-conservative procedure. Unfortunately, the search approachshown in [DKW92] is somewhat primitive and is unable to scaleto the size of problem we want to consider.

The use of Timed Boolean Functions (TBF) [LB94] has also beenproposed for computation of the vector pair that causes the maxi-mum number of transitions. This is related to our problem, but it isnot equivalent and no strategy for noise analysis is reported. Theunderlying computational mechanism is based on Binary DecisionDiagrams (BDDs) [Bry86]. Also, basing his approach on BDDs is[Kir97]. This work does focus on noise analysis and does a nice jobof describing the relationship between spatial, temporal, and func-tional elements of noise analysis; however, in [Kir97] results arecited on only very modestly sized circuits (< 1000 gates). BDD-based techniques are necessarily limited because many circuits donot have compact BDD representations.

Other recent work has used Timed Automata to model couplingdelays [ea97]; however, these approaches are even more computa-tionally expensive than the BDD-based approaches.

In conclusion, although a variety of work has been performedthat is relevant to this problem, there is still a need for an accurate“true noise” analysis approach that is computationally efficient.This is the goal of this chapter.


3. Vector Pair Searching Algorithm3.1 Overview

Our proposed approach is based on a similar method of functionaltiming verification [DKM93, DKMW94, Sas93]. We need to setup timed Boolean variables for each node at some time points andconjunct the gate characteristic functions, which represent all thepossible logic combinations of a gate. According to the allowablenoise level to assign the weights of some Boolean variables, thevector pair search problem can be formulated as a BCOP, in whichwe find some assignment to satisfy the constraints and maximizean objective function in terms of these Boolean variables. In thefollowing, we describe each step in detail.

3.2 BCOP: Boolean Constrained OptimizationProblem

Given an objective function,

where and we wantto maximize such that it satisfies the constraint:

where The constraint can bewritten in Conjunction Normal Form(CNF). This problem is similarto the BCP.


For weighting a switching on the aggressor nets, the cost func-tion might not be linear. Moreover, if timing is considered, someweighted terms must be represented as a complex conjunction ofsome circuit variables. In such cases, we implement a branch-and-bound algorithm to address this special objective function evalua-tion.

3.3 Constructing Circuit via SATTo represent a combinational circuit, we use the characteristic func-tion of each gate and set up a variable for each node. Conjunctingthese characteristic functions together, we obtain a characteristicfunction to represent the whole circuit [Lar92][SBSV96]. Thesecharacteristic functions are represented by CNF clauses. A circuitis functionally consistent if and only if the CNF clause can be sat-isfied. Namely, we can find a valid assignment for each variable,which means there is a valid logic combination of the inputs, theoutputs and the internal nodes of the circuit.

For example, in Figure 6.2, this AND circuit can be characterizedby

is equal to one if and only if X, A, and B are a valid variable

assignment for AND gate operation. Consider the circuit in Fig-ure 6.3. We can conjunct the characteristic functions of all gatestogether to obtain the characteristic function of this whole circuit.


Thus, the stable state of this circuit must satisfy the constraint above( equals 1).

3.4 Maximum Noise under the Zero-Delay ModelIn the zero-delay model, all the gates and the interconnect are as-sumed to have zero delay. Therefore, the maximum noise occurswhen all the aggressor nets make transitions in the same direction.We can then investigate the correlation between signals to find themaximum number of the opposite transitions, which maximizesthe crosstalk noise under the zero-delay model.

For a single victim net, given the coupling capacitance betweeneach aggressor net and the victim net, we can obtain the maximumnoise by:

1 Setting up two variables for each node: one variable denotesthe value of time 0, and the other is for time We denote avariable for node X as and respectively for time 0 andtime

2 Build the characteristic function into the CNF clause for twosets of variables. For the circuit in Figure 6.3, we have:


Find the maximum (or minimum) weighted sum of each ag-gressor’s variable, where the weighting is proportional to thecoupling capacitance or the delta voltage on the victim causedby the aggressor’s switching. The phases are assigned accord-ing to the switching direction on the aggressor nets. Supposewe have node B and Y as aggressors of node Z in Figure 6.3.The objective function to maximize or minimize is:

3

where is the delta voltage at node Z caused by node Bswitching, and is the delta voltage at node Z caused bynode Y switching.

Set up the initial condition that makes the victim net static – thatis, the victim net stays on the same logic state even after thesecond vector is applied. For the circuit in Figure 6.3, we have:

4

3.5 Fixed Delay Circuit Construction via SATThe zero-delay model, in general, does not give an accurate noisebound, and it often gives almost the same scale of the noise boundas the static noise analysis. Thus, timing information is importantto be considered in this vector search procedure to obtain a tightermaximum noise bound.

Timing information can be included by introducing timed Booleanvariables, with which we can represent the logic values of a nodeat different time points.

Also, it is assumed that there are 2 input vectors to apply to theprimary inputs of a circuit: one vector at time minus infinity, andthe other at time zero. The former vector drives each node of thecircuit into a known state no matter how long the circuit delay is,and the latter exercises the maximum crosstalk noise. This scheme


can be easily generalized for multiple vectors or extended to theother applications.

3.5.1 Using Timed Boolean Variables

The timed Boolean variable, used to represent a logic state for anode at some time point, is a mapping The negativetimed Boolean variable denoted by is the complemented variableof

Suppose the circuit in Figure 6.4, where is evaluated.

is abbreviated as Since the delays between X to Zand B to Z are 2, we can represent the gate on the right by thecharacteristic function:

Since B is a primary input, only two values are applied. isequal to We rewrite the above characteristic function as:

Similarly,

A and B are primary inputs, and There-fore,


The whole circuit characteristic function for becomes

Thus, can be sensitized by assigningThis can be obtained by solving SAT of the above

characteristic function, Eq. 6.4. The entire waveform is as shownin Figure 6.5.

3.5.2 Translation of Maximum Coupling Effects into an ObjectiveFunction

After setting up the circuit characteristic functions, we can for-mulate an objective function that represent every possible couplingscenario. A rising switching at time for node can be translatedinto where the time resolution is assumed to be 1.0. Simi-larly, a falling switching at time for node X can be translated into


Suppose node X and node Z attack node Y (not shown inthe figure) at time 3 in Figure 6.4. The maximum coupling functionfor rising attacking is

Because node X has no signal arrival time between time 0 to time2, we can conclude by analyzing all of thepossible topological path delays. Similarly, we can sayThe objective function is reduced to:

This is equivalent to say only node X can switch at time 3. Mean-while, is also constrained by:

For a node the maximum rising crosstalk noise is:

is the aggressor of node Note that a rising and a fallingcrosstalk noise at the same time caused by two different aggressorscan cancel each other in terms of the coupling effects. Thesevariables should be constrained to match the circuit behavior as theprevious section described.

3.5.3 Boolean Constrained Optimization Problem

The formulation then consists of an objective function which istargeted for the maximum crosstalk noise, and a conjuction of SATformula to represent the circuit logic behavior considering logicgate delay. This formulation becomes a Boolean Constrained Op-timization Problem (BCOP).

The Boolean constrained optimization problem is equivalent toa BCP by transforming the objective function into a cost function,and then minimizing the cost function. A straightforward method


to solve this problem is a branch-and-bound method, while manyBCP techniques have been proposed [Cou96].

Some heuristics might be possible to reduce the complexity, suchas a coarse quantum time, relaxing SAT formulation, or partialvariable collapsing.

3.5.4 Discrete Required Time Analysis

In general, the required times under the fixed delay model are notcontinuous – that is, the possible combinational path delays arefinite, resulting in discrete path delays and hence the discrete re-quired times. Therefore, we can analyze these possible discreterequired times to reduce the number of timed Boolean variables.

3.5.5 Structural Hashing

In order to reduce the number of timed Boolean variables, thistechnique tries to find all possible reuses of the timed Booleanvariable from the circuit network structure. The simplest reuse isshown in Figure 6.6, where we can reuse for X and replace anyoccurrence of X by

When each multi-input gate is represented by, or decomposedinto a cube, the localized normal form for gate function represen-tation is established. A hash table can be used to store the outputvariables with the sorted input list of each gate as a hashing key.The reuse of the circuit in Figure 6.7 can be found by the first reuse

and then This technique can reduce the number ofvariables and clauses dramatically, and even reduce the redundantvariables at different time points.

To test our approach, we used the ISCAS85 benchmark circuitset and made some simple assumptions that would emulate accuratelayout information.

In actual practice, due to the locality of the layout (i.e. electricalpruning) for each victim net, there are typically only a few aggres-sors that can cause significant noise. For testing our approach, weemulate this effect by selecting four random aggressor nets and one

4. Experimental Results


3.5.6 Coarse Quantum Time

One way to reduce the variables at the different time points is toassume a very coarse quantum time. Many timed Boolean variablesat different time points can be thus collapsed into one. However,this technique leads to a more conservative noise bound.

3.5.7 Boolean Constraint Relaxation

For large circuits, the CNF clauses might be too numerous to solveor satisfy. To relax the functional constraints, it can be just re-stricted to the relevant sum of product terms, in which we do notattempt to satisfy all of the characteristic functions. The idea isto select a depth of gates to build the characteristic functions, andassume the inputs of the boundary gates without the functionalcorrelation.


victim net. These results are shown in Table 6.1. It might be usefulto refer back to Section 3.5 to understand the approaches associatedwith the columns. The first column gives the circuit name from theISCAS benchmark. The simple worst column is the sum of themaximum crosstalk noise from each aggressor. The zero-delaymodel column and the static noise analysis column are describedin Section 3.3 and 3.4, respectively. The fixed delay column is the2-vector approach described in Section 3.5.

Because we do not have real layout information, we use someelectrical parameters, such as based on a sampleof 0.5um 5V static CMOS process, and use Eq. 1.2 to calculatethe maximum the maximum voltage difference shown on thevictim net. Arbitrarily, the same electrical parameters are used foreach circuit. We assume a condition similar to Fig. 1.8, in whichthe four aggressor nets possibly make a transition from high to low,and the victim net keeps static high. The numbers shown in Table.6.1 are the maximum voltage difference on the victim net due tothe coupling effect.

For the minimum voltage to be regarded as logic high, it shouldbe within 70% of VDD – that is, should be less than 1.5Volts in our test case. Therefore, the comparison of the maximumnoise bound shows that for C499, C1908 and C2670 circuits, thestatic noise analysis makes an over-pessimistic prediction, whilethe fixed delay model does not. The zero-delay model cannot takeinto account the effect of glitches, and as a result, it under-predictsthe maximum noise bound of C1908 and C2670. For most of thecases, the zero-delay model cannot predict tighter maximum noisebound than the static noise analysis, The simple worst case givesnothing informative and is included only as a reference. C6288could not be completed within a reasonable time.


5. Future WorkOur approach aims to find two vectors that maximize the noise

under assumptions that are as accurate as possible while being con-servative. One way to improve the conservatism of our approachis to consider the effect of cross-coupling on delay degradation,and therefore on timing. It is possible to model the rise waveformon the victim net and compute the maximum delay degradationusing Eq. 1.2. However, as more accurate RC-interconnect modelis desired for deep submicron technology, the modeling approachsimilar to [YCGS97, SNEZ97b] should be taken into account.

One area for improvement in the accuracy of our approach isto consider combinational logic blocks in their sequential context.We consider combinational blocks in isolation and presume thatthe vector pair that we identify is always within the valid sequen-tial state-space of the circuit. In other words, we assume that thevector pair that we identify can be excited in the normal opera-tion of the circuit. This might not be true and thus we could overestimate the noise of the circuit if this is not so. Resolving thisissue is more computationally challenging, as it is equivalent tothe sequential testing problem, or alternatively, the sequential state


space reachability problem, which is currently unsolved for largecircuits.

One approach to improving both the accuracy and the conser-vatism of our method is to incorporate a timing model in whichbounded delay intervals, rather than fixed delay values, are used.This approach will be investigated, but currently it appears to makethe problem computationally intractable for reasonable sized cir-cuits.

As we were unable to complete our computation on C6288, thereis still room for improvement in improving the computational per-formance of our approach.

For critical path delay degradation, we should consider the extradelay due to the noise interference of the previous input stage. Itwill result in a fixed-point algorithm as described in Chapter 3 todetermine degraded delays on the gates of the critical path, and theobjective function should be modified to be the maximum of thecritical path delays, which should be computed dynamically.

Our approach is conservative in the sense that we assume signalcorrelation only within a combinational block, while signals areassumed uncorrelated across sequential gates. Correlation couldbe possible to cross the sequential gates by the BDD state traversalapproach with the timing information such as TBF[LB94]. How-ever, the complexity is even higher than that of the sequential testgeneration. It is not practical for realistic circuits.

6. Conservativism Consideration

To make the approaches in this chapter conservative in practice,the delay model needs to take every timing uncertainty into account.For example, a bounded delay model needs to be used. The timeslot approach described in Chapter 5 can be used to reduce thecomplexity, and it has a natural fit by using Boolean variables inthe formulation.


7. ConclusionsThe goal of this chapter is to develop an algorithm, software tool,and noise analysis flow that provides a reasonably accurate andconservative approach to the analysis of noise problems that couldcause voltage glitches that lead to erroneous switching of dynamiclogic or the malfunctioning of analog circuitry. With such a toolavailable, the time consuming manual work in analyzing potentiallynoisy signals could be avoided. To achieve improved accuracy ourapproach finds two vectors that maximize the noise, and we havepresented a general scheme for identifying the proper vector pair.

This chapter compares the results obtained by simpler methodsincluding the zero delay model in which functional informationis incorporated but timing information is neglected, and the staticnoise analysis approach in which temporal information is incorpo-rated but functional information is ignored. Our approach is shownto be strictly more accurate than either of these approaches, whilestill being computational feasible on industrially sized sub-circuits.

Chapter 7

CONCLUSIONS

We have studied various static noise analysis problems and tech-niques for DSM designs. The contribution of this work is summa-rized below:

In Chapter 2, we showed how to use the Miller factors to estimatethe extra delay induced by crosstalk effects. This approach usesa decoupled circuit to approximate a coupling circuit. The exper-imental results showed promising accuracy. A theoretical upperbound of 3X is also found for the opposite direction switching, anda lower bound of -1X for the same direction switching. The con-ventional 2X factor is shown by experiments not as a bound andcan be inaccurate for coupling delay calculation.

In Chapter 3, we developed the mathematical foundation to com-pute the switching windows. Many numerical properties were for-mulated and proved. We also studied the effect of using differ-ent underlying coupling models, and its associated computationcomplexity. This work can solve most of the problems regardingswitching window convergence.

In Chapter 4, we proposed some event-driven algorithms to speedup the switching window calculation and showed how to efficientlyalign aggressors to create the worst case delay. We also comparedthe performance of different scheduling approaches.


In Chapter 5, we further modified the idea of using a continuousswitching windows; instead, we proposed a discrete switching win-dow by using time slots. This improves the accuracy and reducesthe pessimism in noise analysis. Our experiments showed that up to90% of potential noise violations suggested by continuous switch-ing windows can be excluded by this approach. Moreover, the sizeof a time slot can be controlled to trade off accuracy for speed andcapacity, which makes this algorithm highly scalable.

In Chapter 6, we presented a functional noise analysis to showhow a vector pair can be found to exercise the maximum noise on agiven net. We used a SAT formulation to solve the false switchingproblem, and showed how temporal information should be includedto improve accuracy. A Boolean constrained optimization problemwas used to find the maximum noise. A similar approach can beused to find if the noise can be propagated to a latch.

The characteristics of DSM processes make crosstalk effects nolonger negligible. Due to the high complexity of DSM chips andthe high cost of DSM processes, the chip design requires an exten-sive analysis of possible factors that affect the chip’s performanceand functionality. The work presented here helps bring a practicalcrosstalk analysis methodology into the DSM design realm.

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