State of the Union Krste Asanovic

UC Berkeley, RISC-V Foundation, & SiFive Inc. krste@berkeley.edu

8th RISC-V Workshop

Barcelona Supercomputer Center, Barcelona, Spain May 8, 2018

What is RISC-V?

A high-quality, license-free, royalty-free RISC ISA specification originally from UC Berkeley

Standard maintained by non-profit RISC-V Foundation Suitable for all types of computing system,

microcontrollers to supercomputers Numerous proprietary and open-source cores Experiencing rapid uptake in industry and academia Supported by growing shared software ecosystem A work in progress…

What’s Different about RISC-V? Simple

- Far smaller than other commercial ISAs

Clean-slate design - Clear separation between user and privileged ISA - Avoids µarchitecture or technology-dependent features

A modular ISA designed for extensibility/specialization - Small standard base ISA, with multiple standard extensions - Sparse and variable-length instruction encoding for vast opcode space

Stable - Base and standard extensions are frozen - Additions via optional extensions, not new versions

Community designed - Developed with leading industry/academic experts and software developers

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RISC-V Timeline

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RISC-V ISA project begins

1st Rocket tapeout, EOS14, 45nm

User ISA v2.0 IMAFD

Hot Chips 2014

First Linux Port 1

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RISC-V Foundation Incorporated

Privileged Arch, v1.10

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User ISA v1.0, Raven-1 tapeout (28nm), RVC MS thesis

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Modest RISC-V Project Goal

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Become the industry-standard ISA for all computing devices

So, how’s it going?

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Looking great, but still a lot of work left to do

RISC-V Standardization and Compliance

RISC-V’s value is providing a common free and open ISA standard to connect hardware and software

Common Questions: How do standards and customization coexist? How to prevent fragmentation? What is a RISC-V-compliant processor anyway?

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RISC-V Design versus Standards

Original Berkeley work built a coherent design for a family of ISAs, frozen in IMAFDQC 2.0 specs

- Not perfect, but apparently good enough

Foundation has had to pick some subset of design to ratify as official ISA standards, i.e. select actual instructions required for a given certification

- Also, fix holes and ambiguities, e.g., memory model, NaN representation, NaN boxing

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RISC-V Encoding Terminology

Standard: defined by the Foundation Reserved: Foundation might eventually use this space for future standard extensions Custom: Space for implementer-specific extensions, never claimed by Foundation

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RISC-V Custom Extension Example

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Base RV32I

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Standard RV32IMAFD Software

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RISC-V Custom Extension Example 2

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Base RV32I

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Standard RV32IMA Software

Custom SW Libraries

Non-Conforming Extension

The RISC-V Big Tent Philosophy Enable all types of RISC-V implementation

- 32-bit microcontrollers with 1KiB SRAM - 64-bit Unix servers with virtualization - 128-bit 100,000-core supercomputers with PiBs DRAM - Fully open platforms, only open-source software - Fully locked-down platforms, completely trusted - Platforms with pay-as-you-go hardware and software - Platforms with extensive non-conforming extensions - QEMU RISC-V containers running on x86 servers

Minimize wasted work through maximum reuse - Factor out platform-level requirements from reusable ISA and SW

modules

Use standard platform profiles to reduce ecosystem effort - Platform profiles tightly constrain choices among all options 12

RISC-V ISA compliance A system is minimally RISC-V-ISA-compliant if it runs claimed

RISC-V unprivileged code correctly - E.g., gcc-compiled RV32IMAC functions will work correctly

Pragmatically, platform must be able to execute memory images containing user RISC-V instructions in some environment and return test results somehow

- Platform is responsible for loading, initializing, running test, stopping test, extracting signature

One set of Foundation unprivileged ISA compliance tests should be able to run on any platform

- Challenge in handling tiny platforms, e.g., 1KiB SRAM

Foundation privileged ISA compliance tests similar 13

RISC-V Platform Compliance

A platform specification provides tight constraints on system configuration and options to support a software ecosystem

- Provides interface between platform hardware and platform software, including privileged level(s)

Unprivileged ISA choices constrained by need to reuse compiler/library work

Privileged architecture might vary widely across platforms - Differences in timers, counters, memory maps, interrupt schemes,

security, virtual memory, hypervisor… - But try to minimize unnecessary duplication

Platform compliance test provided by relevant ecosystem - E.g. Server platform compliance, ZephyrOS platform compliance

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In RISC-V land, software is king

If you build it, they might not come - No point adding instructions if no software wants to use it - Don’t repeat mistakes of proprietary ISAs

ISA extensions need compiler/linker/library support ISA proposals should be sensible to implement

- i.e., doesn’t make everything else worse in a pipeline

Platform standards must have software ecosystem

Standards take time to co-develop, evaluate, iterate No point in rushing just to have a frozen bad standard

- But do have to freeze sometime, otherwise worthless

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Open-Source Hardware

RISC-V a key component of nascent open-source hardware community

Some lessons from Free/Open-Source Software community apply, but many things are different

RISC-V is breaking new ground: very large investments in hardware artifacts that cannot be changed once manufactured, threat of patent lawsuits, …

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2017 was start of RISC-V Legacy

Fixed holes in user ISA, no changes now in IMAFDQC Froze priv-1.10, updates must be backwards-compatible Memory models RVWMO/TSO completed, in ratification Linux ABI frozen Debug spec completed, in ratification

All new standards work has to build on these decisions

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2018 Standards Initiatives Prepare base for ratification, in progress Formal spec, in progress Hypervisor, spec done, implementation needed Vector spec, close, implementation/compiler needed Crypto, in progress J (dynamic translation) extension, in progress P (small packed SIMD) in progress Security task group, in progress Fast interrupts, started Trace, started

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2018 RISC-V Embedded Platform

Task groups to improve embedded platforms Faster, nested, preemptive interrupts P packed SIMD extension

Possible initiatives: New ABI for embedded (e.g., long double=64b) Build on RV32E for smaller contexts Compiler/library work for improved code compression

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Expanding Foundation

RISC-V uptake continues to explode far faster than we ever imagined

Board discussing how to grow Foundation capabilities to support more initiatives

Informa engaged to manage conferences/workshops Improved media channel on website Major annual RISC-V summit in Silicon Valley Several different regional RISC-V workshops/year

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RISC-V and Security

Security is one of biggest challenges in contemporary computer architecture, so which to trust? Simple free ISA with open implementations and

publicly scrutinized security systems Baroque proprietary ISAs with complex unauditable

implementations of NDA-only security systems RISC-V already the center of security architecture research, but Foundation wants to accelerate innovation and deployment of secure RISC-V systems

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New RISC-V Security Standing Committee

Chair: Helena Handschuh, Rambus Vice-Chair: Joe Kiniry, Galois Research

Develop consensus around best security practices Develop and publish RISC-V security roadmap Propose security task groups (Marketing or Technical) Liaise with internal RISC-V committees and external security orgs Create repository on new attack trends, threats and countermeasures Identify top 10 open challenges in security Recruit security talent to the RISC-V ecosystem Promote RISC-V to security community

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Debian Port Progress

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RISC-V in Education

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RISC-V spreading quickly throughout curricula of top schools

Books available now!

¡La versión en Español ya está disponible!

Traductores Alí Lemus, Director de Laboratorio Turing

Eduardo Corpeño, Director del Área de Electrónica

Esta traducción es el resultado de la colaboración entre David Patterson, Andrew Waterman, UC Berkeley, SiFive y Universidad Galileo, en Guatemala.

Correctores Rodrigo Baessa. Decano, Facultad de C.C. Julio Fajardo. Candidato PhD, Lab. Turing Víctor Ferman. Candidato PhD, Lab. Turing

Descarga

Gratis:

http://riscvbook.com/espanol

Descarga Gratis:

http://riscvbook.com/espanol

Dave Patterson, John Hennessy 2017 Turing Award

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“For pioneering a systematic, quantitative approach to the

design and evaluation of computer architectures with

enduring impact on the microprocessor industry.”

RISC-V Adoption

No longer if, but where and when Likely mainframe (360), PC (x86), and smartphone

(ARM) markets will stay with incumbents for forseeable future

Everything else is open to RISC-V

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