start group tutorial [2]

http://www.bized.co.uk

Copyright 2006 – Biz/ed

Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud

Version 02 – October 2011

Start Group tutorial [2]



-Using Xilinx IP Cores

-ISIM Simulator

-Language Templates

B Outline

2



Using Xilinx IP Cores



tutorial

Why IP cores

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An IP (intellectual property) core is a block of logic or data that is used in FPGAs or ASIC

for a product.

Features

1-Repeated use of previously designed components.

2-Portable that is able to easily be inserted into any design methodology.



First Step Generating IP Core

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tutorial



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tutorial



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tutorial

In the IP selection window, find the IP to

customize.



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tutorial

For information about the customization

options, click the Data Sheet button in the

core customization GUI. The data sheet that

appears explains all of the options.



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Now, we generated an IP core and this core is on this

project, before generating this code you must read the

data sheet to deal with its GUI, know the timing diagram

and pins I/O interface of this core.

tutorial



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tutorial

Data Sheet



Second Step Using IP Core

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tutorial



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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity add is

port (

in1 : IN std_logic_VECTOR(14 downto 0);

in2 : IN std_logic_VECTOR(14 downto 0);

clk : IN std_logic;

enable : IN std_logic;

result : OUT std_logic_VECTOR(15 downto 0));

end entity;

architecture Behavioral of add is

component adder_core

port (

a: IN std_logic_VECTOR(14 downto 0);

b: IN std_logic_VECTOR(14 downto 0);

clk: IN std_logic;

ce: IN std_logic;

s: OUT std_logic_VECTOR(15 downto 0));

end component;

Now, we will make a project that adds two

numbers using this IP core.

VHDL code

tutorial



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Begin

your_instance_name : adder_core

port map (

a => in1,

b => in2,

clk => clk,

ce => enable,

s => result);

end Behavioral;

tutorial



Third Step Simulating IP Core

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tutorial

Click the device icon ..in Design Utilities click

on compile HDL Simulation libraries.

For simulation on Modelsim you should

generate some libraries for the ip core.



[ISIM] ISE Simulator



ISIM Simulator

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tutorial



ISIM Simulator

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tutorial



ISIM Simulator

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tutorial



ISIM Simulator

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tutorial



ISIM Simulator

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tutorial



Download ISIM tutorial from Xilinx

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug682.pdf

tutorial

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Language Templates



Language Templates

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tutorial

The ISE Language Templates provide predefined pieces of code and code syntax for

use in your source files.

These templates enable easy insertion of pre-built text structures into your VHDL file.

Select Edit > Language Templates, or click the Language Templates toolbar button

shown .



Language Templates

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tutorial

Click the plus (+) icon to expand the folders until you find the

template you want to use.

Select the template to display it in the right pane.

Insert the code in your source file.



Language Templates

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tutorial

you can create your own custom templates

as follows.

1-Select the User Templates folder.

2-Right Click : New Folder

Type a name for your folder.

3-Right Click : New Template.

Type a name for your template.



Language Templates

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tutorial

4-Add your code to the right pane of the

Language Templates window.

5-Right Click on the template name : Save

Template.

6-Note To remove a template, select the

template, and click the Delete toolbar

button .



See You Next Session

tutorial

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