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TRANSCRIPT
A 5GHz, 1mW CMOSVoltage–Controlled Differential
Injection–Locked Frequency Divider
Hamid R. Rategh, Hirad Samavati, Thomas H. Lee
Center for Integrated SystemsStanford University
OUTLINE
� motivation
� injection–locked frequency dividers (ILFDs)
– mathematical model
– circuit implementation
– design issues
� optimal inductor design
� measurement results
� summary
� conclusion
MOTIVATION
� wireless systems:
– are narrowband
– require frequency synthesizers
– require low power operation
� PLL–based frequency synthesizer require frequency dividers
� conventional dividers:
– wideband
– power hungry
VCO
M
PFD
Loop Filter
Channel Selection
foutf =M.frefref
IDEA
� design a low–power and narrowband frequency divider
use resonators to trade off bandwidth for power
INJECTION–LOCKED OSCILLATORS
� by impressing an oscillator with an external (incident) signal,frequency locking can be achieved
– first-harmonic injection locked oscillators (fi = fo)
– subharmonic injection locked oscillators (fi =
1Nfo)
– superharmonic injection locked oscillators (fi = N � fo)injection–locked frequency dividers (ILFDs)
ILFD MODEL
f(x) VoVi Η(ω)u(t)e(t)
vo(t) = Vocos(!ot)
vi(t) = Vicos(!it+ �)
u(t) = f [e(t)] = f [vo(t) + vi(t)]
H(!) =
H0
1 + j2Q!�!r
!r
� oscillation condition should be satisfied in the presence of theincident signal.
SIMPLIFIED PICTURE
f(e) = e2
iω iω2
iωi2
ωi2
ω
i2
ωi Η(ω)e uω
2,
,
3@
e = cos(!it) + cos(!i
2t)
u = [cos(!it) + cos(!i
2t)]2
u = 1 +1
2cos(2!it) +1
2cos(!it) + cos(3!i
2t) + cos(!i
2t)
SPECIAL CASE (DIVIDE–BY–TWO)
f(e) = a0 + a1e+ a2e2 + a3e3
� phase condition:
j�!
!rj < jH0a2Vi
2Q
j ;
H0Q
=LQ!r
Q
= L!r
� gain condition:
H0(a1 +3
2a3V2
i + a2Vicos(�)) < 1
VOLTAGE–CONTROLLED DIFFERENTIAL ILFD
R
VC
i
i
Vout
Vc
M1M2
M3 R1
Ibias
Vdd
- - ++
� 0.24�m CMOS
� Vdd=1.5V
� Ibias=300�A
� fo=2.25GHz
� fi=4.5GHz
VARACTOR
-n -n +n+n
G
N-well
Sub
S/D
VFB VGS
G
S/D
+
-
C
� accumulation mode MOS capacitor
– large quality factor (> 60 @ 2.5GHz)
– flat–band voltage � zero volt
INDUCTOR DESIGN
� maximum locking range ) maximize L
� minimum power consumption ) maximize LQ
INDUCTOR DESIGN
Cox Cox
Csi
RsLs
Cs
Rsi Csi Rsi
Sub
w
s
OD
� design parameters:
– w: metal width
– s: metal spacing
– OD: outer dimension
– n: number of turns
INDUCTOR DESIGN
� in planar spiral inductors maximizing L does not maximize LQ
+
maximize L for a given LQ
MEASUREMENT (FREE–RUNNING OSCILLATION)
1 1.5 2 2.52180
2200
2220
2240
2260
2280
2300
2320
Control Voltage (V)
Out
put f
requ
ency
(M
Hz)
� 0.24�m CMOS
� Vdd=2.0V
� Ibias=600�A
� �f=110MHz
� �ffo
=5%
� �Vc=1.5V
MEASUREMENTS (FREQUENCY RANGE)
3800 4000 4200 4400 4600 4800 5000
0.3
0.4
0.5
0.6
0.7
0.8
Incident frequency (MHz)
Inci
dent
am
plitu
de (
V)
Vc=0.0VVc=2.0V
� 0.24�m CMOS
� Vdd=1.5V
� Ibias=300�A
TRACKING ILFD
12
Vc
VVi o
VCDILFDVCO
� locking range extension
Rategh et al., symposium on VLSI circuits, June 1999, session12.1
MEASUREMENTS (LOCKING RANGE)
0.3 0.4 0.5 0.6 0.7 0.8200
300
400
500
600
700
800
900
1000
1100
1200
Incident amplitude (V)
Inpu
t ref
erre
d lo
ckin
g ra
nge
(MH
z)
Vc=0.0VVc=1.5VVc=2.0V� 0.24�m CMOS
� Vdd=1.5V
� fo=2.2GHz
� fi=4.4GHz
� �f=900MHz
� 20% @ 0.5V
MEASUREMENTS (POWER CONSUMPTION)
0.3 0.4 0.5 0.6 0.7 0.8
0.7
0.8
0.9
1
1.1
1.2
1.3
Incident amplitude (V)
Pow
er (
mW
)
� 0.24�m CMOS
� Vdd=1.5V
� fo=2.2GHz
� fi=4.4GHz
� P=1.0mW @ 0.5V
PHASE NOISE MEASUREMENT TEST SETUP
HP8563E50
On chip
ViVCDILFD
50
50
Vdd
Ext. Amp.
MEASUREMENTS (PHASE NOISE)
101
102
103
−130
−120
−110
−100
−90
−80
−70
Offset frequency (kHz)
Pha
se n
oise
(dB
c/H
z)
HP83732B Free running Middle freqeuncyEdge frequency
� 0.24�m CMOS
� Vdd=1.5V
� fo=2.2GHz
� fi=4.4GHz
CHIP MICROGRAPH
� 0.24�m CMOS
� area=0:186mm2
(345�m� 540�m)
SUMMARY
maximum frequency of operation 5GHz
output frequency tuning 110MHz � 5%
input–referred locking range 450MHz � 10% @ 0.7mW
900MHz � 20% @ 1.0mW
technology 0.24�m CMOS
die area 0.186mm2
flip–flop–based divider
0.24�m CMOS (simulation) 7mW @ 5GHz
0.1�m CMOS 2.6mW @ 5GHz(Razavi et al., JSSC Vol. 30, No.2, pp 101–109, Feb. 1995)
CONCLUSION
� injection–locked frequency dividers can be designed with:
– very large locking range
– very low power consumption
� spiral inductor design can be optimized to increase the ILFDlocking range
� varactors can be used to extend the ILFD locking range(tracking ILFD)
� voltage–controlled ILFDs are suitable for low–power andhigh–frequency wireless systems
ACKNOWLEDGMENTS
M. Hershenson
S. Mohan
T. Soorapanth
National Semiconductor
Stanford Graduate Fellowship program