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Development of A DERIVATIVE STANDARD CELL LIBRARY BNM_LVT_45NM FOR CMOS GPDK045 LIBRARY- AJAY.GAgendaINTRODUCTIONPROBLEM DEFINITION & JUSTIFICATIONDELIVERABLESBNM_LVT_45NM LIBRARYDESIGN FLOWDESIGN GUIDELINESBNM_LVT_45NM DESIGN DESIGN CHARACTERIZATIONRESULTS AND DISCUSSIONSCHEMATIC VIEW LAYOUT VIEWABSTRACT VIEWCHARACTERIZATION DATALEF DEF

CONCLUSIONFUTURE SCOPEPAPER PUBLICATIONSREFERENCES

Introduction Standard cell based design is the most practiced approach to implement an ICThis design flow requires a set of logic cells whose characteristic behavior is well knownSuch a set of logic cells is collectively called as a Standard Cell Library.Constituents of CMOS Standard Cell Library

Introduction contd.The components of a standard cell library areLogical cellsBuffer CellsSpecial Cells

Academic Cell librariesS.I No.,Library nameUniversity / OrganisationTechnology1VTVTVirginia tech250nm & 180nm2OSUOklahoma state university250nm &180 nm3NCSUNorth Carolina State University250 nm4MSUMississippi State university180nm4gpdk045Cadence45nmDeliverables of BNM_LVT_45nmThe BNM_LVT_45nm library contains the following deliverables.lib (Liberty library file).LEF(Library exchange format).spi (Spice netlist)Schematic representationLayout ViewAbstract viewAv_extracted viewComponents of BNM_LVT_45nm libraryCell Name No., of InputsDrive strengthINVERTER 11X,2X,4X,16X,32XBUFFER11X,2X,4X,16X,32XAND2,3,41X,2X,4XOR 2,3,41X,2X,4XNAND2,3,41X,2X,4XNOR2,3,41X,2X,4XAOI(21),(22),(211),(221),(222)1X,2X,4XOAI(21),(22),(211),(221),(222)1X,2X,4XXOR21X,2XFULL ADDER3MUX2X1,4X11X,2XDFLIPFLOP 1X,2XCLK GATE1XCLK BUFFER1XFILLER CELLS BNM_LVT_45NM library designStandard Cell Library Development- General FlowExtractionLayout Abstract(LEF/DEF)Pre Layout Simulation

Post Layout SimulationStandard Cell Library7/10/2011 AJAY G 1BG10LVS01 BNMIT9Library VerificationCharacterizationSchematic EntryEDA ToolsEDA Tool NameTool functionalityCadence Virtuoso Schematic Editor XLSchematic EntryCadence Virtuoso Analog Design EnvironmentSimulation Environment setupCadence Spectre SimulatorSpice Simulations /Functional VerificationCadence Virtuoso Layout XLLayout EntryCadence Assura DRC, LVS /Cadence Physical VerificationDesign Rule Check and Layout vs. Schematic verificationCadence QRCParasitic ExtractionCadence Hierarchy EditorBack annotationCadence Abstract GeneratorAbstract View generationCadence LEF/DEFLEF and DEF view generationCadence Encounter Library CharacterizerCharacterization of Cells Design GuidelinesStandard Cell design template -IntroductionCell height 3.36m15 routing tracks7/10/2011 AJAY G 1BG10LVS01 BNMIT12

Pitch

Routing Grid7/10/2011 AJAY G 1BG10LVS01 BNMIT14 Horizontal

Vertical

Routing Grid Definition -Tracks7/10/2011 AJAY G 1BG10LVS01 BNMIT15 Horizontal

15 Routing TracksStandard Cell Template

Standard cell heightCell OriginVdd RailVss RailPMOS REGIONNMOS REGION Pin placement

DesignDesign - Schematic EntryInput file formatspice model files (.scs, .spi, .sp )Output file format Spice netlist (.scs, .spi, .sp )Tool Cadence Virtuoso Schematic editor

Design Circuit SimulationToolSpectre Simulator in Cadence Virtuoso ADE

Design- LayoutInput file format Spice netlist (.scs, .spi, .sp )Output file formatIntermediate layout data base in .oa (Open Access)ToolCadence Virtuoso Layout editor

Design - Parasitic ExtractionInput file formatIntermediate layout data base in .oa (Open Access)Output file formatCircuit Spice netlist (.scs, .spi, .sp )ToolCadence QRC extraction tool

Design- Post Layout Simulation

Physical Simulation

Design- AbstractionAbstract View GenerationCadence Abstract generator

Pin InformationDesign- AbstractionLEF file generationThe LEF file for all cells is generated using the Cadence Virtuoso Toolset.The LEF contains information about the physical characteristics of the cellsDesign Library Characterization .Lib generationCharacterization of the BNM_LVT_45nm library cells is carried out using Cadence Encounter Library CharacterizerThe Cadence Encounter Library Characterizer requires the extracted spice netlists of BNM_LVT_45nm Cells.The cells are characterized for different Process, voltage and temperature conditions through spice simulations.The characterization data is presented in a Liberty file format (.Lib)Design-Characterization environment

Design - ELC Setup for CharacterizationThe ELC tool must be configured as per the requirements of the characterization processThe elccfg file is used to configure ELC.It contains information about model files, spice subcircuit definitions, process for which the cells must be characterized etc.Design - CharacterizationELC setup fileThe ELC tool requires a setup file which contains information about different process, voltage and temperature conditions to be considered for simulation.Design Characterization -Process conditionsParametersProcess CornersMinTypicalMAXVdd0.9 V1 V1.1 VAmbient Temperature0C25C 40CRESULTS & DISCUSSIONSDifferent views of a cell in BNM_LVT_45nm librarySchematicLayoutAbstractSpice netlistExtracted viewLEF fileLiberty library fileDEF file

LEF- Library exchange formatMACRO NOR2_X1 CLASS BLOCK ; ORIGIN 0 0 ; FOREIGN NOR2_X1 0 0 ; SIZE 1.275 BY 3.36 ; SYMMETRY X Y R90 ; PIN y DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 1.025 1.02 1.16 1.08 ; END END y PIN B DIRECTION INPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 0.995 2.075 1.195 2.165 ; END END B

PIN A DIRECTION INPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 0.1 0.935 0.3 1.195 ; END END A PIN gnd! DIRECTION INOUT ; USE GROUND ; PORT LAYER Metal1 ; RECT 0.62 -0.06 0.68 0.025 ; END END gnd! PIN vdd! DIRECTION INOUT ; USE POWER ; PORT LAYER Metal1 ; RECT 0.18 3.3 0.24 3.42 ; END END vdd! OBS 7/10/2011 AJAY G 1BG10LVS01 BNMIT32LAYER Metal1 ; RECT 0 0 1.275 3.36 ; LAYER Metal2 ; RECT 0 0 1.275 3.36 ; LAYER Metal3 ; RECT 0 0 1.275 3.36 ; LAYER Metal4 ; RECT 0 0 1.275 3.36 ; LAYER Metal5 ; RECT 0 0 1.275 3.36 ; LAYER Metal6 ; RECT 0 0 1.275 3.36 ; LAYER Metal7 ; RECT 0 0 1.275 3.36 ; LAYER Metal8 ; RECT 0 0 1.275 3.36 ; LAYER Metal9 ; RECT 0 0 1.275 3.36 ; LAYER Metal10 ; RECT 0 0 1.275 3.36 ; LAYER Metal11 ; RECT 0 0 1.275 3.36 ; ENDEND NOR2_X1

DEF- Design Exchange formatVERSION 5.6 ;DIVIDERCHAR "/" ;BUSBITCHARS "[]" ;DESIGN AND2_X1 ;UNITS DISTANCE MICRONS 2000 ;COMPONENTS 11 ;- I__0 pmos1v_lvt_45 + PLACED ( 1370 3200 ) FN ;- I__1 nmos1v_lvt_46 + PLACED ( 1250 1080 ) FN ;- I__2 pmos1v_lvt_43 + PLACED ( 2550 2840 ) N ;- I__3 nmos1v_lvt_47 + PLACED ( 810 1080 ) FN ;- I__4 nmos1v_lvt_48 + PLACED ( 2250 670 ) N ;- I__5 pmos1v_lvt_49 + PLACED ( 770 3200 ) N ;- I__6 M1_PO_3 + PLACED ( 290 2220 ) N ;- I__7 M1_PO_3 + PLACED ( 1610 2650 ) N ;- I__8 M1_PO_3 + PLACED ( 2310 2080 ) N ;- I__9 M1_NWELL_1 + PLACED ( 180 3230 ) N ;- I__10 M1_PSUB_8 + PLACED ( 760 30 ) N ;END COMPONENTSEND DESIGN

.LIB- Liberty library formatLiberty file for AOI211_X1Cell Data SheetAOI211_X1:Features:Strength1XCell Area4.7376m2FunctionY=!(((C1 & C2) | B) | A)TypeCombinationalInputA ,B ,C1,C2OutputYPower SupplyVdd -1V, Gnd -0VCell Data Sheet Contd.AOI211_X1

Propagation delay[ns]Input Transition[ns]0.02311.2Load Capacitance[fF]0.82189.750.82189.75A to YFall0.0243280.5859330.2062511.14821Rise0.0553381.870690.251122.2676B to YFall0.0227130.5565890.1671281.11221Rise0.0517871.867260.2584172.33449C1 to YFall0.0280181.128920.1599011.62Rise0.0365321.974810.2132292.43432C2 to YFall0.0305191.131840.1659511.60209Rise0.0423191.99640.2491312.46087Cell Data Sheet Contd.Transition Delay of AOI211_X1

Output Transition[ns]Input Transition[ns]0.02311.2Load Capacitance[fF]0.82189.750.82189.75A to YFall0.0159020.8038320.1711140.846717Rise0.0379772.4380.1486592.43649B to YFall0.0137440.7646360.1706910.815712Rise0.0380342.437450.1750892.43724C1 to YFall0.0205961.516540.1810011.52304Rise0.0363562.622740.1917062.61927C2 to YFall0.0206711.529940.1627441.52109Rise0.0413682.643660.1918932.64294Cell Data Sheet Contd.CapacitancePower Capacitance[fF]A1.09103B1.15921C10.931196C20.11872Leakage Power[nW]0.251096Cell Data Sheet Contd.AOI211_X1Dynamic power consumptionDynamic Power Consumption[nW]Input Transition[ns]0.02311.2Load Capacitance[fF]0.82189.750.82189.75A to YFall0.0004710.0760250.001020.07593Rise0.0027070.0792610.0028810.079247B to YFall0.0002730.0762010.0008730.076116Rise0.0023960.0789590.0026830.078947C 1to YFall0.0001880.0766070.000410.07654Rise0.0018280.0784210.002422 0.078469C2 to YFall0.0001740.0766020.0002070.076601Rise0.0021790.0787360.0028510.078807Conclusion - HighlightsTarget Library - 45nm technology Standard cell height 3.36m (149)Derivative library to gpdk045It is a 15 track librarySupports core power supply 1VContains functional special cells filler cellsLiberty file format for all cells synthesis LEF, DEF available for all cellsCadence Design tools used for entire design flowLow Vt transistors are used for all cellsCells are operable upto 125 CelsiusOnly Metal1,Metal2 and poly are used for intra-cell routing

Future ScopeThe Standard cell library is technology dependent , hence as the technology shifts to newer sub nano geometry nodes, a new cell library must be developed.Optimized versions of BNM_LVT_45nm library can be developed focusing on either low power or high performance cells.It is also possible to scale down the library to sub-45nm technology.

PublicationsTitle of the PaperAccurate Power Measurement Methodology for VLSI Circuits Using CAD ToolsName of the conferenceInternational Conference on Devices ,Circuits and SystemsIEEE xplore paper IDINSPEC Accession no: 12692787ISBN no: 978-1-4577-1545-7VenueKarunya Univeristy, Coimbatore, IndiaReferencesDimitris Bekiaris, Antonis Papanikolaou, Giorgos Stamelos, Dimitrios Soudris, George Economakos and Kiamal Pekmestzi, A standard-cell library suite for deep-deep submicron CMOS technologies, 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE -2011 .Jianping Hu and Jun Wang Low Leakage Power Designs of Basic Standard Cells Using Gate-Length Biasing, IEEE 2011Gerson Scartezzini, Ricardo Reis, Power Consumption in Transistor Networks versus in Standard Cells, IEEE 2011.Jeannette Donan Djigbenou, Thien Van Nguyen, Cheng Wei Ren, and Dong Sam Ha, Development of TSMC 0.25m Standard Cell Library ,IEEE 2007

References- Contd.Development and Distribution of TSMC 0.25 m Standard CMOS Library Cells,Jeannette Donan Djigbenou and Dong Sam Ha,VTVT (Virginia Tech VLSI for Telecommunications) Lab,IEEE 2007Puneet Gupta, Andrew B. Kahng, Puneet Sharma, and Dennis Sylvester Gate-Length Biasing for Runtime-Leakage Control, IEEE 2006Nguyen Minh Duc and Takayasu Sakurai Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies,ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference, 2000Asral bin Bahari Jambek, Ahmad Raif bin Mohd Noor Begand Mohd Rais Ahmad Standard Cell Library Development, IEEE 1999J.L. Noullet, A. Ferreira-Noullet Do We Need So Many Cells For Digital ASIC Synthesis?, Institut National des Sciences Appliquees,Electron Technol (Warsaw). Vol. 32, No. 3, Pp. 272-276. 1999.

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