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STM icroelectr oni cs

AD C S 7645929A S T231 Core a nd Inst ruct ion S et Archit ect ure Ma nua l

ST200 VLIWSeries

ST231 Core andInstruction Set

Architecture Manual

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S T231 Core a nd Inst ruct ion S et Archit ect ure Ma nua l AD CS 7645929A

This publication contains proprietary information of STMicroelectronics,

and is not to be copied in whole or part.

Issued by the MCDT Documentation Group on behalf of STMicroelectronics

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility forthe consequences of use of such information nor for any infringement of patents or other rights of third parties which mayresult from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces

all information previously supplied. STMicroelectronics products are not authorized for use as critical components inlife support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners.

The ST231 core is based on technology jointly developed by Hewlett-Packard Laboratories and

STMicroelectronics.

Linuxis a registered trademark of Linus Torvalds

2000, 2001, 2002, 2003, 2004 STMicroelectronics. All Rights Reserved.

STMicroelectronics Group of Companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong

India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - SwitzerlandUnited Kingdom - U.S.A.

http://www.st.com
http://www.st.com/http://www.st.com/

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Contents

Preface xv

1 Introduction 1

1.1 VLI W over view 1

1.2 S T231 over view 2

1.3 S T231 ch a nges su mma r y 3

1.4 D ocumen t over view 4

2 Execution units 7

2.1 I nt eger un it s (I U ) 7

2.2 Mult iply unit s 7

2.3 L oa d /st or e u nit (L S U ) 8

2.3.1 Memory a ccess 8

2.3.2 Addressing m odes 8

2.3.3 Alignment 9

2.3.4 C ont rol regist ers 9

2.3.5 C ache purging 9

2.3.6 D ism issible loa d s 10

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2.4 B ra nch unit 10

2.4.1 I dle m ode m acr o 112.4.2 syncins ma cro 12

3 Architectural state 13

3.1 P r ogr a m cou nt er (P C ) 13

3.2 Regist er file 133.2.1 Link regist er 13

3.3 P r ogr a m st a t us w or d (P S W) 14

3.3.1 B it fields 14

3.3.2 U SE R_MOD E 15

3.3.3 P SW a ccess 15

3.4 B r a n ch r egis ter file 16

3.5 C on tr ol r egist er s 16

4 Execution pipeline and latencies 17

4.1 E xecu tion pipelin e 17

4.2 Oper a tion la t en cies 18

4.3 Int er locks 18

4.4 Addit ion a l n ot es 19

4.4.1 R es t rict ion s on lin k r eg is t er 19

5 Traps: exceptions and interrupts 21

5.1 Tr a p mecha n ism 21

5.2 E xcept ion h a nd lin g 22

5.3 S a ved execut ion st a t e 22

5.4 Int errupt s 24

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5.5 D ebug in ter ru pt h a nd lin g 24

5.6 Ex cept ion t y pes a n d pr ior it ies 24

5.6.1 I lleg a l in st r uct ion d efin it ion 26

5.7 S pecula t ive loa dconsiderations 27

5.7.1 Mis a lig ned im plem en t a t ion 27

6 Memory translation and protection 296.1 I nt roduct ion 29

6.2 Overview 29

6.3 TLB sizes 30

6.4 Addr ess spa ce 30

6.4.1 P h ysica l a ddresses 30

6.4.2 Vir t ua l a ddresses 30

6.4.3 Ca ches 30

6.5 C on tr ol r egist er s 34

6.5.1 P S W 34

6.5.2 TLB _I ND EX 346.5.3 TL B _E NTR Y0 35

6.5.4 TL B _E NTR Y1 38

6.5.5 TL B _E NTR Y2 38

6.5.6 TL B _E NTR Y3 39

6.5.7 TLB _RE P LACE 39

6.5.8 TL B _C ONTROL 41

6.5.9 TLB _AS ID 41

6.5.10 C oher en cy 41

6.5.11 TL B _E XC AU S E 42

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6.6 TL B d escr ipt ion 43

6.6.1 Reset 436.6.2 U TLB a rbit ra t ion 44

6.6.3 E xcept ions 44

6.6.4 I nst ruct ion a ccess es 44

6.6.5 D at a a ccesses 46

6.7 S pecu la t ive con t r ol unit (S C U) 47

6.7.1 S CU _B AS E x 48

6.7.2 S CU _LIMITx 48

6.7.3 U pda t es t o S CU r eg ist er s 48

7 Memory subsystem 49

7.1 Memor y subsyst em 50

7.2 I -s id e m em or y s ubs yst em 50

7.2.1 I nst ruct ion buffer 51

7.2.2 I nst ruct ion ca ch e 51

7.2.3 I -side bus er ror 53

7.3 D -s id e m em or y s ubs ys tem 537.3.1 Loa d st ore unit 53

7.3.2 D a t a ca ch e pa r tit ion in g 54

7.3.3 S pecula t ive loa d s 54

7.3.4 C a ch ed loa ds a n d st or es 55

7.3.5 U n ca ch ed loa d a n d st or es 55

7.3.6 P refet ching da t a 557.3.7 P urgin g da t a ca ches 56

7.3.8 D -s id e sy nch ron iza t ion 57

7.3.9 D -side bus er ror s 57

7.3.10 Oper a tion s 58

7.3.11 C a ch e policy 58

7.3.12 Wr it e bu ffer 63

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7.4 Core memory con t rol ler (CMC) 63

7.5 Addit ion a l n ot es 637.5.1 M em or y or der in g a n d s yn ch r on iz a t ion 63

7.5.2 Coh er en cy b et w een I -s id e an d D-s id e 64

7.5.3 Reset st a te 64

7.5.4 C a ch ed d a t a in u nca ch ed r eg ion 64

7.5.5 P r efet ch per for ma n ce 64

8 Streaming data interface (SDI) 67

8.1 Overview 67

8.2 F un ct ion a l d es cr ipt ion 68

8.2.1 D a ta w idt h 68

8.3 C om mun ica t ion ch a nn el 69

8.3.1 Timeout s 69

8.4 Regist ers 69

8.4.1 I npu t ch a nn el m em or y m a ppin g 69

8.4.2 Out pu t ch a nn el m em or y m a ppin g 71

8.4.3 P rot ect ion 71

8.5 Ex cept ion s, int er r upt s , r es et a n d r es t a r t 72

8.5.1 In t errupt s 72

8.5.2 S DI except ions 73

8.5.3 R est a r t (or s oft r es et ) 73

9 Control registers 77

9.1 Acces s oper a t ion s 77

9.2 E xcept ions 77

9.3 C on t rol r egis ter a d dr es ses 78

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9.4 Ma ch in e st a t e r egist er 83

9.5 Ver sion r egist er 84

10 Timers 85

10.1 Oper a t ion 85

10.1.1 TI ME D IVI D E 86

10.1.2 TIME COU NTi 8610.1.3 TI ME CONS Ti 86

10.1.4 TI ME C ON TR OL i 87

10.2 Timer in ter rupts 87

10.3 P r ogra m m in g t h e t im er 87

11 Peripheral addresses 89

11.1 Access to peripheral registers 89

11.2 P er iphera l addresses 90

11.2.1 In ter rupt con trol ler & t imer reg is ters 90

11.2.2 D S U r egist er s 92

11.2.3 D SU ROM 94

12 Interrupt controller 95

12.1 Arch itecture 95

12.2 Oper a t ion 96

12.2.1 Tes t r eg is t er 96

12.3 I n t er r upt r eg is t er s 96

12.3.1 In ter rupt pend ing regi ster (INTP ENDING ) 96

12.3.2 In ter rupt mask reg is ter (INTMASK) 97

12.3.3 In ter rupt ma sk se t and clear reg is ters (INTMASKSE T and

INTMASKCLR) 98

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12.3.4 Interrupt test register (INTTES T) 100

12.3.5 In ter rupt set a nd clear reg is ters (INTSET and INTCLR)

101

12.4 P r og ra m m in g 103

12.4.1 Ena b ling/disab ling inter rupts 103

12.4.2 Tes t r eg is t er 103

12.4.3 I n ter ru pt pr ior it y 103

13 Debugging support 105

13.1 Ov er view 105

13.2 C ore 106

13. 2.1 D eb ug in t er ru pt s 106

13.2.2 H ar d w a r e b reakpoin t suppor t 107

13.3 Debug suppor t un it 109

13.3.1 Ar ch it ect u re 109

13.3.2 S h a r ed r eg is t er b a nk 110

13.3.3 DS U con t r ol r eg is t er s 111

13.4 D ebu g R OM 113

13.4.1 Debu g i ni t ia l iz a t i on loop 113

13. 4.2 D efa u lt d eb ug h a n dler 113

13.5 Hos t debug inter face 117

13.5.1 Mes sa g e for ma t 117

13.5.2 O per a t ion 119

14 Performance monitoring 121

14.1 E ven ts 121

14.2 Access to regis ters 124

14.3 Control register (P M_CR) 124

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14.4 Event counters (P M_CNTi) 125

14.5 Clock counter (P M_P CLK ) 126

14.6 Recording even ts 126

15 Interfaces 127

15.1 M ode pin s 127

15.1.1 P e riph er a l a d dr es s 127

15.1.2 B oot a d dr es s 127

15.1.3 D ebug en a ble 127

15.1.4 P or t lis t 128

15.2 S yst em 128

15.2.1 P or t lis t 129

15.3 Interrupt control ler 129

15.3.1 P or t lis t 129

15.4 S D I I n t er fa ces 129

15.4.1 P or t lis t 131

15.5 STB us Master interface (type 3) 13215.5.1 P or t L ist 133

15.6 STB us Ta rget interfa ce (type 3) 133

15.6.1 P or t lis t 134

15.7 Debugging interface 134

15.7.1 P or t lis t 135

15.8 Secur ity inter face 135

15.8.1 P or t lis t 136

15.9 D F T a n d t est 136

15.9.1 P or t lis t 137

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16 Execution model 139

16.1 I n t roduct ion 139

16.2 B undle fetch, decode, a nd execute 140

16.3 Funct ion s 142

16.3.1 B u n dle d ecod e 142

16.3.2 Oper a t i on ex ecu t ion 142

16. 3.3 E x cept ion a l ca s es 143

17 Specification notation 145

17.1 Ov er view 145

17.2 Var iab les and types 146

17.2.1 I nt eger 146

17.2.2 B oolea n 147

17.2.3 B i t -field s 147

17.2.4 Ar ra ys 147

17.3 Expressions 148

17.3.1 I n t eger a r i t h met i c oper a t or s 148

17.3.2 I n t eger sh if t op er a t o rs 149

17.3.3 I n t eger b it w i se opera t o rs 150

17.3.4 Rela t i on a l oper a t or s 151

17.3.5 B oolea n oper a t or s 152

17.3.6 Single-va lue funct ions 152

17.4 S t a t em en ts 15417.4.1 U n d ef in ed b eh av ior 154

17.4.2 As sig nm en t 155

17.4.3 C on dit ion a l 156

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17.4.4 R epet it ion 157

17.4.5 E xcept ion s 157

17.4.6 P r ocedu res 158

17.5 Arch itectura l s t a te 158

17.6 Memory a nd control registers 159

17.6.1 S u ppor t f un ct i on s 159

17.6.2 M em or y m od el 161

17.6.3 Con t r ol r eg is t er m od el 167

17.6.4 C a ch e m odel 169

18 Instruction set 171

18.1 I n t roduct ion 171

18.2 B undle encoding 171

18.2.1 E x ten ded im med ia t e s 172

18.2.2 E n cod in g r es t r ict i on s 173

18.3 Opera t ion speci fica t ions 173

18.4 Example opera t ions 175

18.4.1 a d d I mm edia t e 175

18.5 Ma cr os 177

18.6 Oper a t ion s 178

A Instruction encoding 357

A.1 Reserved bit s 357

A.2 Fields 357

A.3 Forma t s 358

A.4 Opcodes 359

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B Glossary 365

Index 367

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Preface

This document is pa rt of the ST200 documenta tion suit e deta iled below. Comment s

on this or other ma nua ls in the ZZZ documenta tion suite should be ma de by

cont a cting your local S TMicroelectronics sa les office or dist ribut or.

ST200 document identification and controlEa ch book in th e ST200 document a tion suite car ries a un ique ADC S ident ifier of

the form:

ADCS nnnnnnnx

where nnnnnnnis t he document n umber, a nd xis th e revision.

Whenever ma king comment s on a n S T200 document , t he complete identificat ion

ADCS nnnnnnnxshould be quoted.

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ST200 documentation suite

The S T200 document a tion s uite comprises t he follow ing volumes:

ST230 Core and Instruction Set Architecture Manual (ADCS 7511658)

This ma nua l describes the a rchitectur e an d instr uction set of the S T231

implementation.

ST200 Micro Toolset User Manual (ADCS 7508723)

This ma nua l describes the softw a re provided a s par t of the ST200 tools. It supports

th e development of ST200 applica tions for embedded syst ems. Applica tions m a y be

developed in eith er a sta nd-a lone environment , or und er th e OS21 rea l-tim e

operat ing system.

This ma nua l also conta ins reference ma teria l relat ing to th e ST200 micro toolset.

ST200 Cross Development Manual (ADCS 7521642)

This ma nua l describes the cross development t ools a nd plat forms.

ST200 Runtime Architecture Manual (ADCS 7521848)

This m a nua l describes t he common softw a re convent ions for t he S T200 processor

runt ime a rchitecture.

OS21 for ST200 User Manual (ADCS 7410372)

This ma nua l describes th e use of OS21 on ST200 pla tforms. I t describes how

specific ST200 facilities a re exploited by th e OS21 AP I. I t a lso describes th e OS21

board s upport pa ckages for ST200 pla tforms.

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1IntroductionThe 32-bit ST231 is a mem ber of t he S T200 fa mily of cores.

This fa mily of embedded processors use a scala ble technology t ha t a l lows va ria tion

in instruction issue width, t he number a nd capa bili t ies of functional units a nd

register f iles, and t he instruction set.

The S T200 fa mily includes t he following feat ures:

para l lel execution uni ts , including mult iple in teger ALU s a nd mult ipl iers ,

a rch itectura l suppor t for da ta prefetch ,

pred ica t ed execut ion t h rough selectoperations,

eff icient bra nch a rchi tecture wi th mult iple condi t ion registers ,

encoding of immedia te opera nds up to 32 bits ,

suppor t for user/supervisormodes and m emory protect ion.

1.1 VLIW overview

VLIW (very long inst ruction w ord) processors use a techniqu e wh ere instr uction

level pa ra llelism is explicitly exposed t o the compiler w hich must schedule

opera t ions t o a ccount for the opera tion lat ency.

RIS C-like operat ions (sylla bles) a re gr ouped int o bundles (wide w ords). The

opera tions in a bu ndle ar e issued simulta neously. In t he ST200 fa mily opera tions

a lso complet e simulta neously. While the dela y betw een issue an d completion is the

sa me for a l l opera tions, some results a re a vaila ble for bypa ssing to subsequent

opera tions prior t o completion. This is d iscussed furt her in Chapter 4: Executi on

pipeli ne and lat encies on page 17.

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A ha rdw a re implementa tion of a VLIW is signif ica ntly simpler th a n a

corresponding mult iple issue superscaler C P U . This is due principally t o the

simplif icat ion of the opera tion grouping a nd scheduling ha rdw a re, a l l thiscomplexit y is moved to the inst ruction scheduling syst em (compiler an d a ssembler)

in the softwa re toolcha in.

1.2 ST231 overview

Figure 1: ST231 processor diagram

I-side

subsystem

memory

Debugsupport unit

Peripherals

61 interrupts Debuglink

InterruptcontrollerTimers

Trapcontroller

STBus

Writebuffer

Controlregisters

D-side

subsystemmemory

SDI ports

STBus

ST230 core

MulMul

IUIU IUIU

Instructionbuffer

Registerfile (64

8 read4write)

Loadstoreunit

(LSU)

registers

Branchregister

file

PC and

unitbranch

ICache

Prefetchcache

DCache

DTLBITLB

CMC

UTLB 4 x SDI

32-bit

64-bit

SCU

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ST231 changes summary 3PRELIMINARY DATA



1.3 ST231 changes summary

The follow ing is a brief description of th e cha nges from th e ST220 to t he S T231, a nd

a n indication of where in the document a more deta iled description of the feat ure

can be found.

A tr a nsla tion looka side buffer (TLB ) ha s been a dded t o provide full support for

memory tra nslat ion a nd protection (see Chapter 6: M emory translat ion and

pr otecti on on page 29).

Operat ion la tency int erlocks have been ad ded in order t o reduce th e number ofrequir ed nops, an d t herefore reduce code size (Secti on 4.3: I nt er locks on

page 18).

A num ber of ad ditiona l performa nce monitoring events ha ve been add ed (see

Secti on 14.1: Event s on page 121for deta ils):

A lower pow er idlemode has been a dded. This a llow t he core to be put int o a lowpow er mode until a n int errupt occurs (see Secti on 2.4.1: Idl e mode macr o on

page 11).

The sbrk a ndsyscall operat ion ha ve an a dditiona l f ield for softwa re f lags (seeSecti on 18.6: Oper ati ons on page 178).

The P SW is now read only, but i t can be cha nged a tomica lly using the new

pswsetand pswclrinst ructions (see Secti on 18.6: Oper ati ons on page 178).

The syncinsma cro ha s been cha nged (see Secti on 2.4.2: syncin s macro onpage 12). This ma cro ca n n ow only be executed in supervisormode.

The instr uction ca che can be flushed by pag e using the new prginspginst ruction (see Secti on 18.6: Oper ati ons on page 178).

The beha vior of uncached a ccesses ha s been cha nged t o ensur e they flush t he

da ta cache (see Secti on 7.5.4: Cached dat a i n un cached r egion on page 64).

All control regist ers a re now only a ccessible in supervisor mode (see Secti on 9.1:

Access oper at i ons on page 77).

The timer regist ers a nd opera tion ha s been cha nged to help improve OS support

(see Chapter 10: Tim ers on page 85).

The non-ma ska ble bits in t he int errupt cont rol ha ve been rem oved (see

Chapter 12: I nterr upt contr ol l er on page 95).

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The DS U sta tus register (DS R1) ha s the a dditiona l endia n bit (see Table 49:

DSR1 bi t fi eld s on page 111).

The VER SI ON (see Table 26: VERSION bit f i eld s on page 84) a nd

DS U _VERSI ON (see Table 48: DSR0 bit field s on page 111) registers h a ve been

changed.

A num ber of new 32x32 multiply inst ructions, mul32, mul64h, mul64hu&mulfracha ve been a dded (see Chapter 18: Instruct ion set on page 171).

1.4 Document overviewThis ma nua l describes the a rchitectur e an d instr uction set of the S T231

implementa tion. This section gives an outline of th e follow ing document.

The processor is ma de up of a num ber of functiona l unit s described in Chapter 2:

Execut ion uni tsw hich opera te on da ta stored in the register f iles (Chapter 3:

Ar chit ectur al state). These functiona l unit s a re pipelined a nd s ubject t o explicit

observa ble la tencies (Chapter 4: Executi on pi peli ne and lat encies).

The ha ndling of exceptions a nd int errupts a re deta iled in Chapter 5: Traps:

excepti ons and in ter r upts.

The S T231 accesses memory t hrough th e memory subsy stem (Chapter 7: M emory

subsystem) w hich provides protection a nd a ddress tra nslat ion by mea ns of a

Tra nsla tion Looka side Buffer (Chapter 6: Memory tr anslat i on an d pr otect ion).

The S T231 ha s 4 S DI port s (Chapter 8: Str eami ng data i nterface (SDI )) wh ich allow

it t o communica te ra pidly w ith other devices a nd a void cache pollution w hen

processing large a mounts of data .

Cont rol of the devices is performed using t he memory ma pped cont rol registers

defined within the relevant cha pters. The a ddress of the cont rol registers a nd P SW

a re deta iled in Chapt er 9: Cont r ol r egister s.

The ST231 also provides a performa nce monitoring syst em to help with softw a reoptimisa tion an d debugging (Chapter 14: Per form ance monitori ng on page 121).

The following peripheral d evices a re a lso provided: tim ers (Chapter 10: Tim ers),

interrupt control (Chapter 12: I nterr upt contr ol l er) a nd debug support (Chapter 13:

Debugging support). The periphera l register a ddresses a re deta iled in Chapter 11:

Per i pheral add r esses.

The execution m odel is described in Chapter 16: Execut ion model. The execution of

bundles is described in Secti on 16.2: Bund l e fetch, decode, and execut e on page 140,

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Document overview 5



including the behavior of the machine when exceptions or interrupts are

encountered.

The interfa ces presented by th e core to the sys tem a re deta iled in Chapter 15:

I nt er faces on page 127.

Chapter 18: Instru ct i on setdescribes th e deta ils of each opera tion, including t he

sema nt ics. The inst ruction set includes deta ils of the inst ruction set encoding,

synt a x a nd sema nt ics. The encoding of bundles is defined in Secti on 18.2: Bu nd le

encodi ng on page 171.

The beha vior of opera tions is specified using t he nota tiona l lan gua ge defined inSecti on 17.1: Over view on page 145through Secti on 17.4: Statements on page 154.

The descriptions clea rly identify where a rchitectura l sta te is updat ed an d t he

lat ency of the operan ds.

A simple model of memory a nd control registers defined in Secti on 17.6.2: M emory

model on page 161an d Secti on 17.6.3: Contr ol r egister model on page 167is used

when specifying the loadan d storeoperations.

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6 Document overview



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2Executionunits

The functional core of ST231 comprises of a number of execution units working on

tw o register files. The execution units include 4 int eger units , 2 mult iply units, a

loa d store unit a nd a bra nch unit w hich a re a l l described in this chapter. The tw o

register f i les, the bra nch registers a nd t he general purpose registers a re described

in Chapter 3: Architectur al state on page 13.

2.1 Integer units (IU)

The ST231 has four identical int eger units. E a ch integer unit is ca pa ble of

executing one opera tion per cycle. The result s of the int eger units can be used a s

opera nds of t he next bundle. This is equiva lent t o a pipeline depth of one cycle.

Ea ch opera tion ca n t a ke up to three opera nds in t he form of tw o 32-bit va lues a nd a

single conditiona l bit. The IU th en executes th e appropriat e opera tion a nd produces

up to tw o results in t he form of a 32-bit va lue an d a 1-bit conditiona l va lue. The

integer operat ions supported a re deta iled in t he Chapter 18: Instruct ion set on

page 171.

2.2 Multiply unitsThe ST231 has t wo identica l multiply units. E a ch multiply unit is pipelined wit h a

depth of t hree cycles, executing a n operat ion every cycle.

Ea ch multiply units t a kes tw o 32-bit opera nds a nd produces a s ingle 32-bit result .

The mult iply opera tions support ed ar e deta iled in the Chapter 18: Instruct ion set on

page 171.

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8 Load/store unit (LSU)



2.3 Load/store unit (LSU)

The ST231 ha s a single loa d st ore unit . The loa d st ore unit is pipelined wit h a depth

of three cycles, execut ing a n opera tion every cycle.

The load st ore ca n t a ke up to th ree 32-bit operan ds a nd ma y produce a sing le 32-bit

result depending on the opera tion. The loa d store opera tions support ed ar e deta iled

in the Chapter 18: I nstruct ion set on page 171.

Memory a ccess protection a nd t ra nslat ion is implemented by the TLB , this is pa rt

of th e memory sub-syst em. The TLB a lso cont rols the cache beha vior of dat aaccesses, Chapter 6: M emory tr anslat i on and protect ion on page 29.

U ncached accesses or a ccesses w hich miss t he da ta cache ca use the loa d store unit

to st a ll the pipeline to ensure correct operat ion.

2.3.1 Memory access

The ST231 addresses the external memory system via a single address space.P eriphera l devices a nd contr ol registers a re a lso ma pped into th e a ddress space.

All ca chea ble memory tr a nsa ctions a re made via t he dat a ca che. The dat a cache

then decides i f i t needs to go to externa l memory to sa tisfy t he request.

Note: Cacheable memory tr ansact ions that m iss are wr i t ten t o the wri te buf fer n otth e

da ta cache.

U nca ched accesses a re performed directly on t he memory syst em (refer to

Chapter 7: Secti on 7.3.5: Un cached l oad an d stor es on page 55).

2.3.2 Addressing modes

The ST231 supports one addressing mode th e effective addr ess is an immedia te

(const a nt ) plus a r egister.

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Load/store unit (LSU) 9



2.3.3 Alignment

1 All loadand storeinstructions work on da ta stored on the na tura l al ignment ofthe da ta type; tha t is, words on w ord bounda ries, ha lf-word on half word

boundaries.

2 load an d storeoperat ions w ith misa ligned a ddresses raise a n exception whichmakes possible the implementation of misaligned loads by tra p handlers.

3 For a byt e or ha lf-word load, the da ta from memory is loaded into the lea stsignificant part of a register and is either sign-extended or zero extended

a ccording to the inst ruction definition.

4 For a byte or ha lf-w ord store, the da ta s tored f rom t he least s igni fica nt pa r t of aregister.

2.3.4 Control registers

The LSU ma ps a part of the addr ess spa ce tha t is devoted to contr ol registers (see

th e Contr ol Registers cha pter for deta ils). The LS U cont rol register block int ercepts

loads and stores to this a rea of memory so tha t i t can process the operat ion. Noa ccess to th e da ta cache is ma de for contr ol register opera tions. Tra nsa ctions a re

ma de across th e 32-bit cont rol register bus to th ose cont rol registers t ha t live

outside the LSU .

2.3.5 Cache purging

Ca che purging (flush a nd inva lidat e) opera tions a re provided on the S T231.

They a llow for purging l ines an d sets from the dat a cache, a nd inva lida ting t he

entire instruction cache.

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10 Branch unit



2.3.6 Dismissible loads

Dismissible loads a re used to support softw a re loa d speculat ion. This a l lows t hecompiler to schedule a load in a dvan ce of a condition tha t predica tes i ts use.

Dismissible loads a re required to return t he same va lue as a normal load if sucha n opera tion can be executed w ithout ca using a n exception. Otherw ise dismissible

loads return zero.

In th e event tha t misa ligned accesses are supported through a softw a re tra p

ha ndler, the ST231 ma y be configured t o tra p non-a ligned dismissible loads, see theChapter 5: Tr aps: excepti ons and i nterr upt s on page 21. The TLB ca n be configured

to retu rn zero for dismissible loads in cases wh ere they can be executed withoutexception; this is to support peripherals w hich ha ve destructive rea d beha vior.

2.4 Branch unit

The ST230 has one bra nch unit. It support s both r elat ive immedia te bra nches (w itha nd w ithout condition code) a nd a bsolute a nd relat ive jumps a nd calls.

A condit iona l bra nch is performed usin g th e bran d brfins tr uctions. Theseinstructions ha ve tw o opera nds, a condition code register a nd t he immediate offset

of th e bran ch.

A condit iona l bra nch is performed usin g th e goto(immedia te) instru ction. Thisinstruction ha s one operand conta ining the immediat e offset of the bran ch.

An un condit iona l jump is performed us ing t he goto(link register) instruction. Thisinstruction ca uses a cont rol tra nsfer to th e ad dress stored in the l ink register (see

Secti on 3.2.1: L in k r egister on page 13).

An unconditiona l ca ll is performed using t he call(link register) a nd call(immedia te) inst ructions. These instruct ion cause a contr ol tr a nsfer to the a ddress

stored in t he link register (see Secti on 3.2.1: L in k r egister on page 13) or t o the

specified immedia te offset. After t he ca ll th e link register w ill cont a in th e returnaddress .

Du e to pipeline restr ictions a ll bra nches a nd jumps incur a pena lty of one cycle of

s tal l .

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Branch unit 11



2.4.1 Idle mode macro

The idlemode macro is encoded as a bundle conta ining a goto(immedia te) to thesa me bun dle. The idlemode ma cro must be alone in a bund le (otherw ise it ist rea ted as a normal goto).

The idlema cro is a rchitectura lly identical t o the bra nch it is derived from. Whena n int errupt or debug interrupt occurs th e core will exit idle mode a nd jump to the

correct ha ndler.

2.4.1.1 Implementation notes

When a n idlemacro is executed the ST231:

empties th e pipeline, completing a ny ins tr uctions issued before th e idle,

wa its for a l l outsta nding bus tra nsa ctions to complete:

- al l prefetches issued to the bus ha ve completed (responses have come

ba ck),

- al l wri tes issued to the bus have completed (responses have come back).

wa its for the S DI output buffer t o be become empty,

enters idle mode.

The core w ill not enter idle mode if th e perform a nce monitoring count ers a re

ena bled. When t he core enters idle mode a bit is set in t he P M_CR register (see

Secti on 14.3: Cont r ol r egister (PM_CR) on page 124).

The core will exit (or discontin ue ent ry t o) idle mode a nd jump t o the correct

ha ndler on th e follow ing condit ions:

external interrupt,

exception (for exa mple, STB us err or),

debug interrupt.

While in idle mode:

tim ers will continue t o opera te norma lly,

external interrupts will be processed,

the SD I input ports w i ll not accept da ta ,

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the SD I output ports w ill not send out dat a a s they must be empty before the

core enters idle mode,

the periphera l block will a ccept a nd respond to S TB us tr a nsa ctions a s normal,

the DS U continues to opera te a s normal (both via th e ta plink and via the

STBus).

2.4.2 syncins macro

The syncinsma cro can be used to ensure tha t a l l previous instructions ha vecompleted a nd a ll new instructions ha ve not yet sta rted. The syncinsma croensures tha t t he pipeline is empty a nd t he instruction buffer is purged.

The syncinsma cro may only be execut ed in supervisor mode.

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3Architecturalstate

This cha pter describes the a rchitectura l sta te of the S T231 core.

3.1 Program counter (PC)

The P C conta ins a 32-bit byt e add ress pointing t o th e beginning of the current

bundle in memory.

The two LSB s of the P C a re alwa ys zero.

3.2 Register file

The genera l purpose register file conta ins 64 words of 32 bit s, R0... R63.

Reading r egister zero, R0, a lwa ys retur ns t he value zero. Writing va lues to R0, has

no effect on t he processor sta te.

3.2.1 Link register

Register 63, R63, is t he a rchitectura l l ink register used by the callan d returnmecha nism. R63 is updat ed by explicit r egister w rites a nd t he callopera tion. Somerestr ictions a pply to accessing t he link register, see Secti on 4.4.1: Restr i cti ons on

li nk r egister on page 19.

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3.3 Program status word (PSW)

The progra m st a tus word (P SW) cont a ins control informa tion tha t a f fects theopera t ion of th e S T231 processor.

3.3.1 Bit fields

The PSWcont a ins t he follow ing bit fields:

Name Bit(s) Writeable Reset Comment

USER_MODE 0 RW 0x0 When 1 the core is in user mode,

otherwise supervisor mode.

INT_ENABLE 1 RW 0x0 When 1 external interrupts are

enabled.

TLB_ENABLE 2 RW 0x0 When 1 address translation isenabled.

TLB_DYNAMIC 3 RW 0x0 When 1 prefetches, speculative loadsand purge address cause no mapping

violations. When 0 the violations are

ignored.

SPECLOAD_MALIGNTRA

P_EN

4 RW 0x0 When 1 enables exceptions on

speculative load misalignment errors.

Reserved 5 RO 0x0 Reserved



DBREAK_ENABLE 8 RW 0x0 When 1 data breakpoints are enabled.

IBREAK_ENABLE 9 RW 0x0 When 1 instruction breakpoints are

enabled.



Table 1: PSW bit fields

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3.3.2 USER_MODE

The US ER_MODE bit indica tes wh ether the ma chine is in usermode orsupervisormode. When in usermode, the processor ha s rest ricted a ccess:

The TLB (see Chapter 6: Memory tr anslat i on an d pr otect i on on page 29) define

th e level of access t o memory in both usera n d supervisormodes.

In usermode th ere is limited a ccess to cont rol registers (see Chapter 9: Contr olr egister s on page 77).

Certa in instructions ca n not be executed in usermode (see Chapter 18:I nstru cti on set on page 171).

3.3.3 PSW access

The P SW ca n be rea d a s a cont rol regist er, Secti on 3.5: Cont r ol r egister s on page 16.

The pswsetinstruction ca n be used to at omically set a ny number of bits in theP S W. The pswclrinstruction will at omically clear a ny nu mber of bits in th e P SW.

The P SW ca n a lso be upda ted by mea ns of an rfioperation. The required statusw ord should be stored into the SAVED _P SW a nd t he a ddress of the code t o be

executed directly a fter t he cha nge should be stored in th e SAVED _P C. Then

executing a n rfia tomica lly copies t he SAVED _P SW into t he P SW and theSAVED _P C int o the PC.

DEBUG_MODE 12 RW 0x0 When 1 the core is in debug mode.

Reserved [31:13] RO 0x0 Reserved


Table 1: PSW bit fields

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Example: P rocedure t o wr ite t he P S W, (in S T231 a ssembler code),

_sys_set_psw: stw SAVED_PC[$r0.0] = $r0.63;; // Return address stw SAVED_PSW[$r0.0] = $r0.4;; // New valuenop ;;nop ;;nop ;;nop ;;rfi ;;

Note: I nterr upts mu st be di sabled dur in g thi s sequence to prevent SAVED_PC andSAVED_PSW fr om bein g changed.

3.4 Branch register file

The bra nch register file cont a ins 8 single bit bra nch registers, B 0... B 7.

3.5 Control registers

Additiona l a rchitectura l sta te is held in a number of memory ma pped contr ol

registers, Chapt er 9: Cont r ol r egister s on page 77. These regist ers include support

for interrupts and exceptions, and memory protection.

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4Executionpipeline andlatencies

This cha pter describes th e ar chitectura lly visible pipeline and opera tion la tencies.

4.1 Execution pipeline

The ST231 uses a pipelined execution scheme. This pipeline is architecturally

visible in a number of area s:

operation latencies,

bypassing,

usa ge restrictions.

The execution pipeline is th ree cycles long. I t comprises of three st a ge E 1, E2 a ndE3. All operat ions begin in E1. Operan ds a re read or bypa ssed to an operat ion a t

the sta rt of E1. All results ar e writt en at the end of E3.

This execut ion pipeline allows a rith metic a nd load/storeopera tions t o execute forup to thr ee cycles. The results of opera tions w hich complete ear lier t ha n E 3 ar e

ma de ava ila ble for bypassing a s operan ds to subsequent opera tions, though strictly

opera tions do not complete unt il the end of th e E3 sta ge. This is wh en th e

archi tectura l s ta te is upda ted .

The pipeline is designed t o efficiently implement th e seria l execut ion of the code

(see Chapter 16: Execut ion model on page 139).

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4.2 Operation latencies

ST231 opera tions begin in E 1 cycle a nd complete in eith er E 1, E2 or E 3. The t imeta ken for a n opera tion to produce a result is ca lled the opera tion lat ency. For simple

opera tions like addan d subtractth e lat ency is a sing le cycle. For opera tions likemultiplyan d load th e la tency is th ree cycles.

Note: Oper at ional latencies may vary between di f ferent members of the ST200 pr ocessor

fami ly .

4.3 Interlocks

The S T231 provides opera tion la tency in terlock checking w hich enforces t he la tency

betw een cert a in opera t ions. The following la tencies a re checked on th e ST231:

loa d to use,

compa re to bra nch, mult iply to use,

l ink register w rite t o ca ll or retur n.

For these part icular operat ion la tencies the processor w ill au toma tically sta l l the

pipeline to uphold th e interna l lat ency constr a ints . As such there a re no possible

lat ency viola tions for t he a bove cases.

However, for optimal machine usage, bundles containing useful operations shouldbe inserted in order to respect the underlying latency between operations.

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4.4 Additional notes

4.4.1 Restrictions on link register

As a performance optimization a speculative link register (SLR) has been added

w hich is a copy of possible futu re upda tes t o R63. In t he implement a tion th is

register is updat ed earlier in the pipeline tha n R63. SLR is used a s th e source forregister indirect bra nch opera tions.

It is possible to observe th a t S LR is not a tr ue copy of R63. This can only occurs inth e followin g case:

The ta king of a n int errupt or exception just prior to an upda te of R63 but a fter

SL R ha s been cha nged specula tively. Solution; All int errupt a nd exception

ha ndlers mus t explicitly w rite R63 prior to the execution of an rfi, icallorigoto. This requirement can ea sily be met w ith a movopera tion from R 63 toR63 in one of the first bundles of the tr a p ha ndler.

In a ddition register indirect call a ndgoto opera tions requ ire R63 to be sta ble. IfR63 is modified in th e thr ee bundles preceding one of these opera tions th en a n

interlock sta ll w ill occur.

A num ber of opera tions ca nnot ta rget R63 for efficiency reas ons. These include

multiplyoperat ions, byt e a nd ha lf-w ord load operations (see Chapter 18:I nstru cti on set on page 171).

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5Traps:exceptionsand interrupts

In t he ST231 archit ect ure, exceptions a nd int errupt s a re joint ly term ed tra ps. This

chapter describes th e tra p mecha nism.

5.1 Trap mechanism

The S T231 defines tw o ty pes of tra ps:

externa l a synchronous tr a ps (interrupts a nd bus errors),

intern a l synchronous tr a ps (exceptions result ing from opera tion execut ion).

A tr a p point is the point in t he progra m execut ion w here a t ra p occurs. All bundles

executed before the t ra p point w il l ha ve completed upda ting a rchitectura l sta te;

a nd no a rchitectura l stat e will ha ve been unda ted by subsequent bundles. For a nexception, the tr a p point is th e (st a rt of th e) bundle w hich ca used th e exception. For

a n int errupt, th e tra p point is (th e sta rt of) the bundle wh ose execution ha s been

interrupted. Typica lly this is a bundle tha t h a d been executed shortly a f ter the

interrupt wa s ra ised or enabled.

The flow diagram, F igu re 16in Secti on 16.2, defines when a tra p is ta ken. The aim

of th is cha pter is to define the steps tha t a re ca rried out w hen a t ra p is to be ta ken.

In effect, ta king a t ra p ca n be viewed as executing a n operat ion w hich bra nches to

th e required ha ndler, w ith a number of side effects. The side effects a re defined by

the st a tements below. An externa l interrupt is trea ted a s a n E XTERN _INT

exception, with only debug int errupt s being ha ndled different ly.

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At t he tra p point , the ST231 tra nsfers execution to the tra p han dler, sta rt ing at the

a ddress held in t he HANDLE R_P C control register, a nd sa ves the execution sta te

a s detailed inSecti on 5.3: Saved execut i on stat e

. All opera tions issued before t hetrapping bundle are allowed to complete. All operations issued after and including

the t ra pping bundle ar e disca rded. The a rchitectura l sta te, w ith t he exception of

sa ved execution sta te, is exactly th a t a t t he tra p point . Hence ST231 interrupts a nd

exceptions can be considered precise.

Tra ps ar e ha ndled str ictly (in order), an d indivisibly with r espect to the bundle

s t ream.

5.2 Exception handling

Due to the fa ct tha t t here may be more tha n one opera tion executing a t once, i t is

possible to ha ve more th a n one exception throw n in a bundle. However, only th e

highest priority exception is passed t o th e ha ndler.

5.3 Saved execution state

Directly following a tra p the sa ved execution sta te defines the rea son for the tr a p

a nd t he precise tra p point in t he execution flow of th e processor. Control registers

a re used to store these va lues for use by the ha ndler routine.

Ta king a n exception ca n be summ a rized as:

NEXT_PC HANDLER_PC; // Branch to the exception handler

EXCAUSE HighestPriority(); // Store informationEXADDRESS ExceptAddress(EXCAUSE);// for the handler

SAVED_PSW PSW; // Save the PSW and PCSAVED_PC BUNDLE_PC;

PSW[USER_MODE] 0; // Enter supervisor modePSW[INT_ENABLE] 0; // Disable interruptsPSW[IBREAK_ENABLE] 0; // Disable instruction breakpointsPSW[DBREAK_ENABLE] 0; // Disable data breakpoints

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Where t he funct ion HighestPriorityretur ns t he highest priority exception fromthose tha t h a ve been thr own (please refer to Secti on 5.6). The ExceptAddressfunction defines the value th a t is st ored into the E XADD RES S control register. I t s

return va lue will either be 0or the address of da ta or instruction which hastr iggered th e exception.

Therefore,

Where valueis the optiona l argum ent th a t w il l ha ve been passed to the THROW(see Section 17.4.5: Excepti ons on page 157) wh en the exception wa s generat ed.

The rfi (retur n from int errupt ) opera tion is used to recommence execution at th etra p point. An rfioperat ion w ill cause the following st a te upda tes:

variable ExceptAddress(exception);is equivalent to:

IF ((exception = DBREAK) OR (exception = MISALIGNED_TRAP) OR (exception = CREG_NO_MAPPING) OR (exception = CREG_ACCESS_VIOLATION) OR (exception = DTLB) OR (exception = ITLB)) THEN variable value;ELSE

variable 0;

PC SAVED_PC;

PSW SAVED_PSW;

SAVED_PC SAVED_SAVED_PC;

SAVED_PSW SAVED_SAVED_PSW;

// Address execution control is// transferred to by rfi. Can be

// altered during the exception

// handler routine.

// Restore saved_psw. Can be

// altered during the exception

// handler routine.

// Restore previous saved_pc

// Restore previous saved_psw

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5.4 Interrupts

All int errupt s a re effectively trea ted by t he ST231 as a n exception of ty peEXTER N_INT. In dividua l interrupt l ines a re indica ted by registers in t he interrupt

controller, Chapter 12: I nterr upt contr ol l er on page 95.

5.5 Debug interrupt handling

P lease refer t o Chapt er 13: Debugging support on page 105.

5.6 Exception types and priorities

The E XCAUS EN O cont rol register, in Tab le 2gives the cau se of the la st exception.

Sin ce only one exception is ra ised at a t ime, simulta neous exceptions a re

prioritized.

For ba ckwa rd compat ibil i ty th e exception cause is a lso ava ilable as a bit-f ield by

reading th e EXCAU SE register. The EXCAU SE register is read only and a lwa ys

returns 1

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EXTERN_INT 2 There was an external interrupt.

IBREAK 3 An instruction address breakpoint has occured.

ITLB 4 An instruction related TLB exception has

occured.

SBREAK 5 A software breakpoint was found.

ILL_INST 6 The bundle could not be decoded into legalsequence of operations or a privileged

operation is being issued in user mode.

SYSCALL 7 System call.

DBREAK 8 A breakpoint on a data address has beentriggered.

MISALIGNED_TRAP 9 The address is misaligned and misalignedaccesses are not supported.

CREG_NO_MAPPING 10 The load or store address was in control

register space, but no control register exists at

that exact address.

CREG_ACCESS_VIOLATIO

N

11 A store to a control register was attempted

whilst in user mode.

DTLB 12 A data related TLB exception has occured.

Reserved 13 Reserved

SDI_TIMEOUT 14 One of the SDI interfaces timed out while being

accessed.

Name Value Comment

Table 3: EXCAUSENO_EXCAUSENO values

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5.6.1 Illegal instruction definition

An illegal inst ruction exception is caused w hen a n illegal bun dle is executed. Alega l bundle a nd a ll sylla bles conta ined in i t must conform t o the restrictions as

deta iled in Chapter 18: I nstr uct ion set on page 171.

A legal bund le a nd a ll syllables conta ined in it must conform to the followin g:

All sylla bles must be valid opera tions.

A bundle must ha ve a stop bitth a t is, four zero stop bitsa re i llegal .

U nused opcode fields must be set t o zero, including bit 30.

Any branch, call, rfi, pswsetan d pswclropera tion must appear a s the f irstsylla ble of a b undle.

Multiply operat ions must a ppear a t odd word addresses.

Long immediat e extensions must a ppea r a t even word addresses.

Immediat e extensions must a ssocia te with a n operat ion tha t is in the same

bundle and ha s a n immedia te format tha t can be extended.

There ma y be no more tha n one immedia te extension a ssociat ed wit h a single

operation.

A privileged opera tion ca n only be executed in supervisormode. This in cludesrfi, pswset, pswclr, prginspgan d prgins.

There can only be one opera tion requ iring t he loadstoreunit in each bundle.

This includes sync, prgset, prgadd, prginspg, pswset, pswclr, rfi, ldb, ldh,ldw, stb, sthan d stw.

The sbrk opera tion must ha ve the stop bit set.

Destina tion registers in a bundle have t o be unique, w ith t he exception of R0.

ldb, ldhan d muloperat ions must n ot ha ve R63 as a destinat ion register.

prginsa n d syscall must be alone in a bundle.

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5.7 Speculative loadconsiderations

Speculative (or dismissible) loads are defined such that they execute as normalloa ds except in t he follow ing cas es:

1 The address is in a region where a speculat ive load ma y be destructive. In thiscase the SC U (see Secti on 6.7: Specul ati ve cont r ol u ni t (SCU ) on page 47) should

be setup t o prevent specula tion to this region. In t his case a zero is a lwa ys

returned a nd no a ccess is ma de to the m emory.

2 A norma l load would cause a n exception. G enera lly, in t his case, th e load isconsidered to ha ve been incorrectly specula ted a nd t he da ta w ill not ut i l ized in

th e correct execution of the progra m. Zero is retur ned by defa ult, t he follow ing

tw o sub-sections det a il the exceptions to t his beha vior.

3 If a dismissible load causes a bus error th en a bus error exception is a lwa ysra ised. The TLB a nd/or SC U should a lwa ys be set up to prevent dismissible

loa ds from cau sing bus err ors (see Chapter 6: Memory tr anslat i on and protect ion

on page 29).

5.7.1 Misaligned implementation

Applica tion or syst em softwa re ma y require misalignment support, w ith misa ligned

a ccesses being correctly int erpreted by th e exception ha ndler. To improve

speculative load support for misa ligned a ddresses, a contr ol va luePSW[SPECLOAD_MALIGNTRAP_EN] can be set which causes speculative loads

to tra p on misa ligned addr esses ra ther t ha n return ing zero (see Secti on 3.3:Program statu s word (PSW) on page 14).

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6Memorytranslation andprotection6.1 Introduction

The ST230 provides full memory tr a nsla tion a nd protection by mea ns of a

tr a nsla tions looka side buffer (TLB ).

It a l lows t he running of memory m a na ging operat ing systems (OS) (for exam ple,Linux) together wit h some level of backwa rd compat ibil i ty support for th e IP U a nd

DP U functions under a non memory ma na ged OS (for example, OS21).

6.2 Overview

The ST230 has a sma ll inst ruction TLB (ITLB ), a sm a ll dat a TLB (DTLB ) a nd a

lar ger un ified TLB (U TLB ).

The ITLB performs instr uction a ddress tra nslat ions a nd a cts as a cache for a ddress

tra nslat ions stored in the U TLB . When the ITLB misses i t a utoma tically updat es

from t he UTLB .

The DTLB performs da ta address tra nslat ions a nd a cts a s a ca che for a ddress

tra nslat ions stored in the U TLB . When the DTLB misses i t a utoma tically updat es

from t he UTLB .

When the U TLB is cha nged, the ITLB a nd DTLB a re not updat ed. The ITLB a nd

DTLB can be flushed under softw a re cont rol by means of the TLB _C ONTROL

register. See Secti on 6.5.8: TL B_CONTROL on page 41.

The ITLB a nd D TLB a ct a s sma ll ca ches t ha t keep copies of the currently a ctive

tra nslat ions. Only tra nslat ions tha t a re shared or ma tch the current a ppl icat ion

(ASI D) specific identifier a re loa ded into th e ITLB a nd D TLB .

30 TLB sizesPRELIMINARY DATA

UTLB fully a ssociat ive buffer w hich is ma na ged by the softw a re

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UTLB fully a ssociat ive buffer w hich is ma na ged by the softw a re.

ITLB fully a ssocia tive buffer with LRU repla cement.

DTLB fully a ssocia tive buffer with LRU repla cement.

6.3 TLB sizes

The S T230 ha s t he following TLB configura tion:

The U TLB size ca n be determin ed eith er by rea ding t he core version regist er (usinga lookup ta ble) or reading t he TLB _RE P LACE register a f ter reset.

6.4 Address space

6.4.1 Physical addresses

The S T230 TLB support s up-to 32-bit (4-G byt e) of physica l a ddr ess spa ce. This

a llows future va riant s t o support up to 45 bits of physical a ddress space.

6.4.2 Virtual addresses

The virt ua l ad dresses a re 32-bits. The TLB perform s th e ma pping from virt ua l to

physica l a ddresses using one of t he following pa ge sizes: 8KB , 4MB a nd 256MB .

Control register a ddresses ar e not t ra nslat ed. They t a ke precedence over TLB

translat ions.

6.4.3 Caches

The level 1 caches a re virtu a lly indexed and physically t a gged. The cache ta g RAM

lookup occurs in pa ra llel w ith th e TLB lookup.

Item Value

DTLBsize 8 entries

ITLBsize 4 entries

UTLBsize 64 entries

Address space 31PRELIMINARY DATA

6 4 3 1 Instruction cache

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6.4.3.1 Instruction cache

Figure 2: Instruction cache

32 Address spacePRELIMINARY DATA

The inst ruction ca che is 32Kb direct m a pped a nd built from 512 x 64 byt e lines

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The inst ruction ca che is 32Kb direct m a pped a nd built from 512 x 64 byt e lines.

The virt ua l a ddress bit s [14:06] a re used to index th e instr uction ca che RAMs.

Virtua l a ddress bits [31:13] a re sent t o the ITLB for t ra nslat ion. The tr a nslat ed

physical a ddress bits [31:13] from the ITLB is then compared a ga inst t he

instruction cache ta g.

Virt ua l a ddress bits [05:00] a re used t o select t he correct byt es from the ca che line.

Address space 33PRELIMINARY DATA

6.4.3.2 Data cache

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Figure 3: Data cache

34 Control registersPRELIMINARY DATA

The da ta cache is 32Kb four w a y set a ssocia te a nd built from 4 x 256 x 32 byt e lines.

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The virt ua l ad dress bits [12:05] a re used to index the da ta cache RAMs.

Virtua l a ddress bits [31:13] a re sent t o the D TLB for t ra nslat ion. The tr a nslat ed

physica l a ddress bits [31:13] from the DTLB a re then compared a ga inst t he da ta

ca che ta g .

Virt ua l a ddress bits [04:00] a re used t o select t he correct byt es from the ca che line.

6.5 Control registersA full list of control regist ers is det a iled in Chapter 9: Cont r ol r egister s on page 77.

6.5.1 PSW

The TLB can be ena bled a nd disa bled by a bit in t he P SW (see Chapter 3:

Ar chi tectu r al state on page 13).

When a ddress tra nslat ion is disabled (TLB _ENABL E = 0) the virtua l add ress will

be used as th e physical address. In th is ca se, the default a tt r ibutes for data a ccesses

w ill be unca ched and n o TLB exceptions will be th rown .

6.5.2 TLB_INDEX

When th e TLB _IND E X register is w ritt en subsequent r ead /wr ites to the

TLB _EN TRYX registers w ill be to th e indica t ed U TLB entr y.


ENTRY [7:0] RW 0x0 Determines which of the 64 TLBentries is mapped to the

TLB_ENTRYx registers. Writing a

value to this register that is greater

than the maximum UTLB entry

available has no effort (the entry is not

updated).

Reserved [31:8] RO 0x0 Reserved.

Table 4: TLB_INDEX bit fields

Control registers 35PRELIMINARY DATA

6.5.3 TLB ENTRY0

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_

This r egister ma ps bits [31:00] of the TLB entr y. The ent ry is chosen by w riting to

th e TLB _IND E X register.

Writ ing zero to th is register disa bles the page.


ASID [7:0] RW 0x0 Indicates which process this page

belongs to.

SHARED 8 RW 0x0 Page shared by multiple processes(ASIDs).

PROT_SUPER [11:9] RW 0x0 A three bit field that defines the

protection of this region in supervisormode.

PROT_USER [14:12] RW 0x0 A three bit field that defines the

protection of this region in user mode.

DIRTY 15 RW 0x0 Page is dirty. When this bit is 0 write

accesses to this page (when write

permission is allowed) cause a

TLB_WRITE_TO_CLEAN exception.

When this bit is 1 writes to this page

(when write permission is allowed) arepermitted.

POLICY [19:16] RW 0x0 Cache policy for this page.

SIZE [22:20] RW 0x0 Size of this page (also used to disable

the page).

PARTITION [24:23] RW 0x0 Data cache partition indicator.

RESERVED [31:25] RO 0x0 Reserved.

Table 5: TLB_ENTRY0 bit fields


Tab le 6lists th e possible va lues of the P OLI CY field.

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Tab le 7lists of th e possible values of the S IZE field:

Name Value Comment

UNCACHED 0 Uncached mode. Reads and write that miss the

cache are uncached.

CACHED 1 Cached mode. Reads that miss the cachecause the cache to be filled. Writes that hit the

cache are written into the cache. Writes that

miss the cache are sent to the write buffer.

WCUNCACHED 2 Write combining uncached. Writes that miss the

cache are sent to the write buffer. Reads that

miss the cache are uncached.

Reserved 3 Reserved (On the ST230 reserved cache

policies default to uncached).



Reserved 5 Reserved (On the ST230 reserved cachepolicies default to uncached).





Table 6: TLB_ENTRY0_POLICY values

Name Value Comment

DISABLED 0 Page is disabled.

8K 1 8Kb page.

4MB 2 4MB page.

Table 7: TLB_ENTRY0_SIZE values


Name Value Comment

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Tab le 8lists of the possible values of the PARTITION field:

Tab le 9l ists of th e possible va lues of t he P ROT_U SE R a nd P ROT_SU P ER fields:

256MB 3 256MB page.

Reserved 4 Reserved (on the ST230 reserved page sizes

disable the page).


disable the page).


disable the page).

Reserved 7 Reserved (on the ST230 reserved page sizesdisable the page).

Name Value Comment

REPLACE 0 Place in the way specified by the replacement

counter and increment the counter.

WAY1 1 Place in the way 1 only.



Table 8: TLB_ENTRY0_PARTITION values

Name Value Comment

EXECUTE 1 Execute permission

READ 2 Read (Prefetch & Purge) permission

WRITE 4 Write permission

Table 9: TLB_PROT values

Name Value Comment

Table 7: TLB_ENTRY0_SIZE values


6.5.4 TLB_ENTRY1

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This r egist er a llows a ccess t o bits [63:32] of the TLB ent ry. The ent ry is chosen by

wr iting to th e TLB _IND EX register

6.5.5 TLB_ENTRY2

This r egist er a llows a ccess t o bits [95:64] of the TLB ent ry. The ent ry is chosen by

wr iting t o the TLB _IND EX r egister.


VADDR [18:0] RW 0x0 The upper 19 bits of the virtual

address. For 4MB pages only the

upper 10 bits of this field are

significant. For 256MB pages only theupper 4 bits of this field are significant.




PADDR [18:0] RW 0x0 The upper 19 bits of the physical

address. For 4MB pages only the

upper 10 bits of this field aresignificant. For 256MB pages only the

upper 4 bits of this field are significant.




6.5.6 TLB_ENTRY3

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This r egister m a ps bits [127:96] of the TLB entr y. The ent ry is chosen by w ritin g t o

th e TLB _IND E X register.

6.5.7 TLB_REPLACE





LFSR [15:0] RW 0xffff Random number used to determine

which entry to replace next.

LIMIT [23:16] RW 0x40 Number of TLB entries that will be

replaced.


Table 13: TLB_REPLACE bit fields

Figure 4: REPLACE register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Load from REPLACE

LFSR


The replacement regist er is used by the softwa re to ra ndomly decide which TLB

entr y to replace. The va lue of the RE P LACE field is genera ted in a pseudo-ra ndom

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e t y to ep ace. e a ue o t e C e d s ge e a ted a pseudo a do

ma nner using a 16-bit l inea r feedba ck shif t register (LFS R) generat ing a ma ximum

length sequence (ta ps on bits 3, 12, 14 an d 15).

A read from th e TLB _RE P LACE r egister return s the current LF SR a nd LI MIT

values, the L FS R is t hen clocked to generat e a new va lue. The current va lue of the

LFS R field can be changed by w riting t o the TLB _RE P LACE register.

The LI MIT field is reset to t he num ber of entries in t he TLB 1. The LI MI T field can

be cha nged by writing t he TLB _RE P LACE register. I t is expected tha t t he softw a re

w ill reduce the va lue of the L IMI T field in order to reserve a n umber of TLB entr iesfor a f ixed ma pping.

The LIMI T field is not used by the ha rdw a re but is included to al low th e softw a re to

quickly determine th e next TLB entr y to replace. A suggest ed replacement

a lgorithm is a s follows:

unsigned replace, lfsr, limit, index;

// Read replace register to get LIMIT and LFSRreplace = VOLUINT(LXTLB_REPLACE);

// Extract fieldslfsr = LXTLB_REPLACE_LFSR(replace);limit = LXTLB_REPLACE_LIMIT(replace);

// Decide which entry to replace

index = (lfsr * limit) >> 16;

// Select the correct entryVOLUINT(LXTLB_INDEX) = index;

Note: The mullhuin str uction can be used to extr act th e LFSR an d L IM I T f ield s fr om t heTLB_REPLACEregister an d per form the mu lt ipl y. The r esul t i s then shi fted r ight by

16 bit s to obtai n t he ent r y number to replace.

1. This depends on w hich core is implemented.


6.5.8 TLB_CONTROL

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B efore the ITLB or DTLB a re f lushed, the har dwa re will ensure tha t a l l

outst a nding w rites to the U TLB ha ve completed.

6.5.9 TLB_ASID

6.5.10 Coherency

When flushing t he ITLB , DTLB , changing t he current ASID or upda ting t he UTLB

the softwa re must a l low enough t ime for the change t o ta ke effect:

To ensur e coherency a follow ing such a n upda te a sync(to ensure the st ore ha scompleted) followed by a syncins(to a llow th e cha nge to ta ke effect) must be used.

In a ddi t ion to the above the sof twa re must be a wa re tha t updat ing the UTLB wi l l

not updat e the ITLB or DTLB . I f a ma pping is cha nged in th e UTLB tha t is a lso

present in the ITLB or DTLB then t he ITLB or D TLB must be f lushed. In th is ca se

the syncan d syncinsshould be performed a fter t he flush.


ITLB_FLUSH 0 RW 0x0 Writing a 1 to this bit flushes the entire

ITLB. Writing 0 to this bit has no effect.

This bit always reads as zero.

DTLB_FLUSH 1 RW 0x0 Writing a 1 to this bit flushes the entire

DTLB. Writing 0 to this bit has no

effect. This bit always reads as zero.


Table 14: TLB_CONTROL bit fields


ASID [7:0] RW 0x0 Address space identifier. Indicates thecurrent process ID.


Table 15: TLB_ASID bit fields


6.5.11 TLB_EXCAUSE

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When t he TLB ra ises a n exception this register is upda ted w ith i ts cause.

The possible exceptions a re:

NO_MAP P ING : The UTLB ha d no mapping for th e virtua l addr ess.

P ROT_VIOLATION: An a tt empt ha s been ma de to violat e the permissions of a

page.

WRI TE_TO_CL EAN: A pa ge tha t w a s clea n is being wr itt en to. This a llow s th e

softw a re ma na ging the UTLB to update th e mast er copy of the ta ble kept in

memory a nd to ha ndle a ny sha red pa ges.

MU LTI_MAP P ING : There were multiple hits in th e UTLB . The softw a re ma na ging

the TLB should ensure tha t t his does not ha ppen.

When a NO_MAP P ING exception is raised the given page is not in the U TLB a nd

th e DTLB (for da ta a ccesses) or the I TLB (for inst ruction a ccesses).

When a P ROT_VIOLATION exception for instr uction a ccesses is r a ised, th e given

page ma y be in the ITLB , DTLB , U TLB or any combina tion of the a bove.

When a P ROT_VIOL ATION or WRI TE _TO_C LE AN exception is r a ised for da ta

a ccesses th e given pa ge ma y be in the ITLB , DTLB , U TLB or an y combinat ion of theabove.

It is possible for a page t o be held in the ITLB or DTLB but n ot in th e U TLB if the

softw a re chose not t o purge the ITLB /DTLB wh en a page w a s replaced.

When a MU LTI_MAP P ING exception is ra ised, the virtua l a ddress ma ps to more

tha n one page in the U TLB . In t his ca se the IN_U TLB a nd IND EX fields of the

TLB _EXCAUS E a nd the E XADD RE SS register will cont a in zero.

Name Value Comment

NO_MAPPING 0 No mapping was found

PROT_VIOLATION 1 A protection violation occured.

WRITE_TO_CLEAN 2 A write to a clean page.

MULTI_MAPPING 3 Multiple mappings were found.

Table 16: TLB_EXCAUSE_CAUSE values

TLB description 43PRELIMINARY DATA

When a TLB exception is ta ken, the softw a re can d etermine if th e given pa ge is in

th e UTLB by checking th e IN_U TLB bit.

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6.6 TLB description

The TLB functiona lity is contr olled completely t hrough a ccesses to t he cont rolregisters provided.

6.6.1 Reset

After reset t he content s of the U TLB a re undefined. B efore the TLB is enabled a ll

entr ies must be progra mmed (or clea red) to prevent und efined beha vior.


INDEX [7:0] RW 0x0 TLB index of excepting page.

Reserved [15:8] RO 0x0 Reserved

CAUSE [17:16] RW 0x0 Cause of current TLB exception.

SPEC 18 RW 0x0 When 1 indicates that this exceptionwas caused by either a purge

address, prefetch or speculative load

instruction.

WRITE 19 RW 0x0 When 1 indicates that this exception

was caused by an attempted write to a

page (store). When 0 indicates that

this exception was caused by an

attempted read, prefetch or purge of apage.

IN_UTLB 20 RW 0x0 When 1 the exception address is in

the UTLB and the INDEX field is valid.

When 0 the exception address was

not in the UTLB and the INDEX field isinvalid.


Table 17: TLB_EXCAUSE bit fields

44 TLB descriptionPRELIMINARY DATA

6.6.2 UTLB arbitration

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The DTLB , ITLB a nd TLB contr ol registers ha ve to a rbitra te for access t o the

U TLB . The priority of U TLB a ccesses ar e as follows :

1) TLB control register access,

2) D TLB ,

3) ITLB .

6.6.3 Exceptions

When th e TLB th rows a n exception it jumps to the exception vector an d upda tes t he

TLB _EXCAUS E, EXADD RES S and EXCAUS ENO registers .

When a DTLB exception is ra ised, the E XADD RE SS register contains t he virtua l

effective a ddress th a t caused t he exception.

When a n ITLB exception is ra ised, the EXADD RE SS register w ill conta in the

virtua l a ddress of the sylla ble tha t caused a n exception. In t he case of possible

multiple ITLB exceptions, the exception with the lowest syllable address is thrown.

The SAVED_P C a nd S AVED _P SW sta ck a re also updated in th e same w a y a s other

t raps .

As noted a bove, the TLB _EXCAUS E register indica tes th e na ture of the ITLB or

DTLB exception.

Note: M isal igned l oads and contr ol r egister violat ions are not consid ered T L B exceptions.

Deta ils of the EXCAUS ENO register can be found in Secti on 5.6: Excepti on types

and pr iori t ies on page 24.

6.6.4 Instruction accesses

Inst ruction a ccesses ar e alw a ys ca ched (th e ca che policy is ignored).

TLB description 45PRELIMINARY DATA

Instruction access to virtual address (VA)

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Figure 5: Instruction access

TLB_EXCAUSE NO_MAPPING

THROW ITLB_EXCEPTION

TLB_EXCAUSE MULTI_MAPPING


TLB_EXCAUSE PROT_VIOLATION


PSW[TLB_ENABLE]?

UTLB hit?YesNo

Cached memory access to

PA

No

ITLB hit?

Yes

NoYes

Protection

violation? Yes

Multiple hits? YesNo

Physical Address (PA) =

Virtual Address (VA)

No

PA = Translated VA

46 TLB descriptionPRELIMINARY DATA

6.6.5 Data accesses

Reading and w ri t ing da ta ca n be summarized by F i gu re6

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Reading and w ri t ing da ta ca n be summarized by F i gu re6:

Figure 6: Data access

TLB_EXCAUSE PROT_VIOLATIONTHROW DTLB_EXCEPTION

TLB_EXCAUSE NO_MAPPINGTHROW DTLB_EXCEPTION

PSW[TLB_ENABLE]?

No

Uncached memory accessto PA

No

Data access to virtual address (VA)

UTLB hit?

Yes

Yes

All other VAs

Protectionviolation?

NoYes

VA in control register space

Control register access andpermissions

Multiple hits?

TLB_EXCAUSE MULTI_MAPPINGTHROW DTLB_EXCEPTION

YesNo

Access type

Cached memory access toPA

Write

Read

Yes

Physical Address (PA) =Virtual Address (VA)

Read

PA = Translated VA

Page clean?

TLB_EXCAUSE WRITE_TO_CLEANTHROW DTLB_EXCEPTION

Yes

No

CachedNo

DTLB hit?Yes

No

Speculative control unit (SCU) 47PRELIMINARY DATA

6.7 Speculative control unit (SCU)

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The SC U filters physical specula tive load addresses (both cached and uncached)a nd prefetches tha t miss t he ca che to ensure tha t speculat ive bus requests a re not

sent out t o periphera ls an d unma pped memory r egions.

The SC U support s four regions of memory a ligned to the sma llest TLB page size

(8 Kbyt e). If th e physical a ddress of the speculat ive load/prefetchad dress fa l lswith in one of the four supported r egions i t w il l be a llow ed, otherw ise the SC U

a borts t he specula tive load/prefetch a nd zero is retur ned or th e prefetch is

cancelled.

The regions a re configured using t he SC U _B ASE x an d SC U _LI MITx control

registers. A region ma y be disabled by setting t he base t o be larger t ha n t he l imit.

The S CU resets so ea ch of the four regions cover t he w hole of memory. This a llow s

specula tive loa ds t o be issued before the SC U ha s been initial ized.

Figure 7: ST231 instruction and data cache fetch

Instruction and data cache fetch

Speculative load/prefetch bit

SCU

Speculative

control unit

CMC

Cache miss address

Speculative

abort

Speculative

abort

48 Speculative control unit (SCU)PRELIMINARY DATA

6.7.1 SCU_BASEx

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The SC U base register defines the physica l sta rt a ddress of the region w here

specula tive load s/prefetches ar e permitt ed. This region is a ligned to t he sma llest

pag e size (by virt ue of the rea d only zero bits). The ba se a ddress is inclusive, so

setting B ASE = = LIMI T defines an 8 Kbyte region.

6.7.2 SCU_LIMITx

The SC U base register defines th e physica l end a ddress of the region wh ere

specula tive loa ds a re permitt ed. This region is aligned to th e sma llest page size (by

virtu e of the r ea d only zero bits ). The limit a ddress is inclusive, so sett ing

B ASE = = LIMI T defines an 8 Kbyte region.

6.7.3 Updates to SCU registers

Any cha nges to S CU registers will ta ke effect for futur e bus tra nsa ctions. The

softw a re should therefore issue a syncbefore updating t he SC U if i t w ishes to knowwh ich tr a nsa ctions ha ve been processed with t he new settings.


BASE [18:0] RW 0x0 Upper 19 bits of the base of this

region.


Table 18: SCU_BASE0 bit fields


LIMIT [18:0] RW 0x0x7

ffff

Upper 19 bits of the limit of this region.


Table 19: SCU_LIMIT0 bit fields

PRELIMINARY DATA

7

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7Memorysubsystem

This cha pter describes t he operat ion of t he S T231 processor memory s ubsyst em.

The memory subsy stem in cludes th e ca ches, protection units, w rite buffer, prefetch

cache, tr a nsla tion looka side buffer (TLB ) a nd t he core memory controller (CM C).

The memory subsys tem is split broa dly int o tw o pa rt s, th e instr uction side (I-side)

a nd t he da ta side (D-side). The CMC interfaces these tw o halves to the S TB us port.

The I-side, conta ining t he inst ruction cache, supports t he fetching of instru ctions.The D-side, conta ining th e dat a cache, prefetch cache a nd w rit e buffer, support t he

stor ing a nd loading of data .

The TLB performs m emory a ddress t ra nsla tion a nd protection. The function of th e

TLB is deta iled in Chapter 6: Memory tr anslat i on and protect ion on page 29.

The ST231 ensures t ha t da ta a ccess a re coherent w ith other da ta a ccesses. There is

no guar a ntee of coherency betw een inst ruction a nd da ta a ccesses (see Secti on 7.5.2:

Coher ency betw een I -si de and D-sid e on page 64) or betw een the core a nd externa l

memory. To ensur e coherency da ta must be purged from the core as described lat er

in th is cha pter.

The function of the st rea ming da ta interfa ce (S DI ) is described in Chapter 8:

Str eami ng data i nt er face (SDI ) on page 67.

50 Memory subsystemPRELIMINARY DATA

7.1 Memory subsystem

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7.2 I-side memory subsystemWithin th e ST231 the inst ruction buffer is responsible for issuing inst ructions t o

th e processor core. The inst ruction ca che fetches cache lines from m emory, via th e

CM C a nd sends groups of up to four opera tions to the inst ruction buffer.

Figure 8: Memory subsystem block diagram

I-Side MemorySubsystem

Write Buffer

Prefetch Cache

Data Cache

InstructionCache

WriteData

Prefetch

Request

Prefetch

Data

Writes &(Reads/Prefetch/Sync/Flush)

Prefetches &

(Reads/Writes/Flush)

Fetched

Data

PC

Read

4x32 bit

ReadRequest

Read ResponseCache Line

Read/Write/

Flush/Sync/Prefetch

Request

ReadWord

Busy

Busy

InstructionBuffer

LoadStoreUnit

(LSU)

PC andBranch Unit

CMC

Uncached

Read/Writes& Cache Fill

D-SideMemory

Subsystem

STBUS

I-side memory subsystem 51PRELIMINARY DATA

7.2.1 Instruction buffer

The instruction buffer a tt empts to fetch a head in the instr uction st ream in order t o

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keep its buffer full . When a bra nch is ta ken the instr uction buffer is inva lida ted a nda fetch star t ed from the t arget a ddress .

After a bra nch th e inst ruction buffer will ta ke one cycle to fetch th e next bundle

from th e ca che, this mea ns t he ST231 will sta ll for one cycle. If th e bra nch is to a

bundle tha t spans t wo cache l ines then i t wil l ta ke tw o cycles to fetch th e bundle

a nd t hus t he ST231 will sta ll for t w o cycles.

7.2.2 Instruction cache

Inst ructions a re a lwa ys cached; there is no support for unca ched instr uction

fetching. Self modifying code (loa ders for exa mple) must inva lida te t he cache

explicitly.

The inst ruction cache is a 32 Kby te direct ma pped cache. The cache is ma de up from

512 sets. E a ch set conta ins one 64-byt e line.

When a virtua l (byte) a ddress is submitted t o the cache i ts bits a re used as follows:

B its [05:02] select th e w ord offset w ithin th e line.

B its [14:06] select t he set t ha t could conta in th e required cache line.

B its [31:15] a re tra nslat ed by th e TLB . The resulta nt physica l a ddress forms t he

ta g w hich is used to check if the req uired line is in th e ca che.

The inst ruction cache receives fetch req uests fr om the inst ruction buffer an d

retu rns a group of up to four 32-bit opera tions (16 bytes).

When instructions a re requested from the cache i t uses t he a ddress to determine

wh ether they a re alrea dy present in the cache. I f the instructions are not in the

cache, they a re fetched from memory a nd st ored into th e cache, during which time

th e processor will sta ll. The request ed instru ction bundle is then ret urned t o th e

inst ruction buffer.

52 I-side memory subsystemPRELIMINARY DATA

7.2.2.1 Invalidating the

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