THE KAVERY ENGINEERING COLLEGE, MECHERI

ME VLSI DESIGN

INTERNAL TEST – 1

Sub: SSDMS Marks : 50

Time: 1.30 hours 5*2=10

2- marks

1. Draw the band diagram of MOS capacitor in weak inversion.

2. Define gate bias dependent mobility.

3. Define DIBL.

4. What is non quasi static modeling?

5. What are the requirements for modeling a MOSFET for RF application?

10 -marks

1. Explain about i)Meyer model

ii) Velocity saturation model

2. Explain the unified MOSFET C-V Model.

3. What is parameter extraction? How is it performed in RF MOSFET devices?

4. What is Flicker noise?