spring 2010, mar 10elec 7770: advanced vlsi design (agrawal)1 elec 7770 advanced vlsi design spring...
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Spring 2010, Mar 10Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design
Spring 2010Spring 2010Gate SizingGate Sizing
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
ECE Department, Auburn UniversityECE Department, Auburn University
Auburn, AL 36849Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10
Clock DistributionClock Distribution
clock
Spring 2010, Mar 10Spring 2010, Mar 10 22ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Clock PowerClock PowerPclk = CLVDD
2f + CLVDD2f / λ + CLVDD
2f / λ2 + . . .
stages – 1 1= CLVDD
2f Σ ─ n= 0 λn
where CL = total load capacitance
λ = constant fanout at each stage in distribution network
Clock consumes about 40% of total processor power.
Spring 2010, Mar 10Spring 2010, Mar 10 33ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Delay of a CMOS GateDelay of a CMOS Gate
CMOSgate
CLCgCint
Propagation delay through the gate:
tp = 0.69 Req(Cint + CL)
≈ 0.69 ReqCg(1 + CL /Cg)
= tp0(1 + CL /Cg)
Gate capacitanceIntrinsic capacitance
Spring 2010, Mar 10Spring 2010, Mar 10 44ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
RReqeq, , CCgg, , CCintint, , andand Width SizingWidth Sizing
RReqeq: equivalent resistance of “on” transistor, : equivalent resistance of “on” transistor, proportional to proportional to L/W; scales as L/W; scales as 11/S, /S, S S = sizing = sizing factorfactor
CCgg: gate capacitance, proportional to : gate capacitance, proportional to CCoxoxWLWL; ; scales as Sscales as S
CCintint: intrinsic output capacitance ≈ : intrinsic output capacitance ≈ CCgg, for , for submicron processessubmicron processes
ttp0p0: intrinsic delay = 0.69: intrinsic delay = 0.69RReqeqCCgg; ; independent of independent of sizingsizing
Spring 2010, Mar 10Spring 2010, Mar 10 55ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Effective Fan-out, Effective Fan-out, ff Effective fan-out is defined as the ratio Effective fan-out is defined as the ratio
between the external load capacitance and between the external load capacitance and the input capacitance:the input capacitance:
ff == CCLL/C/Cgg
ttpp == ttp0p0(1 + (1 + ff ) )
Spring 2010, Mar 10Spring 2010, Mar 10 66ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Sizing an Inverter ChainSizing an Inverter Chain
Cg1 Cg2 CL
1 2 N
Cg2 = f2Cg1
tp1 = tp0 (1 + Cg2/Cg1)
tp2 = tp0 (1 + Cg3/Cg2)
N N
tp = Σ tpj = tp0 Σ (1 + Cgj+1/Cgj)
j=1 j=1Spring 2010, Mar 10Spring 2010, Mar 10 77ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Minimum Delay SizingMinimum Delay Sizing
Equate partial derivatives of tp with respect to Cgj to 0:
1/Cg1 – Cg3/Cg22 = 0, etc.
or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance is geometric
mean of forward and backward gate capacitances.
Also, Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by
the same factor f with respect to the preceding stage:
CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N)
Spring 2010, Mar 10Spring 2010, Mar 10 88ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Minimum Delay SizingMinimum Delay Sizing
Equate partial derivatives of tp with respect to N to 0:
dNtp0(1 + F1/N) ───────── = 0
dN
i.e., F1/N – F1/N(ln F)/N = 0
or ln f = 1 → f = e = 2.7 and N = ln F
Spring 2010, Mar 10Spring 2010, Mar 10 99ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
Sizing for Energy MinimizationSizing for Energy Minimization
Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing.
Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić,Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Section 5.4.
Spring 2010, Mar 10Spring 2010, Mar 10 1010ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)
SummarySummary
Device sizing combined with supply voltage Device sizing combined with supply voltage reduction reduces energy consumption.reduction reduces energy consumption.
For large fan-out energy reduction by a factor of For large fan-out energy reduction by a factor of 10 is possible.10 is possible.
An exception is An exception is F F = 1 case, where the minimum = 1 case, where the minimum size device is also the most effective one.size device is also the most effective one.
Oversizing the devices increases energy Oversizing the devices increases energy consumption.consumption.
Spring 2010, Mar 10Spring 2010, Mar 10 1111ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)