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Institute of Microelectronic Systems 4. SPICE LEVEL 1 MOSFET MODEL 4: MOSFET Model 2 Institute of Microelectronic Systems Four mask layout and cross section of a N channel MOS Transistor.

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Page 1: Spice Level 1

Institute of MicroelectronicSystems

4. SPICE LEVEL 1 MOSFET MODEL

4: MOSFET Model 2

Institute of MicroelectronicSystems

Four mask layout and cross section of a N channel MOS Transistor.

Page 2: Spice Level 1

4: MOSFET Model 3

Institute of MicroelectronicSystems

Layout and cross section of a n-well CMOS technology.

4: MOSFET Model 4

Institute of MicroelectronicSystems

Equations for the different operation regions

0=DSI )( THGS VV ≤

( )[ ]( )DSDSTHGSDSeffDS VLAMBDAVVVVLWKP

I ⋅+−−= 12)(2

)0( THGSDS VVV −≤≤

( )( ) ( )DSTHGSeffDS VLAMBDAVVLWKP

I ⋅+−= 12

2 )0( DSTHGS VVV ≤−≤

Where the threshold voltage is given by:

( )PHIVPHIGAMMAVV BSTTH ⋅−−⋅+= 220

and the channel length:

LDLLeff ⋅−= 2

Page 3: Spice Level 1

4: MOSFET Model 5

Institute of MicroelectronicSystems

Where L is the length of the polysilicon gate and LD is the gate overlap of the source and drain.

The elements in the large signal MOSFET model are shown in the following figure.

4: MOSFET Model 6

Institute of MicroelectronicSystems

MOSFET SPICE PARAMETERS.

Parameter Name SPICE Symbol Analytical Symbol Units

Channel length Leff L M

Poly gate length L Lgate M

Lateral diffusion/Gate-source overlap LD LD M

Transconductanceparameter KP µnCOX A/V2

Threshold voltage/Zero-bias threshold VTO VTO V

Channel-lengthmodulation parameter LAMBDA λn V-1

Bulk threshold/Backgate effect parameter GAMMA γn V1/2

Surface potential/Depletion drop in

inversionPHI -φP V

Page 4: Spice Level 1

4: MOSFET Model 7

Institute of MicroelectronicSystems

Specifying MOSFET Geometry in SPICE.

Mname D G S B MODname L= W= AD= AS= PD= PS= NRD= NRS=

4: MOSFET Model 8

Institute of MicroelectronicSystems

LEVEL 1 MOSFET MODEL PARAMETERS.

.MODEL MODname NMOS/PMOS VTO= KP= GAMMA= PHI= LAMBDA= RD= RS= RSH= CBD= CBS= CJ= MJ= CJSW= MJSW= PB= IS= CGDO= CGSO= CGBO= TOX= LD=

where:

NMOS/PMOS- MOSFET type.

VTO- Threshold voltage (V)

KP- Transconductance parameter (A/V2)

GAMMA- Bulk threshold parameter (V1/2)

PHI- Surface potential (V)

LAMBDA- Channel length modulation parameter (V-1)

RD- Drain resistance (Ω)

Page 5: Spice Level 1

4: MOSFET Model 9

Institute of MicroelectronicSystems

LEVEL 1 MOSFET MODEL PARAMETERS.

RS- Source resistance (Ω)

RSH- Sheet resistance of the drain/source diffusions (Ω/ )

CBD- Zero bias drain-bulk junction capacitance (F)

CBS- Zero bias source-bulk junction capacitance (F)

MJ- Bulk junction grading coefficient (dimensionless)

PB- Built-in potential for the bulk junction (V)

• With CBD, CBS, MJ and PB, SPICE computes the voltage dependences of the drain-bulk and source-bulk capacitances:

( )( )MJ

BD

BDBDPBV

CBDVC

−=

1( )

( )MJBS

BSBSPBV

CBSVC

−=

1

4: MOSFET Model 10

Institute of MicroelectronicSystems

Large-signal, charge-storage capacitors of the MOS device.

Page 6: Spice Level 1

4: MOSFET Model 11

Institute of MicroelectronicSystems

LEVEL 1 MOSFET MODEL PARAMETERS.

CJ- Zero bias planar bulk junction capacitance (F/m2)

CJSW- Zero bias sidewall bulk junction capacitance (F/m)

MJSW- Sidewall junction grading coefficient (dimensionless)

• If CJ, CJSW, and MJSW are given, a more accurated simulation of these capacitances is performed using the following equations:

( )( ) ( )MJSW

BDMJ

BD

BDBDPBV

PDCJSW

PBV

ADCJVC

−⋅

+−

⋅=

11

( )( ) ( )MJSW

BSMJ

BS

BSBSPBV

PSCJSW

PBV

ASCJVC

−⋅

+−

⋅=

11

4: MOSFET Model 12

Institute of MicroelectronicSystems

Bottom and Sidewall components of the bulk junction capacitors.

Bottom=ABCD

Sidewall=ABEF+BCFG+DCGH+ADEH

Page 7: Spice Level 1

4: MOSFET Model 13

Institute of MicroelectronicSystems

LEVEL 1 MOSFET MODEL PARAMETERS.

IS- Saturation current of the junction diode (A)

CGDO- Overlap capacitance of the gate with drain (F)

CGSO- Overlap capacitance of the gate with source (F)

CGBO- Overlap capacitance of the gate with bulk (F)

TOX- Gate oxide thickness (m)

LD- Lateral diffusion (m)

4: MOSFET Model 14

Institute of MicroelectronicSystems

Overlap Capacitances of an MOS transistor. (a) Top view showing the overlap between the source or drain

and the gate. (b) Side view.

Page 8: Spice Level 1

4: MOSFET Model 15

Institute of MicroelectronicSystems

Example of MOSFET model parameters values.

Parameter Name N Channel MOSFET P Channel MOSFET Units

Gate oxide thickness TOX 150 150 Angstroms

Transconductanceparameter KP 50 x 10-6 25 x 10-6 A/V2

Threshold voltage 1.0 -1.0 V

Channel-lengthmodulation parameter

LAMBDA0.1/L (L in µm) 0.1/L (L in µm) V-1

Bulk threshold parameterGAMMA 0.6 0.6 V1/2

Surface potential PHI 0.8 0.8 V

Gate-Drain overlapcapacitance. CGDO 5 x 10-10 5 x 10-10 F/m

Gate-Source overlapcapacitance. CGSO 5 x 10-10 5 x 10-10 F/m

Zero-bias planar bulkdepeltion capacitance CJ 10-4 3 x 10-4 F/m2

Zero-bias sidewall bulkdepletion capacitance

CJSW5 x 10-10 3.5 x 10-10 F/m

Bulk junction potential PB 0.95 0.95 V

Planar bulk junctiongrading coefficient MJ 0.5 0.5

Sidewall bulk junctiongrading coefficient MJSW 0.33 0.33