spectre-compatible process design...

Spectre-Compatible Process Design Kits

May 2007

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Contents1 Introduction

Understanding Spectre-Compatible PDKs ............................................................... 1-1Intended Audience.................................................................................................... 1-2Using Spectre-Compatible PDKs in RFDE ............................................................... 1-2The ADSsim and Spectre Simulators ....................................................................... 1-2

The ADSsim Simulator ....................................................................................... 1-3The Spectre Simulator ........................................................................................ 1-3Multi-Language Simulator Front End.................................................................. 1-3

Supported Design Flows .......................................................................................... 1-4The PDK Development Flow .............................................................................. 1-4

Support Model .......................................................................................................... 1-6Documentation References ...................................................................................... 1-6

2 Administrative TasksSetting Up the Cadence Environment ...................................................................... 2-1

Spectre-Compatibility File Descriptions .............................................................. 2-1Viewing Effective RFDE Library Compatibility for Library Cells................................ 2-4

Setting Up Library Cell Compatibility for RFDE.................................................. 2-7Testing Library Cells for RFDE Spectre Compatibility .............................................. 2-9

Setting Up Model Includes and Include Path ..................................................... 2-13Setting Up Cell Model Parameters ..................................................................... 2-17Setting Up Switch and Stop View lists ................................................................ 2-18

3 Compatible Devices and ModelsInternal Mapping....................................................................................................... 3-1Supported Devices and Models................................................................................ 3-4Sources .................................................................................................................... 3-116

Supported Sources............................................................................................. 3-117Behavioral Source (bsource) .............................................................................. 3-118

Cadence Provided Libraries ..................................................................................... 3-122ahdlLib................................................................................................................ 3-122analogLib............................................................................................................ 3-123basic ................................................................................................................... 3-128rfLib .................................................................................................................... 3-128

Third-Party Libraries ................................................................................................. 3-128Case-Preferential Parameter Matching .............................................................. 3-129

4 Compatible FeaturesExpressions .............................................................................................................. 4-1

Operators ........................................................................................................... 4-1Algebraic and Trigonometric Functions .............................................................. 4-3

iii

Built-in Constants ............................................................................................... 4-4Subcircuits ................................................................................................................ 4-4

Nested Subcircuits.............................................................................................. 4-4Inline Subcircuits ................................................................................................ 4-5Subcircuit Parameters ........................................................................................ 4-5

Process Variation and Mismatch .............................................................................. 4-6The statistics Statement ..................................................................................... 4-6

Structural if-else........................................................................................................ 4-6Sectional Includes .................................................................................................... 4-7Special Character Support........................................................................................ 4-7Verilog-A Support (ahdl_include).............................................................................. 4-8Using Design Variables ............................................................................................ 4-8

5 Managing Unsupported FeaturesIdentifying Unsupported Features ............................................................................ 5-1

Unsupported Parameters on Supported Devices............................................... 5-1Generating Debugging Output ........................................................................... 5-3

Incompatible Features .............................................................................................. 5-4Spectre Analyses................................................................................................ 5-4Case Insensitivity ............................................................................................... 5-5Spectre Control Statements................................................................................ 5-5The paramtest Component................................................................................. 5-9Model Scale Factor (scalem).............................................................................. 5-9Missing Devices and Models .............................................................................. 5-9Spectre High-Level Description Language (HDL) .............................................. 5-9Cadence Compiled-Model Interface (CMI)......................................................... 5-10Spectre Encryption ............................................................................................. 5-10SPICE Format Compatibility............................................................................... 5-10

6 The RFDE NetlisterInstance Netlisting .................................................................................................... 6-2Basic Spectre Formatting ......................................................................................... 6-2Instance Name Mapping........................................................................................... 6-3Node Name Mapping................................................................................................ 6-3Adding Instance Pins for pinMapping ....................................................................... 6-3Subcircuit Netlisting .................................................................................................. 6-4Scoping Rules .......................................................................................................... 6-4Verilog-A Netlisting ................................................................................................... 6-5Include Files ............................................................................................................. 6-5Default Switch and Stop View Lists, Hierarchy Editor .............................................. 6-6Error Messages ........................................................................................................ 6-6Alias Warning Messages .......................................................................................... 6-7Backward Compatibility ............................................................................................ 6-7

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7 Spectre-Compatible Process Design Kit VerificationSetting Up and Running a Simulation....................................................................... 7-1Using the Results Browser ....................................................................................... 7-2Annotating DC Results ............................................................................................. 7-4

Annotating DC Voltages ..................................................................................... 7-4Annotating DC Currents ..................................................................................... 7-5

Displaying DC Operating Points ............................................................................... 7-6Index

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Chapter 1: IntroductionThis documentation provides information on how to be successful using a Spectre Process Design Kit (PDK) in the RF Design Environment (RFDE). This RFDE capability is referred to as Spectre-Compatible PDK. In general, RFDE now supports Spectre simulator syntax allowing simulations in both RFDE and Spectre using the same PDK.

The documentation assumes that you are familiar with the development of process design kits and that you have some familiarity with RFDE and Spectre simulation in the Cadence Design Framework II (DFII) environment. The goal of this documentation is to provide information on:

• What steps to take to accomplish your tasks using the software

• What are the likely design repercussions of the options available at each step

• What are the likely outcomes with the current limitations of the tools

The information in this first chapter describes an overview of a single process design kit for RFDE and Spectre.

Understanding Spectre-Compatible PDKsProcess Design Kits or PDKs are a complete set of the basic building blocks that enable custom IC design. In addition to the numerous baseline PDKs that are available from various vendors, custom PDKs can be developed to suit your own specific needs. PDKs are essential in today’s fast-paced electronic design environment in order to meet aggressive design and development schedules.

Agilent EEsof EDA is now introducing a Spectre-Compatible solution for RF Design Environment (RFDE) users. Agilent Technologies has included a number of new circuit features and devices available in RFDE that are Spectre-Compatible. When developing a new PDK, or a foundry library, you can now set up your PDK or library to be Spectre-Compatible in RFDE and take advantage of both the ADSsim and Spectre simulators. These new Spectre-Compatible features are readily available and easy to use; however, it is important to recognize that there are certain limitations due to differences between the two simulator technologies.

This documentation is intended to help you understand specifically what is supported. The documentation can also help to identify areas of concern and how to deal with these particular situations.

Understanding Spectre-Compatible PDKs 1-1

Introduction

Intended AudienceThe audience intended for this documentation consists of a variety of people involved in process design kit creation, verification, distribution and use. However, the primary audience for this documentation are process design kit developers and CAD administrators. Advanced PDK users who need to understand the details of Spectre compatibility may also benefit from understanding this information.

Using Spectre-Compatible PDKs in RFDEThe complexity of model file translation has been greatly reduced, and in some cases, completely eliminated in this release of RF Design Environment. Model file translation is only required to overcome issues where a feature in Spectre is not supported in RFDE.

Model file verification is also simplified. A single netlist can be reused to verify multiple simulators, and the netlist does not have to be generated by the Cadence environment.

Library setup is also eliminated or greatly reduced. Library setup is only required in cases where a feature in Spectre is unsupported and requires a work-around, or when a specific RFDE feature that does not exist in Spectre is desired.

Programming has also been reduced in the local CAD environment setup. Setups related to switch views, stop views, and model files can now be automated in the Cadence Initialization (.cdsinit) or Library Initialization (libInit.il) file. The setup that works for Spectre now also works for RFDE. Depending on the components used, there are also no requirements to use the RFDE delivered Analog Library (analogLib).

The ADSsim and Spectre SimulatorsCircuit designers do not typically care if Process Design Kits are compatible; they simply expect PDKs to function with either the ADSsim or Spectre simulator. If a PDK developed for Spectre does not function in RF Design Environment, this can present a significant barrier for the RFDE user. The goal of this document is to help CAD Managers and PDK designers become successful in configuring RFDE for use with Spectre-Compatible PDKs.

1-2 Intended Audience

The ADSsim Simulator

Agilent Technologies provides two distinct products that use a common simulation technology called the ADS Analog/RF Simulator (ADSsim). RF Design Environment, using ADSsim, is available in Cadence Design Framework II. A separate, stand-alone product, Advanced Design System, also uses ADSsim.

RF Design Environment enables you to simulate circuits and RF systems designed for specific objectives, such as large-scale RF/mixed signal IC design. RFDE makes available, in the Cadence environment,

• important frequency-domain and mixed-domain simulation technologies

• optimization and statistical design tools

• additional device, system, and behavioral models

• powerful data display post processing

The Spectre Simulator

The Spectre simulator provided by Cadence Design Systems is used to simulate analog and digital circuits at the differential equation level. The simulator uses algorithms that offer increased simulation speed and greatly improved convergence characteristics over SPICE. In addition to the basic capabilities, the Spectre circuit simulator provides additional capabilities over SPICE. SpectreHDL (Spectre High-Level Description Language) and Verilog-A use functional description text files, or modules, to model the behavior of electrical circuits and other systems. The Virtuoso Spectre RF Simulation option includes several analyses that support the efficient calculation of the operating point, transfer function, noise, and distortion of common RF and communication circuits, such as mixers, oscillators, sample holds, and switched-capacitor filters.

Multi-Language Simulator Front End

RF Design Environment includes a multi-language simulator front end as part of the Spectre-Compatibility solution. The front end recognizes the Spectre simulator lang statement with options set to either spectre or ads. For example,

simulator lang=spectre

simulator lang=ads

The ADSsim and Spectre Simulators 1-3

Introduction

This ability to specify a specific language in the netlist is critical to how RFDE’s Spectre parser functions. Once the system selects the spectre or ads simulator language, it can read in the netlist written for spectre or ads syntax, parse the netlist into its various parts, and make the information available for analysis.

Supported Design FlowsAgilent Technologies provides two recognized design flows that can take advantage of the Spectre-Compatible solution:

• RF Design Environment

• RFIC Dynamic Link

An engineer using the RFIC Dynamic Link flow creates a design in the Cadence Virtuoso Schematic Capture. The design is then dynamically linked via inter-process communication (IPC) for simulation in Advanced Design System.

This manual is generally focused on the RF Design Environment design flow. For more information, refer to the Advanced Design System RFIC Dynamic Link and/or the Cadence Library Integration documentation. All Advanced Design System and RF Design Environment documentation can be accessed from the Agilent EEsof EDA Web site at:

http://www.agilent.com/find/eesof-docs/

The PDK Development Flow

The general methodology used for developing process design kits is shown in Figure 1-1. The process begins with the foundry. A manufacturing process is used to generate an integrated circuit (IC) design. The Cadence PDK encapsulates the data for the manufacturing process into a format that will enable a group of designers to create an IC using the specified manufacturing process. This includes libraries that contain layout definitions and verification rule files that can verify that a layout generated using the library can be maintained. Secondary to the layout data is schematic data that can be used to create logical representations of the design. Because of the complexity of modern designs, as well as the cost of manufacturing, it is unrealistic to assume that a designer would create a design directly in layout.

1-4 Supported Design Flows

Figure 1-1. High Level Process Design Kit Development Flow

FoundryCADServices

FoundryCADGroup

Foundry

FoundryManufacturingand Testing

Final ICTest

Packagingand ModuleIntegration

PDKCustomers

PackageModuleTest

Customers receive the finished product

Customers provide specifications, complaints, and/or demands for improved products

Test data is fed back to thedesigner so the design canbe corrected or improved

Test data is fed back to improveFoundry and/or internal models

PDK Development Flow

Foundry Process

PDKDesigners

Supported Design Flows 1-5

Introduction

Support ModelIf you are creating a process design kit that requires some Spectre capability that is not included in this document or includes a feature that is not supported by Agilent Technologies, the Agilent Technologies Spectre-Compatible Process Design Kit team would like to understand your situation. There may be a solution that has not yet been documented, or Agilent Technologies may choose to add it based on a demonstrated need and mutual, widespread benefit.

The standard RF Design Environment user interface does not recognize Spectre netlists. Spectre-Compatibility mode is turned off by default. This means that your designs should be compatible with previous releases. If a problem does occur when using Spectre-Compatibility with a design from a previous release, turn the Spectre-Compatible features off in RFDE to troubleshoot the problem.

For more information, contact your Agilent Technologies sales representative or technical support with a request to submit a suggestion to the Spectre-Compatible Process Design Kit team at the factory.

Documentation ReferencesThis section includes important references to both Agilent Technologies and Cadence Design Systems documentation.

The primary Agilent Technologies documents that are referenced in this documentation include:

• UNIX and Linux Installation

• Using Circuit Simulators

• analogLib Components

• Introduction to Circuit Components

• Nonlinear Devices

• Sources

• Cadence Library Integration

• RF Design Environment Examples

1-6 Support Model

The primary Cadence Design Systems documents that are referenced in this documentation include:

• Cadence Design Framework II Configuration Guide

• Virtuoso Analog Design Environment User Guide

• Virtuoso Spectre Circuit Simulator User Guide

• Virtuoso Spectre Circuit Simulator Reference

• Virtuoso Spectre Circuit Simulator Components and Device Models Manual

• Analog Library Reference Guide

Where ever possible, product version numbers have been included in this document to help identify the correct Cadence documentation.

For more information on Cadence documentation, log into your Cadence SourceLink account from the Cadence Design Systems Web site at:

http://www.cadence.com/

Documentation References 1-7

Introduction

1-8 Documentation References

Chapter 2: Administrative TasksThis chapter describes the administrative tasks that can help a CAD Manager or PDK Designer improve the efficiency of their tasks. The chapter also includes information on the Spectre-Compatibility tools used for setting up and testing library cells.

Setting Up the Cadence EnvironmentThis section describes the different files required for RFDE and the Spectre-Compatibility option to function. With the exception of the RFDE Spectre-Compatibility Configuration file, all other required files are standard Cadence setup files. Once you have configured your Cadence environment to operate with Spectre and RFDE, you can configure your RFDE Spectre-Compatibility Configuration file if not already done. For more information, refer to the “RFDE Spectre-Compatibility Configuration File” on page 2-3.

Spectre-Compatibility File Descriptions

This section includes information on files required for Spectre-Compatibility. In general, the information below includes the file names, locations, purpose, and general contents included in each of the files required for Spectre-Compatibility. References to Cadence documentation are included where appropriate.

For detailed information on RF Design Environment configuration, refer to your UNIX and Linux Installation documentation.

For general information on Cadence configuration, refer to the Cadence Design Framework II Configuration Guide, Product Version 5.0.

Cadence Initialization File

The Cadence initialization file (.cdsinit) is loaded when you start a Cadence session. The .cdsinit file is a SKILL file that enables you to add in commands to do additional customization to the Cadence environment that cannot be easily accomplished by simply changing something in your .cdsenv file. You can load other files in addition to having SKILL commands in your .cdsinit file.

The Cadence initialization file (.cdsinit) is located under:

<Cadence Installation Dir>/tools/dfII/local/

Setting Up the Cadence Environment 2-1

Administrative Tasks

For more information on the .cdsinit file, refer to Creating a .cdsinit File and Modifying the .cdsinit File in the Cadence Design Framework II Configuration Guide, Product Version 5.0.

Cadence Environment Variable File

Cadence environment variable files (.cdsenv) contain information for one or more specific tools that have been configured to work in the Cadence environment. Each tool has its own specific tool file, located under:

<Cadence Installation Dir>/tools/dfII/etc/tools

or located in a directory specified in a setup.loc file if you are using CDS_LOAD_ENV and have set it to CSF.

For more information on the setup.loc file, refer to Chapter 3: Cadence Setup Search File: setup.loc in the Cadence Application Infrastructure User Guide, Product Version 3.4.

The Cadence environment variable file for ADSsim is located under:

<Cadence Installation Dir>/tools/dfII/etc/tools/ADSsim/

For more information on the .cdsenv file, refer to Customizing the Environment in Chapter 2 of the Cadence User Interface SKILL Functions Reference, Product Version 5.0.

Cadence Library Definition File

The Cadence Library Definition file (cds.lib) is located under your Cadence installation directory. This is your library setup file.

For more information on the cds.lib file, refer to Chapter 5: Cadence Library Definition File:cds.lib in the Cadence Application Infrastructure User Guide, Product Version 3.4.

The analogLib library distributed with Cadence tools is partially RFDE compatible; however, the analogLib distributed with RFDE is preferred due to greater component coverage. The RFDE version of analogLib is located under:

$HPEESOF_DIR/cdslibs

The location is specifically keyed off of the Cadence version, which is obtained in the RFDE initialization file, ads.ini. To keep things simple, an include file, rfde.lib, is provided which defines the RFDE analogLib, as well as the adsLib. It is

2-2 Setting Up the Cadence Environment

recommended that both of these, as well as the RFDE version of the Cadence basic library, be added to your cds.lib file, by including the rfde.lib file.

RFDE Spectre-Compatibility Configuration File

In ADS 2006A and beyond, all components that have a spectre definition are considered to be compatible with RFDE by default. RFDE does not have complete compatibility with Spectre, so this may be incorrect. If you find that components that you are using with the spectre definition are not compatible with RFDE, you can selectively turn compatibility on or off by creating a special configuration file in an appropriate location.

The RF Design Environment Spectre-Compatibility Configuration file (rfdeSpectreCompatibility.cfg) enables you to specify whether certain libraries and/or components will work in RFDE Spectre-Compatibility mode. A cell that is marked as incompatible will only netlist in ads mode. A cell that is marked as compatible will netlist in spectre mode assuming that it does not evaluate to having an ads stop view.

For more information on stop views, refer to “Setting Up Switch and Stop View lists” on page 2-18.

If a library is specified, all components in the library will use that setting, unless there is a specific cell setting that will override the library setting.

Format

<libraryName> <cellName> TRUE|FALSE <- Set cell compatibility

<libraryName> TRUE|FALSE <- Set library compatibility

If there are duplicates, only the first setting will be used.

The rfdeSpectreCompatibility.cfg file is located under the following directories:

• <libraryName>/

• $HPEESOF_DIR/custom/config/

• $HOME/hpeesof/config/

These files contain compatibility setting files. The directory locations above are shown from the highest priority to the lowest priority as described in Table 2-1.

Setting Up the Cadence Environment 2-3


Note You can add a setting to the file in your home directory and it will be recognized; however, if it is the same setting as in the library or site directory, it will be overridden.

An additional option is to use the ADSsim.envOpts environment variable. This variable would take the absolute lowest priority below this options listed in Table 2-1. This environment variable can be set in ~/.cdsenv or .cdsenv:

ADSsim.envOpts spectreCompatibility boolean nil

Or, the global file at $CDSHOME/tools/dfII/etc/tools/ADSsim/.cdsenv can be set for all users:

ADSsim.envOpts spectreCompatibility boolean t nil

Setting the value to nil (false) makes the default behavior for cells to be Spectre-Incompatible. An rfdeSpectreCompatibility.cfg file is required to set the library or individual components.

An additional environment variable that can be used for selecting output format is called translateResults. Setting the translateResults environment variable to t (true) will force parameter storage format (PSF) output for all simulations unless you de-activate the Translate Results to PSF option in the Data Display Options form.

ADSsim.envOpts translateResults boolean nil t

You can access the Data Display Options form by choosing Results > Data Display Options in the Analog Design Environment window.

Viewing Effective RFDE Library Compatibility for Library CellsYou can use the View Effective RFDE Compatibility for Library Cells form in RF Design Environment to identify which cells are allowed to be used with RFDE. This

Table 2-1. File Priority for rfdeSpectreCompatibility.cfg

Priority Setting Path Comments

1 LIBRARY <libraryName>/ Overrides SITE & USER settings

2 SITE $HPEESOF_DIR/custom/config/ Overrides USER setting

3 USER $HOME/hpeesof/config/ Lowest priority

2-4 Viewing Effective RFDE Library Compatibility for Library Cells

dialog will show the same settings that will be used by the RFDE netlister to determine if a device can be netlisted, and gives explanations why a component can or cannot be used. A component that is listed in the Cells that do not work with RFDE column can be assumed to cause a simulation error in RFDE, and should not be used in a design that will be simulated in RFDE.

Note This dialog shows settings based on the global environment compatibility setting and rfdeSpectreCompatibility.cfg files. It is up to the administrator to ensure that this dialog is accurate by testing components in the simulator. The software does not perform any specific testing itself.

If you want to force cells to be allowed in a simulation, you have that option as well. Assuming you have write access to a library, you can use the Setup Library Cell Compatibility for RFDE form to change the library defaults to allow Spectre compatibility.

To preview a specific library and review which cells can be simulated in RF Design Environment, launch the Cadence software with RFDE. From the Cadence Command Interpreter Window (CIW),

1. Choose Tools > Agilent RFDE > RFDE Library Compatibility.

The View Effective RFDE Compatibility for Library Cells form appears.

Note The View Effective RFDE Compatibility for Library Cells form can also be accessed from the Analog Design Environment (ADE) window when the ADSsim simulator is selected. To access the form from ADE, choose Tools > RFDE Library Compatibility.

The options for the View Effective RFDE Compatibility for Library Cells form are described in Table 2-2 below.

2. Select a library from the Library drop-down list.

The fields in the form will automatically populate with the library contents. Individual cells are separated into two categories, Cells that work with RFDE and Cells that do not work with RFDE.

3. Click a cell of interest in one of the two categories.

Viewing Effective RFDE Library Compatibility for Library Cells 2-5


Notice that information about the selected cell is displayed in the RFDE Compatibility Setting Status field at the bottom of the form.

Table 2-2. The View Effective RFDE Compatibility for Library Cells Form

Option Description

Library Use the drop-down list to select the appropriate library.

Cells that work with RFDE This field lists the RFDE-Compatible cells within the specified library. Click a library cell to view the effective compatibility displayed in the RFDE Compatibility Setting Status field. While some cells are Spectre-Compatible and will netlist with RFDE, they may still need to be setup for a simulation.


Setting Up Library Cell Compatibility for RFDE

To access the Setup Library Cell Compatibility for RFDE form from the Cadence Command Interpreter Window (CIW),

1. Choose Tools > Agilent RFDE > RFDE Library Compatibility.

The View Effective RFDE Compatibility for Library Cells form appears.

Note The View Effective RFDE Compatibility for Library Cells form can also be accessed from the Analog Design Environment (ADE) window when the ADSsim simulator is selected. To access the form from ADE, choose Tools > RFDE Library Compatibility.

2. Click Edit Settings in the View Effective RFDE Compatibility for Library Cells form.

The Setup Library Cell Compatibility for RFDE form appears.

Cells that do not work with RFDE This field lists the cells within the specified library that are incompatible with RFDE. Click a library cell to view information about why the cell is incompatible. The information will be displayed in the RFDE Compatibility Setting Status field.

RFDE Compatibility Setting Status This field displays information about a selected cell.

Edit Settings Click the Edit Settings button to setup library cells for RFDE-Compatibility. For more information, refer to “Setting Up Library Cell Compatibility for RFDE” on page 2-7.

Table 2-2. The View Effective RFDE Compatibility for Library Cells Form

Option Description

Viewing Effective RFDE Library Compatibility for Library Cells 2-7


If you make a change to your library setup and attempt to close the form without saving your changes, the Save form appears asking if you want to save your changes. Save your settings to ensure your changes are not lost.

If changes are made, and you click the OK or Apply button, an rfdeSpectreCompatibility.cfg file will be written out. If the Show Settings In field is:

• User File - the file will be written to $HOME/hpeesof/config.

• Site File - the file will be written to $HPEESOF_DIR/custom/config, provided you have write access to that file.

• Library File - the file will be written to the root directory of the library, provided you have write access to that file.


Note If you are not the owner of a particular setting, such as a site file, you may not have permissions to change the value of a particular setting. Work with your CAD manager or site administrator to make the appropriate changes.

Refer to Table 2-3 for information on using the Setup Library Cell Compatibility for RFDE form.

Testing Library Cells for RFDE Spectre CompatibilityThis section describes how to test a specific library for Spectre-Compatibility from within the Cadence environment. The tools available in RF Design Environment enable you to test whether a library cell will function in RFDE if it uses Spectre simulation setups. You can set up your own library or cell, or use default settings to

Table 2-3. The Setup Library Cell Compatibility for RFDE Form

Option Description


Show Settings In Select a radio button to User File, Site File, Library File. - User File - the file will be written to $HOME/hpeesof/config.- Site File - the file will be written to $HPEESOF_DIR/custom/config, provided you have write access to that file.- Library File - the file will be written to the root directory of the library, provided you have write access to that file.

Library default is to allow Spectre Simulation Information use with RFDE

Use the drop-down list to set this option to Yes or No. When this option is set to Yes, cells that are specified as Spectre-Compatible will use the Spectre-Compatible features available in RF Design Environment. When this option is set to No, standard RFDE mode will be used. The default value is No.

Cells that work with RFDE This field lists the RFDE-Compatible cells within the specified library.

Cells that do not work with RFDE This field lists the RFDE-Incompatible cells within the specified library.

<-- Use this button to move an entry from the Cells that do not work with RFDE field into the Cells that work with RFDE field.

--> Use this button to move an entry from the Cells that work with RFDE field into the Cells that do not work with RFDE field.

ADD Use the ADD button to add an entry.

DEL Use the DEL button to delete an entry.

+ Cells that are preceded by the + symbol have a cell setting that is inherited from the environment or library default.

Testing Library Cells for RFDE Spectre Compatibility 2-9


control if Spectre-Compatibility should be used or not. You can also save these settings in your configuration file for future use. Settings are saved by default to your configuration file under:

$HOME/hpeesof/config

Note If you are not the owner of a particular setting, such as a site file, you may not have permissions to change the value of a particular setting. Work with your CAD manager or site administrator to make the appropriate changes.

To access the Test Library Cells for RFDE Spectre Compatibility tool, launch Cadence with RFDE. The tool will set up compatibility files by checking if a cell with a Spectre simulation setup will work with RFDE.

From the Cadence Command Interpreter Window (CIW),

1. Choose Tools > Agilent RFDE > Test and Setup RFDE Spectre Compatibility.

The Test Library Cells for RFDE Spectre Compatibility form appears.

2. Use the Library drop-down list to select the appropriate library.

The Cells that have a spectre simulation setup field will be populated by components that have a spectre simInfo.

3. Click a cell that you want to test and then click the right arrow (-->) to move the cell into the Cells to test for RFDE spectre compatibility field.

2-10 Testing Library Cells for RFDE Spectre Compatibility

4. Click Model File Setup.

The Setup Model Includes and Include Path form appears. For more information on model file setup, refer to “Setting Up Model Includes and Include Path” on page 2-13.

5. Click Cell Parameter Setup.

The Setup Cell Model Parameter form appears. For more information on cell parameter setup, refer to “Setting Up Cell Model Parameters” on page 2-17.

6. Click Switch/Stop View Setup.



The Setup switch and stop view lists form appears. For more information on switch view and stop view list setup, refer to “Setting Up Switch and Stop View lists” on page 2-18.

Table 2-4. The Test Library Cells for RFDE Spectre Compatibility Form

Option Description


Test Directory Enter the Test Directory to use in the field provided. This is the directory where test results are stored. The default test directory is under your startup directory.

Test Library Name A default name will be generated in the Test Library Name field. The default name simply appends “_rfdeCompatibilityTests” to the selected library name. You can change this name as desired.

Cells that have a spectre simulation setup The Cells that have a spectre simulation setup field will be populated by components that have a spectre simInfo.You can click the right arrow button (-->) to move a selected cell into the Cells to test for RFDE spectre compatibility list.

Cells to test for RFDE spectre compatibility This field lists all cells that are ready to test for RFDE Spectre-Compatibility. You can click the left arrow button (<--) to move a selected cell back into the Cells that have a spectre simulation setup list.

--> Use this button to move an entry from the Cells that have a spectre simulation setup field into the Cells to test for RFDE spectre compatibility field.

<-- Use this button to move an entry from the Cells to test for RFDE spectre compatibility field into the Cells that have a spectre simulation setup field.

Model File Setup Click the Model File Setup button to launch the Setup Model Includes and Include Path form. Functionality is generally the same as Cadence; however, this form allows you to set a Model include path inside the form. For more information, refer to “Setting Up Model Includes and Include Path” on page 2-13.

Cell Parameter Setup Click the Cell Parameter Setup button to launch the Setup Cell Model Parameter form. This form enables you to set model parameter cells that require a model parameter to be set. If no model parameters are required, a warning message will be displayed in the CIW. For more information, refer to “Setting Up Cell Model Parameters” on page 2-17.

Switch/Stop View Setup Click the Switch/Stop View Setup button to launch the Setup switch and stop view lists form. The switch view and stop view functionality is the same as in the Cadence Environment Options form. For more information, refer to “Setting Up Switch and Stop View lists” on page 2-18.


Setting Up Model Includes and Include Path

In general, the functionality in the Setup Model Includes and Include Path form is the same as provided in the Cadence; however, this form enables you to set a Model include path inside the form. To access the Setup Model Includes and Include Path tool,

1. Access the Test and Setup RFDE Spectre Compatibility form as described in “Testing Library Cells for RFDE Spectre Compatibility” on page 2-9.

2. Click a cell that you want to include.

Note that the Model File Setup button is activated.

3. Click the Model File Setup button.

The Setup Model Includes and Include Path form appears.

Create Test Benches Click the Create Test Benches button to create a test bench from the Cells to test for RFDE Spectre-Compatibility. A test bench enables you to configure a library cell so that you can perform a simple simulation. Test benches are created and stored under:

$HOME/simulation/<libraryName>_<cellName>_test/

Create Test Benches And Run Simulations Click the Create Test Benches And Run Simulations button to create a test bench from the Cells to test for RFDE Spectre-Compatibility and launch a simulation. A pass/fail text file is displayed after the simulation is complete. This file lists all Cells that successfully simulated along with the Cells that failed to simulate.

Simulation results are stored under:$HOME/simulation/<libraryName>_<cellName>_test/

Run Simulations Click this button to run a simulation on the Cells to test for RFDE spectre compatibility. A pass/fail text file is displayed after the simulation is complete. This file lists all Cells that successfully simulated along with the Cells that failed to simulate.

Simulation results are stored under:$HOME/simulation/<libraryName>_<cellName>_test/

Table 2-4. The Test Library Cells for RFDE Spectre Compatibility Form

Option Description



Refer to Table 2-5 for information on using the Setup Model Includes and Include Path form.

Table 2-5. The Setup Model Includes and Include Path Form

Option Description

#Disable|Model Library Setup Lists all of the model files to be included. Enter the model file name and optional section into the Model Library File and Section (opt.) fields described below.

Section Lists all optionally included sections that were entered in the Section (opt.) field below.

Enable Enables the highlighted/selected model files in the Model Library Setup field for a particular run. If any of the highlighted/selected model files in the Model Library Setup field are prefixed with a comment character (#), clicking the Enable button removes the # sign.

Disable De-selects the highlighted model files. Once the Disable button is clicked, the highlighted/selected model files in the Model Library Setup field are disabled and a comment character (#) is added before the model path.

Up Move a highlighted/selected model files in the Model Library Setup field up in the list. This button is disabled if more than one model file is highlighted/selected in the Model Library Setup field. If the first item is highlighted/selected in the Model Library Setup field, the Down button is activated.

Down Move a highlighted/selected model files in the Model Library Setup field down in the list. This button is disabled if more than one model file is highlighted/selected in the Model Library Setup field. If the last item is highlighted/selected in the Model Library Setup field, the Up button is activated.

Model Library File Enter the model library file name in this field.


Note The Setup Model Includes and Include Path form operation in RFDE is very similar to the Cadence Model Library Setup form. For more information, refer to Model Setup for Direct Simulation in Chapter 2 of the Cadence Virtuoso Analog Design Environment User Guide, Product Version 5.1.41.

Loading Model Includes and Include Path from a State

Cadence allows certain portions of a library (e.g. model setup) to be loaded without forcing the entire state to be reloaded. The simulation settings are saved into individual files under the state directory. All or part of a state can be loaded, from any cell or tool in the state directory that is being pointed at, for any cell that is open in the Analog Design Environment. Note that the settings are based on the tool environment value names, so if a tool does not have a particular environment setting, those values would be ignored when a state file is loaded. The Cadence artist state directory structure is shown in Figure 2-1.

Section (opt.) Enter an optional section to include with the model library file in this field.

Add Adds the value of the Model Library File field (and Section (opt.) field) to the end of the list of files in the Model Library Setup field. If a file is selected in the Model Library File field, the Model Library File (and Section (opt.) field) entry is added above the highlighted item.

Delete Removes any highlighted items that are selected in the Model Library Setup field. An item in the Model Library Setup field must be selected in order to remove the file.

Change Replaces the selected entry with the value of the Model Library File field (and Section (opt.) field).

Load from Spectre State Click this button to load a model include and the include path from a previously saved state. For more information, refer to “Loading Model Includes and Include Path from a State” on page 2-15.

Include Path Enter the directory or list of directories for the include path. The paths are checked in sequence.

Table 2-5. The Setup Model Includes and Include Path Form

Option Description



Figure 2-1. Cadence Artist State Directory Structure

To load a model include and the include path from a previously saved state,

1. Access the Setup Model Includes and Include Path form as described in “Testing Library Cells for RFDE Spectre Compatibility” on page 2-9.

2. Click the Load from Spectre State button.

The Load Model Includes and Include Path from a state form appears.

Refer to Table 2-6 for information on using the Load Model Includes and Include Path from a state form.

<artist state directory>

<library 1> <library 2>

<cell 1> <cell 2>

<tool 1> <tool 2>

<state 1> <state 2>

<file 1> <file 2> /tool 1


3. Click OK to enter the values or Cancel to abort the entry.

If you click OK, the values are uploaded into the Setup Model Includes and Include Path form.

Setting Up Cell Model Parameters

The Setup Cell Model Parameters form enables you to set cell model parameters that are required. If no cell model parameters are required, a warning message is displayed in the Cadence Command Interpreter Window (CIW).

To access the Setup Cell Model Parameter form,


2. Click a cell that you want to test and then click the right arrow (-->) to move the cell into the Cells to test for RFDE spectre compatibility field.

3. Click the Cell Parameter Setup button in the Test Library Cells for RFDE Spectre Compatibility form.

The Setup Cell Model Parameter form appears.

Table 2-6. The Load Model Includes and Include Path from a state Form

Option Description

State Save Directory Enter the path for the state save directory. The default path for saved states is ~/.artist_states. The state directory can also be changed by choosing the Session > Options menu item to access the Editing Session Options form in the Analog Design Environment window.

Library Use the drop-down list to select the name of the library whose state was saved.

Cell Use the drop-down list to select the name of the cell whose state was saved. This does not need to match the name of the cell you are currently simulating.

State Name Enter the file name specified when the state was saved.



4. Click the appropriate cell in the Cells that require model parameter setup field and enter a list of models in the Model List field.

5. Click OK to enter the changes and dismiss the form or Cancel to abort the changes.

Setting Up Switch and Stop View lists

The switch view and stop view functionality operates the same as it does in the Cadence environment options.

To access the Setup switch and stop view lists tool,


2. Click a cell that you want to include.

Note that the Switch/Stop View Setup button is activated.

3. Click the Switch/Stop View Setup button.

The Setup switch and stop view lists form appears.


Refer to Table 2-7 for general information on using the Setup switch and stop view lists form.

Table 2-7. The Setup switch and stop view lists Form

Option Description

Switch View List This field includes a list of the views that the software switches into when searching for design variables. The software is searched through the hierarchical views in the order shown in the list. This list must contain the name of the simulator(s).

Stop View List This is a list of views that identify the stopping view to be netlisted. This list does not require a particular sequence.


Chapter 3: Compatible Devices and ModelsThis chapter provides information on the devices and models that are supported for use in Spectre-Compatible PDKs. Device/model detail is described at great length in other Agilent and/or Cadence documentation; therefore, the chapter will provide references to additional information in the corresponding documentation where appropriate.

Note Some Spectre parameters may not be listed for a particular device or model. All Spectre parameters that are not listed should be considered unsupported parameters.

You can also find Spectre instance and model parameter information for each component using the Spectre online help (spectre -h) feature. For more information on this feature, refer to your Cadence documentation set.

Internal MappingWhen RFDE encounters a Spectre netlist, devices and models are mapped to the equivalent ADS Analog/RF simulator (ADSsim) devices and models.

In general, device and model parameters in the ADSsim use initial caps for parameters. Parameters in ADSsim that differ only by the initial cap are mapped directly to the corresponding parameter in Spectre. For example, r in Spectre maps to R in ADSsim. This is helpful to understand when troubleshooting problems in the netlist. Error and warning messages may refer to parameters that are mapped to an equivalent parameter in a different simulator language.

When there is a difference in parameter default values between Spectre and ADSsim, the Spectre default value is used.

The multiplicity factor (m) in Spectre is mapped to _M in ADSsim. This applies to all device and subcircuit instances.

Table 3-1 below displays a list of supported Spectre device and models and their ADSsim equivalents. For information on device, model, and DC operating point parameter mapping, refer to “Supported Devices and Models” on page 3-4.

Internal Mapping 3-1

Compatible Devices and Models

Table 3-1. Supported Devices and Models

Spectre Instance ADSsim Instance Spectre Model ADSsim Model

resistor R resistor R_Model

capacitor C capacitor C_Model

inductor L inductor L_Model

mutual_inductor Mutual

diode Diode diode Diode(Diode_Model)

juncap Juncap(JUNCAP)

juncap Juncap(Juncap_Model)

bjt bjt(BJT_NPN, BJT_PNP )

bjt BJT(BJT_Model)

bht bht(HICUM_NPN, HICUM_PNP)

bht HICUM(HICUM_Model)

bjt503 bjt503(BJT_NPN, BJT_PNP)

bjt503 MextramBJT(MEXTRAM_Model)

bjt504 bjt504(M504_BJT_NPN, M504_BJT_PNP)

bjt504 MextramBJT504(MEXTRAM_504_Model)

bjtst bjtst(BJT_NPN, BJT_PNP)

bjtst STBJT(STBJT_Model)

vbic vbic(VBIC_NPN, VBIC_PNP)

vbic VBIC(VBIC_Model)

bsim3v3 bsim3v3(MOSFET_NMOS, MOSFET_PMOS)

bsim3v3 MOSFET(BSIM3_Model)

bsim4 bsim4(BSIM4_NMOS, BSIM4_PMOS)

bsim4 BSIM4(BSIM4_Model)

mos1 mos1(MOSFET_NMOS, MOSFET_PMOS)

mos1 MOSFET(LEVEL1_Model)





mos902 mos902(MM9_NMOS, MM9_PMOS)

mos902 MOS9(MOS_Model9_Single)

† Supported types are dc, sine, pwl, exp, and pulse.

3-2 Internal Mapping

mos903 mos903(MM9_NMOS, MM9_PMOS)

mos903 MOS9(MOS_Model9_Single)

jfet jfet(JFET_NFET, JFET_PFET)

jfet JFET(JFET_Model)

cccs SDD

pcccs SDD

ccvs SDD

pccvs SDD

vccs SDD

pvccs SDD

vcvs SDD

pvcvs SDD

vsource † V_Source

isource † I_Source

port(type=dc) rfdePdc

port(type=sine) rfdePsin

port(type=exp) rfdePexp

port(type=pwl) rfdePpwl

port(type=pulse) rfdePpulse

bsource Bsource

delay Hybrid

iprobe Short

transformer Hybrid

nport SnP

Table 3-1. Supported Devices and Models

Spectre Instance ADSsim Instance Spectre Model ADSsim Model

† Supported types are dc, sine, pwl, exp, and pulse.

Internal Mapping 3-3


Supported Devices and ModelsThis section provides a list of supported devices and models

Passive Devices and Models

“Resistor” on page 3-5

“Capacitor” on page 3-7

“Inductor” on page 3-9

“Mutual Inductor” on page 3-11

Diode and Bipolar Devices and Models

“Diode” on page 3-12

“JUNCAP (Junction Capacitor)” on page 3-16

“BJT (Bipolar Junction Transistors)” on page 3-19

“BHT (HICUM)” on page 3-25

“BJT503” on page 3-30

“BJT504” on page 3-34

“BJTST” on page 3-41

“VBIC” on page 3-45

FET Devices and Models

“BSIM3v3” on page 3-50

“BSIM4” on page 3-67

“MOS1” on page 3-89





“JFET” on page 3-114

Sources

“Supported Sources” on page 3-116

“Behavioral Source (bsource)” on page 3-117

3-4 Supported Devices and Models

Resistor

Table 3-2 shows the supported resistor instance parameter mapping. The Spectre resistor instance is mapped to the ADSsim R instance.

For more information on the resistor in Spectre, refer to the Two Terminal Resistor (resistor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the resistor device in RFDE, refer to R (Resistor) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-3 shows the supported resistor model parameter mapping. The Spectre resistor model is mapped to the ADSsim R_model.

For more information on the resistor model in RFDE, refer to R_Model (Resistor Model) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-2. Supported Resistor Instance Parameters

Spectre ADSsim Comments

r R

tc1 TC1

tc1r TC1 alias for tc1

tc2 TC2

tc2r TC2 alias for tc2

isnoisy Noise

trise Trise

w Width

l Length

Table 3-3. Supported Resistor Model Parameters

Spectre ADSsim

r R

rsh Rsh

l Length

w Width

etch Dw

etchl Dl

tnom Tnom

Supported Devices and Models 3-5


Table 3-4 shows the supported resistor model DC operating point parameter mapping. The Spectre resistor model is mapped to the ADSsim R_model.

tc1 TC1

tc2 TC2

scaler Scale

trise Trise

coeffs Coeffs

kf Kf

af Af

wdexp Wdexp

ldexp Ldexp

weexp Weexp

leexp Leexp

fexp Fexp

Table 3-4. Supported Resistor Model DC Operating Point Parameters

Spectre ADSsim

i i

pwr power

res r

v v

Table 3-3. Supported Resistor Model Parameters

Spectre ADSsim


Capacitor

Table 3-5 shows the supported capacitor instance parameter mapping. The Spectre capacitor instance is mapped to the ADSsim C instance.

For more information on the capacitor in Spectre, refer to the Two Terminal Capacitor (capacitor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the capacitor device in RFDE, refer to C (Capacitor) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-6 shows the supported capacitor model parameter mapping. The Spectre capacitor model is mapped to the ADSsim C_model.

For more information on the capacitor model in RFDE, refer to C_Model (Capacitor Model) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-5. Supported Capacitor Instance Parameters

Spectre ADS

c C

tc1 TC1

tc2 TC2

ic InitCond

w Width

l Length

trise Trise

Table 3-6. Supported Capacitor Model Parameters

Spectre ADS

c C

cj Cj

cjsw Cjsw

l Length

w Width

etch Narrow

tnom Tnom

tc1 TC1

tc2 TC2



Table 3-7 shows the supported capacitor model DC operating point parameter mapping. The Spectre capacitor model is mapped to the ADSsim C_model.

scalec Scale

trise Trise

coeffs Coeffs

Table 3-7. Supported Capacitor Model DC Operating Point Parameters

Spectre ADSsim

cap c

Table 3-6. Supported Capacitor Model Parameters

Spectre ADS


Inductor

Table 3-8 shows the supported inductor instance parameter mapping. The Spectre inductor instance is mapped to the ADSsim L instance.

For more information on the inductor in Spectre, refer to the Two Terminal Inductor (inductor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the inductor device in RFDE, refer to L (Inductor) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-9 shows the supported inductor model parameter mapping. The Spectre inductor model is mapped to the ADSsim L_model.

For more information on the inductor model in RFDE, refer to L_Model (Inductor Model) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-8. Supported Inductor Instance Parameters

Spectre ADSsim

l L

r R

ic InitCond

isnoisy Noise

trise Trise

tc1 TC1

tc2 TC2

Table 3-9. Supported Inductor Model Parameters

Spectre ADSsim

l L

r R

tnom Tnom

tc1 TC1

tc2 TC2

scalei Scale

trise Trise

coeffs Coeffs



Table 3-10 shows the supported inductor model DC operating point parameter mapping. The Spectre inductor model is mapped to the ADSsim L_model.

kf Kf

af Af

Table 3-10. Supported Inductor Model DC Operating Point Parameters

Spectre ADSsim

i i

ind l

Table 3-9. Supported Inductor Model Parameters

Spectre ADSsim


Mutual Inductor

Table 3-11 shows the supported mutual_inductor instance parameter mapping. The Spectre mutual_inductor instance is mapped to the ADSsim Mutual instance.

For more information on the mutual inductor in Spectre, refer to the Mutual Inductor (mutual inductor) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the mutual inductor in RFDE, refer to Mutual (Mutual Inductor) in Chapter 2 of the Introduction to Circuit Components documentation.

Table 3-11. Supported Mutual Inductor Instance Parameters

Spectre ADSsim

coupling K

k K

mind M

ind1 Inductor1

ind2 Inductor2



Diode

Table 3-12 shows the supported diode instance parameter mapping. The Spectre diode instance is mapped to the ADSsim Diode instance.

For more information on the diode in Spectre, refer to the Diode Model (diode) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the diode device in RFDE, refer to Diode (PN-Junction Diode) in Chapter 1 of the Nonlinear Devices documentation.

Table 3-13 shows the supported diode model parameter mapping. The Spectre diode model is mapped to the ADSsim Diode model.

For more information on the diode model in RFDE, refer to Diode_Model (PN-Junction Diode Model) in Chapter 1 of the Nonlinear Devices documentation.

Table 3-12. Supported Diode Instance Parameters


area Area

lv1 Area alias for area

perim Periph

pj Periph

l Length

w Width

scale Scale

region Region off -> 0on -> 1breakdown -> ignored

trise Trise

Table 3-13. Supported Diode Model Parameters


level Level level=1,3 -> Level=11 Junctionlevel=2 -> Not Supported

etch Etch

etch1 Etch1

shrink Shrink

l Length


w Width

js Js

is Is

jsw Jsw

isw Isw

n N

ns Ns

ik Ikf

ikp Ikp

ikr Ikr

area Area

perim Periph

allow_scaling AllowScaling

tt Tt

cd Cd

lx5 Cd

cjo Cjo

cj0 Cjo "cj0" (zero) is an undocumented alias for "cjo" (letter 0)

vj Vj

m M

cjsw Cjsw

cjp Cjsw alias for cjsw

vjsw Vjsw

php Vjsw alias for vjsw

mjsw Msw

fc Fc

fcs Fcsw

bv Bv

vb Bv alias for bv

ibv Ibv

nz Nbv

bvj Bvj

rs Rs

rsw Rsw





gleak Gleak

gleaksw Gleaksw

minr Minr

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

xti Xti

tbv1 Tbv1

tcv Tbv1 alias for tbv1

tbv2 Tbv2

tnom Tnom

trise Trise

trs Trs

trs2 Trs2

tgs Tgs

tgs2 Tgs2

cta Tcjo

ctp Tcjsw

pta Tvj

ptp Tvjsw

jmelt Imelt

imelt Imelt

expli Imelt

imax Imax

jmax Imax

kf Kf

af Af

ttt1 Ttt1

ttt2 Ttt2

tm1 Tm1

tm2 Tm2

cj Cjo

mj M




Table 3-14 shows the supported diode model DC operating point parameter mapping. The Spectre diode model is mapped to the ADSsim Diode model.

pt Pt

pj Periph

pbsw Vjsw

Table 3-14. Supported Diode Model DC Operating Point Parameters

Spectre ADSsim

cap cd

capp cdsw

i id

lx1 id

pwr power

res rd

resp rdsw

v vd





JUNCAP (Junction Capacitor)

Table 3-15 shows the supported juncap instance parameter mapping. The Spectre juncap instance is mapped to the ADSsim Juncap instance.

For more information on the junction capacitor in Spectre, refer to the Junction Capacitor (juncap) in Chapter 2 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the junction capacitor device in RFDE, refer to JUNCAP (Philips JUNCAP Device) in Chapter 1 of the Nonlinear Devices documentation.

Table 3-16 shows the supported juncap model parameter mapping. The Spectre juncap model is mapped to the ADSsim Juncap model.

For more information on the junction capacitor model in RFDE, refer to Juncap_Model (Philips JUNCAP Model) in Chapter 1 of the Nonlinear Devices documentation.

Table 3-15. Supported Junction Capacitor Instance Parameters


ab Ab

ls Ls

lg Lg

region Region rev -> 0 fwd -> 1 breakdown -> ignored

Table 3-16. Supported Junction Capacitor Model Parameters


type Reversed type=n -> Reversed=1type=p -> Reversed=0

jsgbr Jsgbr

jsdbr Jsdbr

jsgsr Jsgsr

jsdsr Jsdsr

jsggr Jsggr

jsdgr Jsdgr

imax Imax

dta Trise alias of trise

trise Trise


Table 3-17 shows the supported juncap model DC operating point parameter mapping. The Spectre juncap model is mapped to the ADSsim Juncap model.

tr Tr

tref Tr alias of tr

tnom Tr

cjbr Cjbr

cjsr Cjsr

cjgr Cjgr

nb Nb

ns Ns

ng Ng

vr Vr

vdbr Vdbr

vdsr Vdsr

vdgr Vdgr

pb Pb

ps Ps

pg Pg

cjb Cjb

cjs Cjs

cjg Cjg

isdb Isdb

isds Isds

isdg Isdg

isgb Isgb

isgs Isgs

isgg Isgg

vdb Vdb

vds Vds

vdg Vdg

Table 3-16. Supported Junction Capacitor Model Parameters




Table 3-17. Supported Junction Capacitor Model DC Operating Point Parameters

Spectre ADSsim

c cd

i id

pwr power

v vd


BJT (Bipolar Junction Transistors)

Table 3-18 shows the supported bjt instance parameter mapping. The Spectre bjt instance is mapped to the ADSsim bjt instance.

For more information on the bipolar junction transistor in Spectre, refer to the BJT Model (bjt) in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the bjt device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-19 shows the supported bjt model parameter mapping. The Spectre bjt model is mapped to the ADSsim BJT model.

For more information on the bjt model in RFDE, refer to BJT_Model (Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-18. Supported BJT Instance Parameters


area Area

trise Trise

region Region off -> 0fwd -> 1rev -> 2sat -> 3others -> (ignored)

Table 3-19. Supported BJT Model Parameters


type NPN & PNP type=npn -> NPN=1 PNP=0type=pnp -> NPN=0 PNP=1

struct Lateral struct=lateral -> Lateral=1struct=vertical -> Lateral=0

is Is

ise Ise

isc Isc

iss Iss

c2 C2

c4 C4

cbo Cbo



gbo Gbo

vbo Vbo

tcbo Tcbo

tgbo Tgbo

nf Nf

nr Nr

ne Ne

nc Nc

ns Ns

bf Bf

br Br

ikf Ikf

jbf Ikf alias for ikf

ikr Ikr

jbr Ikr alias for ikr

vaf Vaf

va Vaf

var Var

vb Var

ke Ke

kc Kc

rb Rb

rbm Rbm

irb Irb

jrb Irb alias for irb

rbmod RbModel

rc Rc

rcv Rcv

rcm Rcm

dope Dope

cex Cex

cco Cco

re Re

minr Minr

cje Cje




vje Vje

mje Mje

cjc Cjc

vjc Vjc

mjc Mjc

xcjc Xcjc

xcjc2 Xcjc2

cjs Cjs

vjs Vjs

mjs Mjs

fc Fc

tf Tf

td Td

xtf Xtf

vtf Vtf

itf Itf

jtf Itf alias for itf

tr Tr

ptf Ptf

tnom Tnom

trise Trise

eg Eg

xtb Xtb

xti Xti

pt Xti alias for xti

trb1 Trb1

trb2 Trb2

trm1 Trm1

trm2 Trm2

trc1 Trc1

trc2 Trc2

tre1 Tre1

tre2 Tre2

tlev Tlev

tlevc Tlevc





gap1 EgAlpha

gap2 EgBeta

tikf1 Tikf1

tikf2 Tikf2

tikr1 Tikr1

tikr2 Tikr2

tirb1 Tirb1

tirb2 Tirb2

tis1 Tis1

tis2 Tis2

tise1 Tise1

tise2 Tise2

tisc1 Tisc1

tisc2 Tisc2

tiss1 Tiss1

tiss2 Tiss2

tbf1 Tbf1

tbf2 Tbf2

tbr1 Tbr1

tbr2 Tbr2

tvaf1 Tvaf1

tvaf2 Tvaf2

tvar1 Tvar1

tvar2 Tvar2

titf1 Titf1

titf2 Titf2

ttf1 Ttf1

ttf2 Ttf2

ttr1 Ttr1

ttr2 Ttr2

tnf1 Tnf1

tnf2 Tnf2

tnr1 Tnr1

tnr2 Tnr2

tne1 Tne1




tne2 Tne2

tnc1 Tnc1

tnc2 Tnc2

tns1 Tns1

tns2 Tns2

tmje1 Tmje1

tmje2 Tmje2

tmjc1 Tmjc1

tmjc2 Tmjc2

tmjs1 Tmjs1

tmjs2 Tmjs2

cte Cte

ctc Ctc

cts Cts

tvje Tvje

tvjc Tvjc

tvjs Tvjs

tvtf1 Tvtf1

tvtf2 Tvtf2

txtf1 Txtf1

txtf2 Txtf2

imelt Imelt

bvbe Bvbe

bvbc Bvbc

bvsub Bvwub

vbcfwd Vbcfwd

vsubfwd Vsubfwd

imax Imax

kf Kf

af Af

kb Kb

bnoisefc Fb

rbnoi Rbnoi

cse Tccs Undocumented Spectre parameter

nkf Nk Undocumented Spectre parameter





Table 3-20 shows the supported bjt model DC operating point parameter mapping. The Spectre bjt model is mapped to the ADSsim BJT model.

Table 3-20. Supported BJT Model DC Operating Point Parameters

Spectre ADSsim

betaac betaac

betadc betadc

cmu cmu

cmux cbx

cpi cpi

csub ccs

ft ft

gm gm

ib ib

ic ic

isub is

lv5 ft

lx0 vbe

lx1 vbc

lx19 cpi

lx2 ic

lx20 cmu

lx21 ccs

lx22 cbx

lx3 ib

lx6 gm

pwr power

ro ro

rpi rpi

vbc vbc

vbe vbe

vce vce


BHT (HICUM)

Table 3-21 shows the supported bht instance parameter mapping. The Spectre bht instance is mapped to the ADSsim bht instance.

For more information on the HICUM bipolar transistor in Spectre, refer to the HICUM Model (bht) in Chapter 6 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the bht device in RFDE, refer to HICUM_NPN, HICUM_PNP (HICUM Bipolar Transistors, NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-22 shows the supported bht model parameter mapping. The Spectre bht model is mapped to the ADSsim HICUM model.

For more information on the HICUM model in RFDE, refer to HICUM_Model (Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-21. Supported BHT Instance Parameters

Spectre ADSsim

trise Trise

self_heating Selfheating

Table 3-22. Supported BHT Model Parameters



latb Latb

latl Latl

c10 C10

qp0 Qp0

ich Ich

hjci Hjci

hjei Hjei

mcf Mcf

tsf Tsf

hfc Hfc

hfe Hfe

alit Alit



cjei0 Cjei0

vdei Vdei

zei Zei

aljei Aljei

cjci0 Cjci0

vdci Vdci

zci Zci

vptci Vptci

t0 T0

dt0h Dt0h

tbvl Tbvl

tef0 Tef0

gtfe Gtfe

thcs Thcs

alhc Alhc

fthc Fthc

vces Vces

rci0 Rci0

vlim Vlim

vpt Vpt

tr Tr

alqf Alqf

ibeis Ibeis

mbei Mbei

ireis Ireis

mrei Mrei

ibcis Ibcis

mbci Mbci

favl Favl

qavl Qavl

rbi0 Rbi0

fdqr0 Fdqr0

fgeo Fgeo

fqi Fqi

fcrbi Fcrbi




cjep0 Cjep0

vdep Vdep

zep Zep

aljep Aljep

ibeps Ibeps

mbep Mbep

ireps Ireps

mrep Mrep

cjcx0 Cjcx0

vdcx Vdcx

zcx Zcx

vptcx Vptcx

ccox Ccox

fbc Fbc

ibcxs Ibcxs

mbcx Mbcx

ceox Ceox

rbx Rbx

re Re

rcx Rcx

cjs0 Cjs0

vds Vds

zs Zs

vpts Vpts

rsu Rsu

csu Csu

iscs Iscs

msc Msc

itss Itss

msf Msf

msr Msr

ibets Ibets

abet Abet

kf Kf

af Af





Table 3-23 shows the supported bht model DC operating point parameter mapping. The Spectre bht model is mapped to the ADSsim HICUM model.

krbi Krbi

vgb Vgb

alb Alb

alfav Alfav

alqav Alqav

zetaci Zetaci

alvs Alvs

alces Alces

zetarbi Zetarbi

zetarbx Zetarbx

zetarcx Zetarcx

zetare Zetare

alt0 Alt0

kt0 Kt0

rth Rth

cth Cth

trise Trise

tnom Tnom

Table 3-23. Supported BHT Model DC Operating Point Parameters

Spectre ADSsim

cdci cdci

cdei cdei

cjci cjci

cjei cjei

cjep cjep

cjs cjs

gm gm

ib ib

ic ic

is is

pwr power




rbi rbi

sfb sfb

sfc sfc

srb srb

src src

temp temp

vbci vbc

vcei vce

Table 3-23. Supported BHT Model DC Operating Point Parameters

Spectre ADSsim



BJT503

Table 3-24 shows the supported bjt503 instance parameter mapping. The Spectre bjt503 instance is mapped to the ADSsim bjt503 instance.

For more information on the vertical NPN/PNP transistor (bjt503) in Spectre, refer to the Vertical NPN/PNP Transistor (bjt503) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the bjt503 device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-25 shows the supported bjt503 model parameter mapping. The Spectre bjt503 model is mapped to the ADSsim MextramBJT model.

For more information on the bjt503 model in RFDE, refer to MEXTRAM_Model (MEXTRAM Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-24. Supported BJT503 Instance Parameters


area Area

mult Area Alias for area


Table 3-25. Supported BJT503 Model Parameters



exmod Exmod

exphi Exphi

exavl Exavl

is Is

bf Bf

xibi Xibi

ibf Ibf


vlf Vlf

ik Ik

bri Bri

ibr Ibr

vlr Vlr

xext Xext

qbo Qb0

eta Eta

avl Avl

efi Efi

ihc Ihc

rcc Rcc

rcv Rcv

scrcv Scrcv

sfh Sfh

rbc Rbc

rbv Rbv

re Re

taune Taune

mtau Mtau

cje Cje

vde Vde

pe Pe

xcje Xcje

cjc Cjc

vdc Vdc

pc Pc

xp Xp

mc Mc

xcjc Xcjc

tref Tref

tnom Tref alias for tref

tr Tref alias for tref

dta Dta

trise Dta





Table 3-26 shows the supported bjt503 model DC operating point parameter mapping. The Spectre bjt503 model is mapped to the ADSsim MextramBJT model.

vge Vge

vgb Vgb

vgc Vgc

vgj Vgj

vi Vi

na Na

er Er

ab Ab

aepi Aepi

aex Aex

ac Ac

kf Kf

kfn Kfn

af Af

iss Iss

iks Iks

cjs Cjs

vds Vds

ps Ps

vgs Vgs

as As

Table 3-26. Supported BJT503 Model DC Operating Point Parameters

Spectre ADSsim

cb1b2 cb1b2

ib ib

ic ic

ie ie

is is

pwr power

vbc vbc




vbe vbe

vce vce


Spectre ADSsim



BJT504

Table 3-27 shows the supported bjt504 instance parameter mapping. The Spectre bjt504 instance is mapped to the ADSsim bjt504 instance.

For more information on the vertical NPN/PNP transistor (bjt504) in Spectre, refer to the Vertical NPN/PNP Transistor (bjt504) in Chapter 7 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the bjt504 device in RFDE, refer to M504_BJT_NPN, M504_BJT_PNP (Mextram 504 Nonlinear Bipolar Transistors) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-28 shows the supported bjt504 model parameter mapping. The Spectre bjt504 model is mapped to the ADSsim MextramBJT504 model.

For more information on the bjt504 model in RFDE, refer to MEXTRAM_504_Model (MEXTRAM 504 Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-27. Supported BJT504 Instance Parameters


mult Mult

area Area alias of mult




tref Tref

tnom Tnom

tr Tref alias of tref in Spectre

level Level

dta Dta

exmod Exmod

exphi Exphi

exavl Exavl

is Is

ik Ik

ver Ver


vef Vef

bf Bf

ibf Ibf

mlf Mlf

xibi Xibi

bri Bri

ibr Ibr

vlr Vlr

xext Xext

wavl Wavl

vavl Vavl

sfh Sfh

re Re

rbc Rbc

rbv Rbv

rcc Rcc

rcv Rcv

scrcv Scrcv

ihc Ihc

axi Axi

cje Cje

vde Vde

pe Pe

xcje Xcje

cbeo Cbeo

cjc Cjc

vdc Vdc

pc Pc

xp Xp

mc Mc

xcjc Xcjc

cbco Cbco

mtau Mtau

taue Taue

taub Taub





Table 3-29 shows the supported bjt504 model DC operating point parameter mapping. The Spectre bjt504 model is mapped to the ADSsim MextramBJT504 model.

tepi Tepi

taur Taur

deg Deg

xrec Xrec

aqbo Aqbo

ae Ae

ab Ab

aepi Aepi

aex Aex

ac Ac

dvgbf dVgbf

dvgbr dVgbr

vgb Vgb

vgc Vgc

vgj Vgj

dvgte dVgte

af Af

kf Kf

kfn Kfn

iss Iss

iks Iks

cjs Cjs

vds Vds

ps Ps

vgs Vgs

as As


Spectre ADSsim

Cb1b2 cb1b2

cb1b2 cb1b2




Cb1b2x cb1b2x

cb1b2x cb1b2x

Cb1b2y cb1b2y

cb1b2y cb1b2y

Cb1b2z cb1b2z

cb1b2z cb1b2z

Cbcex cbcex

cbcex cbcex

Cbcx cbcx

cbcx cbcx

Cbcy cbcy

cbcy cbcy

Cbcz cbcz

cbcz cbcz

Cbex cbex

cbex cbex

Cbey cbey

cbey cbey

Cbez cbez

cbez cbez

Cts cts

cts cts

gmuex gmuex

gmux gmux

gmuy gmuy

gmuz gmuz

gpix gpix

gpiy gpiy

gpiz gpiz

grbvx grbvx

grbvy grbvy

grbvz grbvz

grcvy grcvy

grcvz grcvz

gS gs


Spectre ADSsim



gs gs

gSf gsf

gsf gsf

gx gx

gy gy

gz gz

Iavl iavl

iavl iavl

Ib ib

ib ib

Ib1 ib1

ib1 ib1

Ib1b2 ib1b2

ib1b2 ib1b2

Ib2 ib2

ib2 ib2

Ib3 ib3

ib3 ib3

Ic ic

ic ic

Ic1c2 ic1c2

ic1c2 ic1c2

Iex iex

iex iex

In in

in in

IRBC irbc

irbc irbc

IRCC ircc

ircc ircc

IRE ire

ire ire

Isf isf

isf isf

Isub isub


Spectre ADSsim


isub isub

Qb1b2 qb1b2

qb1b2 qb1b2

Qbc qbc

qbc qbc

Qbe qbe

qbe qbe

Qe qe

qe qe

Qepi qepi

qepi qepi

Qex qex

qex qex

Qtc qtc

qtc qtc

Qte qte

qte qte

Qtex qtex

qtex qtex

Qts qts

qts qts

Rbv rbv

rbv rbv

SCbe scbe

scbe scbe

Sgpi sgpi

sgpi sgpi

SIb1 sib1

sib1 sib1

SQte sqte

sqte sqte

XCbcex xcbcex

xcbcex xcbcex

Xgmuex xgmuex

xgmuex xgmuex


Spectre ADSsim



XgS xgs

xgs xgs

XIex xiex

xiex xiex

XIsub xisub

xisub xisub

XQex xqex

xqex xqex

XQtex xqtex

xqtex xqtex


Spectre ADSsim


BJTST

Table 3-30 shows the supported bjtst instance parameter mapping. The Spectre bjtst instance is mapped to the ADSsim bjtst instance.

For more information on the bjtst in Spectre, refer to the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the bjtst device in RFDE, refer to BJT_NPN, BJT_PNP (Bipolar Junction Transistors NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-31 shows the supported bjtst model parameter mapping. The Spectre bjtst model is mapped to the ADSsim STBJT model.

For more information on the bjtst model in RFDE, refer to STBJT_Model (ST Bipolar Transistor Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-30. Supported BJTST Instance Parameters

Spectre ADSsim

area Area

Table 3-31. Supported BJTST Model Parameters



is Is

isn Isn

bf Bf

nf Nf

br Br

nr Nr

isf Isf

nbf Nbf

isr Isr

nbr Nbr

ise Ise

ne Ne

isc Isc

nc Nc



vaf Vaf

var Var

ikf Ikf

ikr Ikr

enp Enp

rp Rp

rw Rw

vjj Vjj

vrp Vrp

bvc Bvc

mf Mf

fa Fa

avc Avc

bve Bve

mr Mr

fb Fb

ave Ave

rb Rb

irb Irb

rbm Rbm

re Re

rc Rc

rcs Rcs

cje Cje

vje Vje

mje Mje

fc Fc

cjc Cjc

vjc Vjc

mjc Mjc

xjbc Xjbc

cjs Cjs

vjs Vjs

mjs Mjs

xjbs Xjbs




Table 3-32 shows the supported bjtst model DC operating point parameter mapping. The Spectre bjtst model is mapped to the ADSsim STBJT model.

vert Vert

subsn Subsn

tf Tf

xtf Xtf

vtf Vtf

itf Itf

ptf Ptf

tfcc Tfcc

tr Tr

kf Kf

af Af

eg Eg

xti Xti

xtb Xtb

trb1 Trb1

trb2 Trb2

trbm1 Trbm1

trbm2 Trbm2

tre1 Tre1

tre2 Tre2

trc1 Trc1

trc2 Trc2

trcs1 Trcs1

trcs2 Trcs2

tmeas Tmeas

Table 3-32. Supported BJTST Model DC Operating Point Parameters

Spectre ADSsim

betaac betaac

betadc betadc

cbs cbs

cbx cbx





ccs ccs

cmu cmu

cpi cpi

cxs cxs

gm gm

ib ib

ic ic

rcv rcv

rmu rmu

ro ro

rpi rpi

rx rx

vbc vbc

vbe vbe

vce vce

Table 3-32. Supported BJTST Model DC Operating Point Parameters

Spectre ADSsim


VBIC

Table 3-33 shows the supported vbic instance parameter mapping. The Spectre vbic instance is mapped to the ADSsim vbic instance.

For more information on the VBIC model, refer to VBIC Model (vbic) in Chapter 8 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the VBIC device in RFDE, refer to VBIC_NPN, VBIC_PNP (VBIC Nonlinear Bipolar Transistors, NPN, PNP) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-34 shows the supported vbic model parameter mapping. The Spectre vbic model is mapped to the ADSsim VBIC model.

For more information on the vbic model in RFDE, refer to VBIC_Model (VBIC Model) in Chapter 2 of the Nonlinear Devices documentation.

Table 3-33. Supported VBIC Instance Parameters


area Scale


trise Trise

dtmp Trise alias for trise

dtemp Trise alias for trise

Table 3-34. Supported VBIC Model Parameters



is Is

ibei Ibei

iben Iben

ibci Ibci

ibcn Ibcn

isp Isp



ibeip Ibeip

ibenp Ibenp

ibcip Ibcip

ibcnp Ibcnp

vo Vo

gamm Gamm

hrcf Hrcf

wbe Wbe

wsp Wsp

nf Nf

nr Nr

nei Nei

nen Nen

nci Nci

ncn Ncn

nfp Nfp

ncip Ncip

ncnp Ncnp

ikf Ikf

ikr Ikr

ikp Ikp

vef Vef

ver Ver

avc1 Avc1

avc2 Avc2

rbi Rbi

rbx Rbx

re Re

rs Rs

rbp Rbp

rcx Rcx

rci Rci

cje Cje

pe Pe

me Me




aje Aje

fc Fc

cbeo Cbeo

cjc Cjc

cjep Cjep

pc Pc

mc Mc

ajc Ajc

cbco Cbco

qco Qco

cjcp Cjcp

ps Ps

ms Ms

ajs Ajs

tf Tf

tr Tr

td Td

qtf Qtf

xtf Xtf

vtf Vtf

itf Itf

selft Selft

tnom Tnom

trise Trise

dtmp Trise alias for trise

dtemp Trise alias for trise

rth Rth

cth Cth

xis Xis

xii Xii

xin Xin

tnf Tnf

tavc Tavc

ea Ea

eaie Eaie





Table 3-35 shows the supported vbic model DC operating point parameter mapping. The Spectre vbic model is mapped to the ADSsim VBIC model.

eaic Eaic

eais Eais

eane Eane

eanc Eanc

eans Eans

xre Xre

xrb Xrb

xrbi Xrb alias for xrb

xrc Xrc

xrci Xrc alias for xrc

xrs Xrs

xvo Xvo

dtmax Dtmax

kfn Kfn

afn Afn

bfn Bfn

imelt Imelt

bvbe wBvbe

bvbc wBvbc

bvsub wBvsub

vbcfwd wVbcfwd

vsubfwd wVsubfwd

imax Imax

imax1 wIcmax

Table 3-35. Supported VBIC Model DC Operating Point Parameters

Spectre ADSsim

cbcp cbcp

cbep cbep

cbex cbex

dic_dvbc dicc_dvbci

dic_dvbe dicc_dvbei




ib ib

ic ic

pwr power

vbc vbc

vbe vbe

vce vce

Table 3-35. Supported VBIC Model DC Operating Point Parameters

Spectre ADSsim



BSIM3v3

Table 3-36 shows the supported bsim3v3 instance parameter mapping. The Spectre bsim3v3 instance is mapped to the ADSsim bsim3v3 instance.

For more information on the bsim3v3 model, refer to BSIM3v3 Level-11 Model (bsim3v3) in Chapter 20 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the MOSFET device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-36. Supported bsim3v3 Instance Parameters


w Width

l Length

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

region Region off -> 0triode -> 1sat -> 3others-> (ignored)

nqsmod Nqsmod

trise Trise

geo Geo

delk1 Delk1

delnfct Delnfct

delvto Delvt0

mulu0 Mulu0

sa Sa

sb Sb

acnqsmod Acnqsmod


Table 3-37 shows the supported bsim3v3 model parameter mapping. The Spectre bsim3v3 model is mapped to the ADSsim MOSFET model with Idsmod=8 (BSIM3_Model).

For more information on the bsim3v3 model in RFDE, refer to BSIM3_Model (BSIM3 MOSFET Model) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-37. Supported bsim3v3 Model Parameters


type NMOS & PMOS type=n-> NMOS=yes PMOS=notype=p-> NMOS=no PMOS=yes

vtho Vth0

vth0 Vth0

vfb Vfb

k1 K1

k2 K2

k3 K3

k3b K3b

w0 W0

nlx Nlx

gamma1 Gamma1

gamma2 Gamma2

vbx Vbx

vbm Vbm

dvt0 Dvt0

dvt1 Dvt1

dvt2 Dvt2

dvt0w Dvt0w

dvt1w Dvt1w

dvt2w Dvt2w

a0 A0

b0 B0

b1 B1

a1 A1

a2 A2

ags Ags

keta Keta

vfbflag Vfbflag



nsub Nsub

nch Nch

ngate Ngate

xj Xj

lint Lint

wint Wint

ll Ll

lln Lln

lw Lw

lwn Lwn

lwl Lwl

wl Wl

wln Wln

ww Ww

wwn Wwn

wwl Wwl

dwg Dwg

dwb Dwb

tox Tox

dtoxcv Dtoxcv

toxm Toxm

xt Xt

rdsw Rdsw

prwb Prwb

prwg Prwg

wr Wr

binunit Binunit

mobmod Mobmod

u0 U0

vsat Vsat

ua Ua

ub Ub

uc Uc

drout Drout

pclm Pclm




pdiblc1 Pdiblc1

pdiblc2 Pdiblc2

pdiblcb Pdiblcb

pscbe1 Pscbe1

pscbe2 Pscbe2

pvag Pvag

delta Delta

cdsc Cdsc

cdscb Cdscb

cdscd Cdscd

nfactor Nfactor

cit Cit

voff Voff

dsub Dsub

eta0 Eta0

etab Etab

alpha0 Alpha0

alpha1 Alpha1

beta0 Beta0

rsh Rsh

rs Rs

rd Rd

lgcs Lgcs

lgcd Lgcd

rsc Rsc

rdc Rdc

rss Rss

rdd Rdd

sc Sc

ldif Ldif

hdif Hdif

minr Minr

js Js

jsw Jsw

is Is





n Nj

imelt Imelt

ijth Ijth

tt Tt

cgso Cgso

cgdo Cgdo

cgbo Cgbo

cgsl Cgsl

cgdl Cgdl

ckappa Ckappa

cbs Cbs

cbd Cbd

cj Cj

mj Mj

pb Pb

fc Fc

cjsw Cjsw

mjsw Mjsw

pbsw Pbsw

cjswg Cjswg

mjswg Mjswg

pbswg Pbswg

capmod Capmod

nqsmod Nqsmod

dwc Dwc

dlc Dlc

clc Clc

cle Cle

cf Cf

elm Elm

vfbcv Vfbcv

acde Acde

moin Moin

noff Noff

voffcv Voffcv




xpart Xpart

llc Llc

lwc Lwc

lwlc Lwlc

wlc Wlc

wwc Wwc

wwlc Wwlc

wmlt Wmlt

w W

l L

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

version Version

paramchk Paramchk

acm Acm

calcacm Calcacm

tnom Tnom

trise Trise

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

kt1 Kt1

kt1l Kt1l

kt2 Kt2

at At

ua1 Ua1

ub1 Ub1

uc1 Uc1

prt Prt





trs Trs

trd Trd

ute Ute

xti Xti

pta Pta

tpb Tpb

ptp Ptp

tpbsw Tpbsw

tpbswg Tpbswg

cta Cta

tcj Tcj

ctp Ctp

tcjsw Tcjsw

tcjswg Tcjswg

noimod Noimod

kf Kf

af Af

ef Ef

noia Noia

noib Noib

noic Noic

em Em

flkmod Flkmod

gamma Gamma

nlev Nlev

gdsnoi Gdsnoi

wmax Wmax

wmin Wmin

lmax Lmax

lmin Lmin

imax Imax

bvj wBvsub

vbox wBvg

xl Xl

xw Xw




sa0 Sa0

sb0 Sb0

wlod Wlod

ku0 Ku0

kvsat Kvsat

kvth0 Kvth0

tku0 Tku0

llodku0 Llodku0

wlodku0 Wlodku0

lku0 Lku0

wku0 Wku0

pku0 Pku0

lkvth0 Lkvth0

wkvth0 Wkvth0

pkvth0 Pkvth0

stk2 Stk2

lodk2 Lodk2

steta0 Steta0

lodeta0 Lodeta0

nj Nj

idsmod Idsmod

lxt Lxt

lvbm Lvbm

lvbx Lvbx

lvfbcv Lvfbcv

lvfb Lvfb

lxj Lxj

ldwg Ldwg

ldwb Ldwb

lnch Lnch

lnsub Lnsub

lngate Lngate

lgamma1 Lgamma1

lgamma2 Lgamma2

lalpha0 Lalpha0





lalpha1 Lalpha1

lacde Lacde

lmoin Lmoin

lelm Lelm

lbeta0 Lbeta0

lvth0 Lvth0

lk1 Lk1

lk2 Lk2

lk3 Lk3

lk3b Lk3b

lw0 Lw0

lnlx Lnlx

ldvt0 Ldvt0

ldvt1 Ldvt1

ldvt2 Ldvt2

ldvt0w Ldvt0w

ldvt1w Ldvt1w

ldvt2w Ldvt2w

ldrout Ldrout

ldsub Ldsub

lua Lua

lua1 Lua1

lub Lub

lub1 Lub1

luc Luc

luc1 Luc1

lu0 Lu0

lute Lute

lrdsw Lrdsw

lprwg Lprwg

lprwb Lprwb

lwr Lwr

lprt Lprt

lvsat Lvsat

lat Lat




la0 La0

lketa Lketa

lags Lags

la1 La1

la2 La2

lb0 Lb0

lb1 Lb1

lvoff Lvoff

lvoffcv Lvoffcv

lnoff Lnoff

lnfactor Lnfactor

lcdsc Lcdsc

lcdscb Lcdscb

lcdscd Lcdscd

lcit Lcit

leta0 Leta0

letab Letab

lpclm Lpclm

lpdiblc1 Lpdiblc1

lpdiblc2 Lpdiblc2

lpdiblcb Lpdiblcb

lpscbe1 Lpscbe1

lpscbe2 Lpscbe2

lpvag Lpvag

ldelta Ldelta

lkt1 Lkt1

lkt1l Lkt1l

lkt2 Lkt2

lcgsl Lcgsl

lcgdl Lcgdl

lckappa Lckappa

lcf Lcf

lclc Lclc

lcle Lcle

pxt Pxt





pvbm Pvbm

pvbx Pvbx

pvfbcv Pvfbcv

pvfb Pvfb

pxj Pxj

pdwg Pdwg

pdwb Pdwb

pnch Pnch

pnsub Pnsub

pngate Pngate

pgamma1 Pgamma1

pgamma2 Pgamma2

palpha0 Palpha0

palpha1 Palpha1

pacde Pacde

pmoin Pmoin

pelm Pelm

pbeta0 Pbeta0

pvth0 Pvth0

pk1 Pk1

pk2 Pk2

pk3 Pk3

pk3b Pk3b

pw0 Pw0

pnlx Pnlx

pdvt0 Pdvt0

pdvt1 Pdvt1

pdvt2 Pdvt2

pdvt0w Pdvt0w

pdvt1w Pdvt1w

pdvt2w Pdvt2w

pdrout Pdrout

pdsub Pdsub

pua Pua

pua1 Pua1




pub Pub

pub1 Pub1

puc Puc

puc1 Puc1

pu0 Pu0

pute Pute

prdsw Prdsw

pprwg Pprwg

pprwb Pprwb

pwr Pwr

pprt Pprt

pvsat Pvsat

pat Pat

pa0 Pa0

pketa Pketa

pags Pags

pa1 Pa1

pa2 Pa2

pb0 Pb0

pb1 Pb1

pvoff Pvoff

pvoffcv Pvoffcv

pnoff Pnoff

pnfactor Pnfactor

pcdsc Pcdsc

pcdscb Pcdscb

pcdscd Pcdscd

pcit Pcit

peta0 Peta0

petab Petab

ppclm Ppclm

ppdiblc1 Ppdiblc1

ppdiblc2 Ppdiblc2

ppdiblcb Ppdiblcb

ppscbe1 Ppscbe1





ppscbe2 Ppscbe2

ppvag Ppvag

pdelta Pdelta

pkt1 Pkt1

pkt1l Pkt1l

pkt2 Pkt2

pcgsl Pcgsl

pcgdl Pcgdl

pckappa Pckappa

pcf Pcf

pclc Pclc

pcle Pcle

wxt Wxt

wvbm Wvbm

wvbx Wvbx

wvfbcv Wvfbcv

wvfb Wvfb

wxj Wxj

wdwg Wdwg

wdwb Wdwb

wnch Wnch

wnsub Wnsub

wngate Wngate

wgamma1 Wgamma1

wgamma2 Wgamma2

walpha0 Walpha0

walpha1 Walpha1

wacde Wacde

wmoin Wmoin

welm Welm

wbeta0 Wbeta0

wvth0 Wvth0

wk1 Wk1

wk2 Wk2

wk3 Wk3




wk3b Wk3b

ww0 Ww0

wnlx Wnlx

wdvt0 Wdvt0

wdvt1 Wdvt1

wdvt2 Wdvt2

wdvt0w Wdvt0w

wdvt1w Wdvt1w

wdvt2w Wdvt2w

wdrout Wdrout

wdsub Wdsub

wua Wua

wua1 Wua1

wub Wub

wub1 Wub1

wuc Wuc

wuc1 Wuc1

wu0 Wu0

wute Wute

wrdsw Wrdsw

wprwg Wprwg

wprwb Wprwb

wwr Wwr

wprt Wprt

wvsat Wvsat

wat Wat

wa0 Wa0

wketa Wketa

wags Wags

wa1 Wa1

wa2 Wa2

wb0 Wb0

wb1 Wb1

wvoff Wvoff

wvoffcv Wvoffcv





Table 3-38 shows the supported bsim3v3 model DC operating point parameter mapping. The Spectre bsim3v3 model is mapped to the ADSsim MOSFET model.

wnoff Wnoff

wnfactor Wnfactor

wcdsc Wcdsc

wcdscb Wcdscb

wcdscd Wcdscd

wcit Wcit

weta0 Weta0

wetab Wetab

wpclm Wpclm

wpdiblc1 Wpdiblc1

wpdiblc2 Wpdiblc2

wpdiblcb Wpdiblcb

wpscbe1 Wpscbe1

wpscbe2 Wpscbe2

wpvag Wpvag

wdelta Wdelta

wkt1 Wkt1

wkt1l Wkt1l

wkt2 Wkt2

wcgsl Wcgsl

wcgdl Wcgdl

wckappa Wckappa

wcf Wcf

wclc Wclc

wcle Wcle

llodvth Llodvth

acnqsmod Acnqsmod

lintnoi Lintnoi




Table 3-38. Supported bsim3v3 Model DC Operating Point Parameters

Spectre ADSsim

cbd dqbdvdb

cbg dqbdvgb

cbs dqbdvsb

cdd dqddvdb

cdg dqddvgb

cds dqddvsb

cgd dqgdvdb

cgg dqgdvgb

cgs dqgdvsb

cjd capbd

cjs capbs

gds gds

gm gm

gmbs gmb

i1 id

i3 is

i4 ib

ibulk ib

id id

is is

lv10 vdsat

lv9 vth

lx1 vbs

lx18 dqgdvgb

lx19 dqgdvdb

lx2 vgs

lx20 dqgdvsb

lx21 dqbdvgb

lx22 dqbdvdb

lx23 dqbdvsb

lx28 capbs

lx29 capbd

lx3 vds

lx32 dqddvgb



lx33 dqddvdb

lx34 dqddvsb

lx7 gm

lx8 gds

lx9 gmb

pwr power

vbs vbs

vds vds

vdsat vdsat

vgs vgs

vth vth

Table 3-38. Supported bsim3v3 Model DC Operating Point Parameters

Spectre ADSsim


BSIM4

Table 3-39 shows the supported bsim4 instance parameter mapping. The Spectre bsim4 instance is mapped to the ADSsim bsim4 instance.

For more information on the bsim4 model, refer to BSIM4.2 Level-14 Model (bsim4) in Chapter 21 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the BSIM4 device in RFDE, refer to BSIM4_NMOS, BSIM4_PMOS (BSIM4 Transistor, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-39. Supported bsim4 Instance Parameter Mapping


w Width

l Length

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

trnqsmod Trnqsmod

acnqsmod Acnqsmod

trise Trise

dtemp Trise alias of trise

rgatemod Rgatemod

rbodymod Rbodymod

geomod Geomod

rgeomod Rgeomod

rbpb Rbpb

rbpd Rbpd

rbps Rbps

rbdb Rbdb

rbsb Rbsb

nf Nf

min Min

sa Sa



Table 3-40 shows the supported bsim4 model parameter mapping. The Spectre bsim4 model is mapped to the ADSsim BSIM4 model.

For more information on the bsim4 model in RFDE, refer to BSIM4_Model (BSIM4 MOSFET Model) in Chapter 5 of the Nonlinear Devices documentation.

sb Sb

sd Sd

delvto Delvt0

mulu0 Mulu0

delk1 Delk1

delnfct Delnfct

Table 3-40. Supported bsim4 Model Parameter Mapping



vtho Vth0

vth0 Vth0

phin Phin

k1 K1

k2 K2

k3 K3

k3b K3b

w0 W0

lpe0 Lpe0

lpeb Lpeb

gamma1 Gamma1

gamma2 Gamma2

vbx Vbx

vbm Vbm

dvt0 Dvt0

dvt1 Dvt1

dvt2 Dvt2

dvtp0 Dvtp0

dvtp1 Dvtp1

Table 3-39. Supported bsim4 Instance Parameter Mapping



dvt0w Dvt0w

dvt1w Dvt1w

dvt2w Dvt2w

a0 A0

b0 B0

b1 B1

a1 A1

a2 A2

ags Ags

keta Keta

epsrox Epsrox

toxe Toxe

toxp Toxp

dtox Dtox

ndep Ndep

nsd Nsd

nsub Nsub

ngate Ngate

xj Xj

lint Lint

wint Wint

ll Ll

lln Lln

lw Lw

lwn Lwn

lwl Lwl

wl Wl

wln Wln

ww Ww

wwn Wwn

wwl Wwl

dwg Dwg

dwb Dwb

toxm Toxm

xt Xt





binunit Binunit

rdsmod Rdsmod

rdsw Rdsw

rdswmin Rdswmin

rdw Rdw

rdwmin Rdwmin

rsw Rsw

rswmin Rswmin

prwb Prwb

prwg Prwg

wr Wr

mobmod Mobmod

u0 U0

vsat Vsat

ua Ua

ub Ub

uc Uc

eu Eu

lambda Lambda

vtl Vtl

lc Lc

xn Xn

drout Drout

fprout Fprout

pclm Pclm

pdiblc1 Pdiblc1

pdiblc2 Pdiblc2

pdiblcb Pdiblcb

pscbe1 Pscbe1

pscbe2 Pscbe2

pvag Pvag

delta Delta

pdits Pdits

pditsl Pditsl

pditsd Pditsd




cdsc Cdsc

cdscb Cdscb

cdscd Cdscd

nfactor Nfactor

cit Cit

voff Voff

voffl Voffl

minv Minv

dsub Dsub

eta0 Eta0

etab Etab

alpha0 Alpha0

alpha1 Alpha1

beta0 Beta0

rgatemod Rgatemod

rsh Rsh

rshg Rshg

dmcg Dmcg

dmci Dmci

dmdg Dmdg

dmcgt Dmcgt

dwj Dwj

xgw Xgw

xgl Xgl

ngcon Ngcon

nf Nf

permod Permod

geomod Geomod

rgeomod Rgeomod

xw Xw

xl Xl

agidl Agidl

bgidl Bgidl

cgidl Cgidl

egidl Egidl





igcmod Igcmod

igbmod Igbmod

aigbacc Aigbacc

bigbacc Bigbacc

cigbacc Cigbacc

nigbacc Nigbacc

aigbinv Aigbinv

bigbinv Bigbinv

cigbinv Cigbinv

eigbinv Eigbinv

nigbinv Nigbinv

aigc Aigc

bigc Bigc

cigc Cigc

aigsd Aigsd

bigsd Bigsd

cigsd Cigsd

dlcig Dlcig

nigc Nigc

poxedge Poxedge

pigcd Pigcd

ntox Ntox

toxref Toxref

diomod Diomod

jss Jss

jsd Jsd

jsws Jsws

jswd Jswd

jswgs Jswgs

jswgd Jswgd

njs Njs

njd Njd

imelt Imelt

ijthsrev Ijthsrev

ijthdrev Ijthdrev




ijthsfwd Ijthsfwd

ijthdfwd Ijthdfwd

xjbvs Xjbvs

xjbvd Xjbvd

cgso Cgso

cgdo Cgdo

cgbo Cgbo

cgsl Cgsl

cgdl Cgdl

ckappas Ckappas

ckappad Ckappad

cjs Cjs

cjd Cjd

mjs Mjs

mjd Mjd

pbs Pbs

pbd Pbd

cjsws Cjsws

cjswd Cjswd

mjsws Mjsws

mjswd Mjswd

pbsws Pbsws

pbswd Pbswd

cjswgs Cjswgs

cjswgd Cjswgd

mjswgs Mjswgs

mjswgd Mjswgd

pbswgs Pbswgs

pbswgd Pbswgd

bvs Bvs

bvd Bvd

capmod Capmod

trnqsmod Trnqsmod

acnqsmod Acnqsmod

dwc Dwc





dlc Dlc

clc Clc

cle Cle

cf Cf

vfbcv Vfbcv

acde Acde

moin Moin

noff Noff

voffcv Voffcv

xpart Xpart

llc Llc

lwc Lwc

lwlc Lwlc

wlc Wlc

wwc Wwc

wwlc Wwlc

w W

l L

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

version Version

paramchk Paramchk

tnom Tnom

trise Trise

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

kt1 Kt1

kt1l Kt1l




kt2 Kt2

at At

ua1 Ua1

ub1 Ub1

uc1 Uc1

prt Prt

ute Ute

xtis Xtis

xtid Xtid

pta Pta

tpb Tpb

ptp Ptp

tpbsw Tpbsw

tpbswg Tpbswg

cta Cta

tcj Tcj

ctp Ctp

tcjsw Tcjsw

tcjswg Tcjswg

tempmod Tempmod

saref Saref

sbref Sbref

wlod Wlod

ku0 Ku0

kvsat Kvsat

kvth0 Kvth0

tku0 Tku0

llodku0 Llodku0

wlodku0 Wlodku0

llodvth Llodvth

wlodvth Wlodvth

lku0 Lku0

wku0 Wku0

pku0 Pku0

lkvth0 Lkvth0





wkvth0 Wkvth0

pkvth0 Pkvth0

stk2 Stk2

lodk2 Lodk2

steta0 Steta0

lodeta0 Lodeta0

fnoimod Fnoimod

tnoimod Tnoimod

kf Kf

af Af

ef Ef

noia Noia

noib Noib

noic Noic

em Em

ntnoi Ntnoi

tnoia Tnoia

tnoib Tnoib

rnoia Rnoia

rnoib Rnoib

rbodymod Rbodymod

xrcrg1 Xrcrg1

xrcrg2 Xrcrg2

rbpb Rbpb

rbpd Rbpd

rbps Rbps

rbdb Rbdb

rbsb Rbsb

gbmin Gbmin

wmax Wmax

wmin Wmin

lmax Lmax

lmin Lmin

vbox wBvg

llambda Llambda




wlambda Wlambda

plambda Plambda

lvtl Lvtl

wvtl Wvtl

pvtl Pvtl

lxn Lxn

wxn Wxn

pxn Pxn

lcdsc Lcdsc

lcdsc Lcdsc

lcdscb Lcdscb

lcdscd Lcdscd

lcit Lcit

lnfactor Lnfactor

lxj Lxj

lvsat Lvsat

lat Lat

la0 La0

lags Lags

la1 La1

la2 La2

lketa Lketa

lnsub Lnsub

lndep Lndep

lnsd Lnsd

lphin Lphin

lngate Lngate

lgamma1 Lgamma1

lgamma2 Lgamma2

lvbx Lvbx

lvbm Lvbm

lxt Lxt

lk1 Lk1

lkt1 Lkt1

lkt1l Lkt1l





lkt2 Lkt2

lk2 Lk2

lk3 Lk3

lk3b Lk3b

lw0 Lw0

ldvtp0 Ldvtp0

ldvtp1 Ldvtp1

llpe0 Llpe0

llpeb Llpeb

ldvt0 Ldvt0

ldvt1 Ldvt1

ldvt2 Ldvt2

ldvt0w Ldvt0w

ldvt1w Ldvt1w

ldvt2w Ldvt2w

ldrout Ldrout

ldsub Ldsub

lvth0 Lvth0

lua Lua

lua1 Lua1

lub Lub

lub1 Lub1

luc Luc

luc1 Luc1

lu0 Lu0

lute Lute

lvoff Lvoff

lminv Lminv

ldelta Ldelta

lrdsw Lrdsw

lrsw Lrsw

lrdw Lrdw

lprwg Lprwg

lprwb Lprwb

lprt Lprt




leta0 Leta0

letab Letab

lpclm Lpclm

lpdiblc1 Lpdiblc1

lpdiblc2 Lpdiblc2

lpdiblcb Lpdiblcb

lfprout Lfprout

lpdits Lpdits

lpditsd Lpditsd

lpscbe1 Lpscbe1

lpscbe2 Lpscbe2

lpvag Lpvag

lwr Lwr

ldwg Ldwg

ldwb Ldwb

lb0 Lb0

lb1 Lb1

lcgsl Lcgsl

lcgdl Lcgdl

lckappas Lckappas

lckappad Lckappad

lcf Lcf

lclc Lclc

lcle Lcle

lalpha0 Lalpha0

lalpha1 Lalpha1

lbeta0 Lbeta0

lagidl Lagidl

lbgidl Lbgidl

lcgidl Lcgidl

legidl Legidl

laigc Laigc

lbigc Lbigc

lcigc Lcigc

laigsd Laigsd





lbigsd Lbigsd

lcigsd Lcigsd

laigbacc Laigbacc

lbigbacc Lbigbacc

lcigbacc Lcigbacc

laigbinv Laigbinv

lbigbinv Lbigbinv

lcigbinv Lcigbinv

lnigc Lnigc

lnigbinv Lnigbinv

lnigbacc Lnigbacc

lntox Lntox

leigbinv Leigbinv

lpigcd Lpigcd

lpoxedge Lpoxedge

lvfbcv Lvfbcv

lvfb Lvfb

lacde Lacde

lmoin Lmoin

lnoff Lnoff

lvoffcv Lvoffcv

lxrcrg1 Lxrcrg1

lxrcrg2 Lxrcrg2

leu Leu

wcdsc Wcdsc

wcdscb Wcdscb

wcdscd Wcdscd

wcit Wcit

wnfactor Wnfactor

wxj Wxj

wvsat Wvsat

wat Wat

wa0 Wa0

wags Wags

wa1 Wa1




wa2 Wa2

wketa Wketa

wnsub Wnsub

wndep Wndep

wnsd Wnsd

wphin Wphin

wngate Wngate

wgamma1 Wgamma1

wgamma2 Wgamma2

wvbx Wvbx

wvbm Wvbm

wxt Wxt

wk1 Wk1

wkt1 Wkt1

wkt1l Wkt1l

wkt2 Wkt2

wk2 Wk2

wk3 Wk3

wk3b Wk3b

ww0 Ww0

wdvtp0 Wdvtp0

wdvtp1 Wdvtp1

wlpe0 Wlpe0

wlpeb Wlpeb

wdvt0 Wdvt0

wdvt1 Wdvt1

wdvt2 Wdvt2

wdvt0w Wdvt0w

wdvt1w Wdvt1w

wdvt2w Wdvt2w

wdrout Wdrout

wdsub Wdsub

wvth0 Wvth0

wua Wua

wua1 Wua1





wub Wub

wub1 Wub1

wuc Wuc

wuc1 Wuc1

wu0 Wu0

wute Wute

wvoff Wvoff

wminv Wminv

wdelta Wdelta

wrdsw Wrdsw

wrsw Wrsw

wrdw Wrdw

wprwg Wprwg

wprwb Wprwb

wprt Wprt

weta0 Weta0

wetab Wetab

wpclm Wpclm

wpdiblc1 Wpdiblc1

wpdiblc2 Wpdiblc2

wpdiblcb Wpdiblcb

wfprout Wfprout

wpdits Wpdits

wpditsd Wpditsd

wpscbe1 Wpscbe1

wpscbe2 Wpscbe2

wpvag Wpvag

wwr Wwr

wdwg Wdwg

wdwb Wdwb

wb0 Wb0

wb1 Wb1

wcgsl Wcgsl

wcgdl Wcgdl

wckappas Wckappas




wckappad Wckappad

wcf Wcf

wclc Wclc

wcle Wcle

walpha0 Walpha0

walpha1 Walpha1

wbeta0 Wbeta0

wagidl Wagidl

wbgidl Wbgidl

wcgidl Wcgidl

wegidl Wegidl

waigc Waigc

wbigc Wbigc

wcigc Wcigc

waigsd Waigsd

wbigsd Wbigsd

wcigsd Wcigsd

waigbacc Waigbacc

wbigbacc Wbigbacc

wcigbacc Wcigbacc

waigbinv Waigbinv

wbigbinv Wbigbinv

wcigbinv Wcigbinv

wnigc Wnigc

wnigbinv Wnigbinv

wnigbacc Wnigbacc

wntox Wntox

weigbinv Weigbinv

wpigcd Wpigcd

wpoxedge Wpoxedge

wvfbcv Wvfbcv

wvfb Wvfb

wacde Wacde

wmoin Wmoin

wnoff Wnoff





wvoffcv Wvoffcv

wxrcrg1 Wxrcrg1

wxrcrg2 Wxrcrg2

weu Weu

pcdsc Pcdsc

pcdscb Pcdscb

pcdscd Pcdscd

pcit Pcit

pnfactor Pnfactor

pxj Pxj

pvsat Pvsat

pat Pat

pa0 Pa0

pags Pags

pa1 Pa1

pa2 Pa2

pketa Pketa

pnsub Pnsub

pndep Pndep

pnsd Pnsd

pphin Pphin

pngate Pngate

pgamma1 Pgamma1

pgamma2 Pgamma2

pvbx Pvbx

pvbm Pvbm

pxt Pxt

pk1 Pk1

pkt1 Pkt1

pkt1l Pkt1l

pkt2 Pkt2

pk2 Pk2

pk3 Pk3

pk3b Pk3b

pw0 Pw0




pdvtp0 Pdvtp0

pdvtp1 Pdvtp1

plpe0 Plpe0

plpeb Plpeb

pdvt0 Pdvt0

pdvt1 Pdvt1

pdvt2 Pdvt2

pdvt0w Pdvt0w

pdvt1w Pdvt1w

pdvt2w Pdvt2w

pdrout Pdrout

pdsub Pdsub

pvth0 Pvth0

pua Pua

pua1 Pua1

pub Pub

pub1 Pub1

puc Puc

puc1 Puc1

pu0 Pu0

pute Pute

pvoff Pvoff

pminv Pminv

pdelta Pdelta

prdsw Prdsw

prsw Prsw

prdw Prdw

pprwg Pprwg

pprwb Pprwb

pprt Pprt

peta0 Peta0

petab Petab

ppclm Ppclm

ppdiblc1 Ppdiblc1

ppdiblc2 Ppdiblc2





ppdiblcb Ppdiblcb

pfprout Pfprout

ppdits Ppdits

ppditsd Ppditsd

ppscbe1 Ppscbe1

ppscbe2 Ppscbe2

ppvag Ppvag

pwr Pwr

pdwg Pdwg

pdwb Pdwb

pb0 Pb0

pb1 Pb1

pcgsl Pcgsl

pcgdl Pcgdl

pckappas Pckappas

pckappad Pckappad

pcf Pcf

pclc Pclc

pcle Pcle

palpha0 Palpha0

palpha1 Palpha1

pbeta0 Pbeta0

pagidl Pagidl

pbgidl Pbgidl

pcgidl Pcgidl

pegidl Pegidl

paigc Paigc

pbigc Pbigc

pcigc Pcigc

paigsd Paigsd

pbigsd Pbigsd

pcigsd Pcigsd

paigbacc Paigbacc

pbigbacc Pbigbacc

pcigbacc Pcigbacc




Table 3-41 shows the supported bsim4 model DC operating point parameter mapping. The Spectre bsim4 model is mapped to the ADSsim BSIM4 model.

paigbinv Paigbinv

pbigbinv Pbigbinv

pcigbinv Pcigbinv

pnigc Pnigc

pnigbinv Pnigbinv

pnigbacc Pnigbacc

pntox Pntox

peigbinv Peigbinv

ppigcd Ppigcd

ppoxedge Ppoxedge

pvfbcv Pvfbcv

pvfb Pvfb

pacde Pacde

pmoin Pmoin

pnoff Pnoff

pvoffcv Pvoffcv

pxrcrg1 Pxrcrg1

pxrcrg2 Pxrcrg2

peu Peu

Table 3-41. Supported bsim4 Model DC Operating Point Parameters

Spectre ADSsim

cbd dqb_dvdb

cbg dqb_dvgb

cbs dqb_dvsb

cdd dqd_dvdb

cdg dqd_dvgb

cds dqd_dvsb

cgb dqg_dvsb

cgd dqg_dvdb

cgg dqg_dvgb

gds gds





gm gm

gmbs gmb

ibulk ib

id id

lv10 vdsat

lv9 vth

lx1 vbs

lx2 vgs

lx3 vds

lx7 gm

lx8 gds

lx82 dqg_dvgb

lx83 dqg_dvdb

lx85 dqd_dvdb

lx86 dqd_dvsb

lx87 dqd_dvgb

lx88 dqb_dvgb

lx89 dqb_dvdb

lx9 gmb

lx90 dqb_dvsb

pwr power

vbs vbs

vds vds

vdsat vdsat

vgs vgs

vth vth

Table 3-41. Supported bsim4 Model DC Operating Point Parameters

Spectre ADSsim


MOS1

Table 3-42 shows the supported mos1 instance parameter mapping. The Spectre mos1 instance is mapped to the ADSsim mos1 instance.

For more information on the mos1 model, refer to MOS Level-1 Model (mos1) in Chapter 14 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the mos1 device in RFDE, refer to MOSFET_NMOS, MOSFET_PMOS (Nonlinear MOSFETs, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-43 shows the supported mos1 model parameter mapping. The Spectre mos1 model is mapped to the ADSsim MOSFET model with Idsmod=1 (LEVEL1_Model).

For more information on the mos1 model in RFDE, refer to LEVEL1_Model (MOSFET Level-1Model) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-42. Supported mos1 Instance Parameters


w Width

l Length

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs


nqsmod Nqsmod

trise Trise

Table 3-43. Supported mos1 Model Parameters



vto Vto



kp Kp

lambda Lambda

phi Phi

gamma Gamma

uo Uo

vmax Vmax

theta Theta

nsub Nsub

nss Nss

nfs Nfs

tpg Tpg

ld Ld

tox Tox

ai0 Ai0

lai0 Lai0

wai0 Wai0

bi0 Bi0

lbi0 Lbi0

wbi0 Wbi0

cgso Cgso

cgdo Cgdo

capmod Capmod spectre ADSnone --> 0 (no)meyer --> 3 (qmeyer)yang --> 1 (meyer_ward)bsim --> 2 (smooth)

xpart Xpart

xqc Xpart

rs Rs

rd Rd

rss Rss

rdd Rdd

rsh Rsh

rsc Rsc

rdc Rdc

minr Minr




ldif Ldif

hdif Hdif

lgcs Lgcs

lgcd Lgcd

sc Sc

js Js

is Is

n N

imelt Imelt

cbs Cbs

cbd Cbd

cj Cj

mj Mj

pb Pb

fc Fc

cjsw Cjsw

mjsw Mjsw

pbsw Pbsw

imax Imax

bvj wBvsub

vbox wBvg

tnom Tnom

trise Trise

ute Ute

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

trs Trs

trd Trd

xti Xti

pta Pta

ptp Ptp

cta Cta





Table 3-44 shows the supported mos1 model DC operating point parameter mapping. The Spectre mos1 model is mapped to the ADSsim MOSFET model.

ctp Ctp

w W

l L

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

noisemod Noimod

kf Kf

af Af

ef Ef

wmax Wmax

wmin Wmin

lmax Lmax

lmin Lmin

idsmod Idsmod

Table 3-44. Supported mos1 Model DC Operating Point Parameters

Spectre ADSsim

cbd dqbdvdb

cbg dqbdvgb

cbs dqbdvsb

cdd dqddvdb

cdg dqddvgb

cds dqddvsb

cgd dqgdvdb

cgg dqgdvgb

cgs dqgdvsb

cjd capbd

cjs capbs




gds gds

gm gm

gmbs gmb

i1 id

i3 is

i4 ib

ibulk ib

id id

is is

lv10 vdsat

lv9 vth

lx1 vbs

lx18 dqgdvgb

lx19 dqgdvdb

lx2 vgs

lx20 dqgdvsb

lx21 dqbdvgb

lx22 dqbdvdb

lx23 dqbdvsb

lx28 capbs

lx29 capbd

lx3 vds

lx32 dqddvgb

lx33 dqddvdb

lx34 dqddvsb

lx7 gm

lx8 gds

lx9 gmb

pwr power

vbs vbs

vds vds

vdsat vdsat

vgs vgs

vth vth


Spectre ADSsim



MOS2





For more information on the mos2 model in RFDE, refer to LEVEL2_Model (MOSFET Level-2 Model) in Chapter 5 of the Nonlinear Devices documentation.



w Width

l Length

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs


trise Trise




vto Vto

kp KP


lambda Lambda

phi Phi

gamma Gamma

uo Uo

vmax Vmax

ucrit Ucrit

uexp Uexp

neff Neff

delta Delta

nsub Nsub

nss Nss

nfs Nfs

tpg Tpg

tox Tox

ld Ld

xl Xl

xw Xw

xj Xj

ai0 Ai0

lai0 Lai0

wai0 Wai0

bi0 Bi0

lbi0 Lbi0

wbi0 Wbi0

cgso Cgso

cgdo Cgdo

cgbo Cgbo


xpart Xpart

xqc Xqc

rs Rs

rd Rd





rsh Rsh

rsc Rsc

rdc Rdc

minr Minr

ldif Ldif

hdif Hdif

lgcs Lgcs

lgcd Lgcd

sc Sc

js Js

is Is

n N

imelt Imelt

cbs Cbs

cbd Cbd

cj Cj

mj Mj

pb Pb

fc Fc

cjsw Cjsw

mjsw Mjsw

pbsw Pbsw

imax Imax

vbox wBvg

tnom Tnom

trise Trise

ute Ute

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

trs Trs

trd Trd

xti Xti





pta Pta

ptp Ptp

cta Cta

ctp Ctp

w W

l L

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

noisemod Noimod

kf Kf

af Af

ef Ef

wmax Wmax

wmin Wmin

lmax Lmax

lmin Lmin


Spectre ADSsim

cbd dqbdvdb

cbg dqbdvgb

cbs dqbdvsb

cdd dqddvdb

cdg dqddvgb

cds dqddvsb

cgd dqgdvdb

cgg dqgdvgb

cgs dqgdvsb





cjd capbd

cjs capbs

gds gds

gm gm

gmbs gmb

i1 id

i3 is

i4 ib

ibulk ib

id id

is is

lv10 vdsat

lv9 vth

lx1 vbs

lx18 dqgdvgb

lx19 dqgdvdb

lx2 vgs

lx20 dqgdvsb

lx21 dqbdvgb

lx22 dqbdvdb

lx23 dqbdvsb

lx28 capbs

lx29 capbd

lx3 vds

lx32 dqddvgb

lx33 dqddvdb

lx34 dqddvsb

lx7 gm

lx8 gds

lx9 gmb

pwr power

vbs vbs

vds vds

vdsat vdsat


Spectre ADSsim


vgs vgs

vth vth


Spectre ADSsim



MOS3





For more information on the mos3 model in RFDE, refer to LEVEL3_Model (MOSFET Level-3 Model) in Chapter 5 of the Nonlinear Devices documentation.



w Width

l Length

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs


trise Trise




vto Vto

kp Kp


theta Theta

phi Phi

gamma Gamma

uo Uo

vmax Vmax

eta Eta

kappa Kappa

delta Delta

nsub Nsub

nss Nss

nfs Nfs

tpg Tpg

tox Tox

ld Ld

xl Xl

xw Xw

xj Xj

ai0 Ai0

lai0 Lai0

wai0 Wai0

bi0 Bi0

lbi0 Lbi0

wbi0 Wbi0

cgso Cgso

cgdo Cgdo

cgbo Cgbo


xpart Xpart

xqc Xqc

rs Rs

rd Rd

rsh Rsh





rsc Rsc

rdc Rdc

ldif Ldif

hdif Hdif

lgcs Lgcs

lgcd Lgcd

sc Sc

js Js

is Is

n N

imelt Imelt

cbs Cbs

cbd Cbd

cj Cj

mj Mj

pb Pb

fc Fc

cjsw Cjsw

mjsw Mjsw

pbsw Pbsw

imax Imax

vbox wBvg

tnom Tnom

trise Trise

ute Ute

tlev Tlev

tlevc Tlevc

eg Eg

gap1 Gap1

gap2 Gap2

trs Trs

trd Trd

xti Xti

pta Pta

ptp Ptp





cta Cta

ctp Ctp

w W

l L

as As

ad Ad

ps Ps

pd Pd

nrd Nrd

nrs Nrs

noisemod Noimod

kf Kf

af Af

ef Ef

wmax Wmax

wmin Wmin

lmax Lmax

lmin Lmin

idsmod Idsmod


Spectre ADSsim

cbd dqbdvdb

cbg dqbdvgb

cbs dqbdvsb

cdd dqddvdb

cdg dqddvgb

cds dqddvsb

cgd dqgdvdb

cgg dqgdvgb

cgs dqgdvsb

cjd capbd





cjs capbs

gds gds

gm gm

gmbs gmb

i1 id

i3 is

i4 ib

ibulk ib

id id

is is

lv10 vdsat

lv9 vth

lx1 vbs

lx18 dqgdvgb

lx19 dqgdvdb

lx2 vgs

lx20 dqgdvsb

lx21 dqbdvgb

lx22 dqbdvdb

lx23 dqbdvsb

lx28 capbs

lx29 capbd

lx3 vds

lx32 dqddvgb

lx33 dqddvdb

lx34 dqddvsb

lx7 gm

lx8 gds

lx9 gmb

pwr power

vbs vbs

vds vds

vdsat vdsat

vgs vgs

vth vth


Spectre ADSsim


MOS902


For more information on the mos902 model, refer to Philips Models > Compact MOS-Transistor Model (mos902) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the mos902 device in RFDE, refer to MM9_NMOS, MM9_PMOS (Philips MOS Model 9, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-52 shows the supported mos902 model parameter mapping. The Spectre mos902 model is mapped to the ADSsim MOS9 model.

For more information on the mos902 model in RFDE, refer to MOS_Model9_Single (Philips MOS Model 9, Single Device) in Chapter 5 of the Nonlinear Devices documentation.



l Length

w Width

mult Mult

area Mult





ler Ler

wer Wer

lvar Lvar

lap Lap

wvar Wvar

wot Wot



wdog Wdog

vtor Vtor

slvto Slvto

stvto Stvto

sl2vto Sl2vto

swvto Swvto

kor Kor

slko Slko

swko Swko

kr Kr

slk Slk

swk Swk

phibr Phibr

vsbxr Vsbxr

slvsbx Slvsbx

swvsbx Swvsbx

betsq Betsq

etabet Etabet

the1r The1r

stthe1r Stthe1r

slthe1r Slthe1r

stlthe1 Stlthe1

swthe1 Swthe1

fthe1 Fthe1

the2r The2r

stthe2r Stthe2r

slthe2r Slthe2r

stlthe2 Stlthe2

swthe2 Swthe2

the3r The3r

stthe3r Stthe3r

slthe3r Slthe3r

stlthe3 Stlthe3

swthe3 Swthe3

gam1r Gam1r




slgam1 Slgam1

swgam1 Swgam1

etadsr Etadsr

alpr Alpr

slalp Slalp

swalp Swalp

vpr Vpr

gamoor Gamoor

slgamoo Slgamoo

etagamr Etagamr

mor Mor

stmo Stmo

slmo Slmo

etamr Etamr

zet1r Zet1r

etazet Etazet

slzet1 Slzet1

vsbtr Vsbtr

slvsbt Slvsbt

a1r A1r

sta1 Sta1

Sla1 Sla1

swa1 Swa1

a2r A2r

sla2 Sla2

swa2 Swa2

a3r A3r

sla3 Sla3

swa3 Swa3

tox Tox

col Col

ntr Ntr

nfr Nfr

tr Tr

tref Tr





Table 3-53 shows the supported mos902 model DC operating point parameter mapping. The Spectre mos902 model is mapped to the ADSsim MOS9 model.

tnom Tnom

trise Trise

the1r The1r

dta Trise alias for trise


Spectre ADSsim

cbb cb_sb

cbd cb_ds

cbg cb_gs

cdb cd_sb

cdd cd_ds

cdg cd_gs

cgb cg_sb

cgd cg_ds

cgg cg_gs

csb cs_sb

csd cs_ds

csg cs_gs

gds gid_ds

gm gid_gs

gmb gid_sb

ibe ib

ids id

ige ig

ise is

pwr power

vds vds

vgs vgs

vsb vbs




MOS903


For more information on the mos903 model, refer to Philips Models > Compact MOS-Transistor Model (mos903) in Chapter 11 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the mos903 device in RFDE, refer to MM9_NMOS, MM9_PMOS (Philips MOS Model 9, NMOS, PMOS) in Chapter 5 of the Nonlinear Devices documentation.

Table 3-55 shows the supported mos903 model parameter mapping. The Spectre mos903 model is mapped to the ADSsim MOS9 model.

For more information on the mos903 model in RFDE, refer to MOS_Model9_Single (Philips MOS Model 9, Single Device) in Chapter 5 of the Nonlinear Devices documentation.



l Length

w Width

mult Mult

area Mult





ler Ler

wer Wer

lvar Lvar

lap Lap

wvar Wvar

wot Wot



wdog Wdog

vtor Vtor

slvto Slvto

stvto Stvto

sl2vto Sl2vto

swvto Swvto

kor Kor

slko Slko

swko Swko

kr Kr

slk Slk

swk Swk

phibr Phibr

vsbxr Vsbxr

slvsbx Slvsbx

swvsbx Swvsbx

betsq Betsq

etabet Etabet

the1r The1r

stthe1r Stthe1r

slthe1r Slthe1r

stlthe1 Stlthe1

swthe1 Swthe1

fthe1 Fthe1

the2r The2r

stthe2r Stthe2r

slthe2r Slthe2r

stlthe2 Stlthe2

swthe2 Swthe2

the3r The3r

stthe3r Stthe3r

slthe3r Slthe3r

stlthe3 Stlthe3

swthe3 Swthe3

gam1r Gam1r




slgam1 Slgam1

swgam1 Swgam1

etadsr Etadsr

alpr Alpr

slalp Slalp

swalp Swalp

vpr Vpr

gamoor Gamoor

slgamoo Slgamoo

etagamr Etagamr

mor Mor

stmo Stmo

slmo Slmo

etamr Etamr

zet1r Zet1r

etazet Etazet

slzet1 Slzet1

vsbtr Vsbtr

slvsbt Slvsbt

a1r A1r

sta1 Sta1

Sla1 Sla1

swa1 Swa1

a2r A2r

sla2 Sla2

swa2 Swa2

a3r A3r

sla3 Sla3

swa3 Swa3

tox Tox

col Col

ntr Ntr

nfr Nfr

nfmod Nfmod

nfar Nfar





Table 3-56 shows the supported mos903 model DC operating point parameter mapping. The Spectre mos903 model is mapped to the ADSsim MOS9 model.

nfbr Nfbr

nfcr Nfcr

tr Tr

tref Tr

tnom Tr

trise Trise

dta Trise alias for trise


Spectre ADSsim

cbb cb_sb

cbd cb_ds

cbg cb_gs

cdb cd_sb

cdd cd_ds

cdg cd_gs

cgb cg_sb

cgd cg_ds

cgg cg_gs

csb cs_sb

csd cs_ds

csg cs_gs

gds gid_ds

gm gid_gs

gmb gid_sb

ibe ib

ids id

ige ig

ise is

pwr power

vds vds




vgs vgs

vsb vbs


Spectre ADSsim



JFET

Table 3-57 shows the supported jfet instance parameter mapping. The Spectre jfet instance is mapped to the ADSsim jfet instance.

For more information on the JFET model, refer to JFET Model (jfet) in Chapter 10 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

For more information on the JFET device in RFDE, refer to JFET_NFET, JFET_PFET (Nonlinear Junction FETs, P-Channel, N-Channel) in Chapter 4 of the Nonlinear Devices documentation.

Table 3-58 shows the supported jfet model parameter mapping. The Spectre jfet model is mapped to the ADSsim JFET model.

For more information on the JFET model in RFDE, refer to JFET_Model (Junction FET Model) in Chapter 4 of the Nonlinear Devices documentation.

Table 3-57. Supported JFET Instance Parameters


area Area

trise Trise


Table 3-58. Supported JFET Model Parameters


type NFET & PFET type=n -> NFET=yes PFET=notype=p -> NFET=no PFET=yes

vto Vto

beta Beta

lambda Lambda

rd Rd

rs Rs

is Is

n N

imelt Imelt

cgs Cgs


Table 3-59 shows the supported jfet model DC operating point parameter mapping. The Spectre jfet model is mapped to the ADSsim JFET model.

SourcesRFDE users can simulate polynomial and linear controlled sources in Spectre-Compatible PDKs. Agilent Technologies supports both linear and polynomial types of current and voltage controlled, current and voltage sources. Polynomial controlled sources (e.g. pvcvs or pcccs) can support multiple controlling inputs as long as the inputs are of the same type (i.e. all voltage or all current controllers); whereas, linear controlled sources are strictly for single input systems.

cgd Cgd

pb Pb

fc Fc

tnom Tnom

trise Trise

xti Xti

imax Imax

bvj wBvgd

kf Kf

af Af

Gdsnoise The Gdsnoise parameter is always added to the ADS translation, with a value of YES.

Table 3-59. Supported JFET Model DC Operating Point Parameters

Spectre ADSsim

cgd cgd

cgs cgs

gds gds

gm gm

ig ig

pwr power

vds vds

vgs vgs

Table 3-58. Supported JFET Model Parameters


Sources 3-115


Supported Sources

Table 3-60 shows a list of currently supported sources for Spectre-Compatible PDKs.

For more information on individual current sources, refer to Current Sources in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

Table 3-61 shows the supported isource DC operating point parameter mapping. The Spectre isource model is mapped to the ADSsim I_Source model.

For information on current sources in RFDE, refer to the Sources documentation.

For more information on individual voltage sources, refer to Voltage Sources in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

Table 3-62 shows the supported vsource DC operating point parameter mapping. The Spectre vsource model is mapped to the ADSsim V_Source model.

Table 3-60. Supported Sources

Source Type Linear Polynomial

Independent Current Source (isource) N/A N/A

Independent Voltage Source (vsource) N/A N/A

Current Controlled Current Source cccs pcccs

Current Controlled Voltage Source ccvs pccvs

Voltage Controlled Current Source vccs pvccs

Voltage Controlled Voltage Source vcvs pvcvs

Table 3-61. isource DC Operating Point Parameter Mapping

Spectre ADSsim

i is

pwr power

v vs

Table 3-62. vsource DC Operating Point Parameter Mapping

Spectre ADSsim

i is

3-116 Sources

For information on voltage sources in RFDE, refer to the Sources documentation.

Behavioral Source (bsource)

The behavioral source or bsource enables you to model a resistor, inductor, capacitor, voltage or current source as a behavioral component. This section describes the RFDE, ADSsim implementation of the bsource. Most of the information in this section is in addition to the Spectre documentation for bsource. The purpose of this section is to enable you to understand any potential differences between ADSsim and Spectre implementations.

For more information, refer to the Behavioral Source Use Model (bsource) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Bsource parameters

ADSsim supports all of the bsource parameters listed in the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41, June 2004. The only difference is in the capitalization of the parameter isnoisy. Both ADSsim and Spectre accept the parameter isNoisy. Except for the tnom parameter, all default values for ADSsim are consistent with Spectre.

pwr power

v vs

Table 3-63. Behavioral Source Parameters

Parameter Expression Description Default

Type r|g|l|phi|c|q simple_expr type of bsource component

v|i generic_expr

tnom value nominal temperature Options/25 degC

trise value temperature rise above circuit ambient 0

tc1 value linear temperature coefficient 0

tc2 value quadratic temperature coefficient 0

max_val value maximum value of bsource expression

min_val value minimum value of bsource expression

isNoisy flag - yes/no v|i|r|g types - flag to generate noise yes

Table 3-62. vsource DC Operating Point Parameter Mapping

Spectre ADSsim

Sources 3-117


Support for the temp Parameter

Spectre supports an undocumented temp parameter for the bsource component. ADSsim also supports this parameter for its bsource equivalent. If the parameter is not specified, then the global (ambient) temperature, as specified by the RFDE Options parameter Temp (default is 27 degrees Celcius), is used.

Interpretation of the trise Parameter

The standard behavior for ADSsim devices is that the parameter Trise takes effect only if the device parameter Temp is not specified. Then, the actual device temperature is the global circuit temperature (as defined by Options, or 25°C by default) modified by the value of Trise. Otherwise, if the device parameter Temp is specified, Trise is ignored even if a non-zero value is specified.

This behavior is different for bsource. Similarly to Spectre, the bsource parameter trise is always used to modify the device temperature, regardless of whether the reference temperature is defined by the undocumented bsource parameter temp or by the global circuit temperature.

Bsource Connection Nodes

If the bsource behavioral expression contains a reference to a voltage probe v(ni,nj), then the list of bsource connection nodes may be expanded by additional nodes. For example,

inst_name (n1 n2 [n3 n4 ...]) bsource type = expression_with_v(n3,n4)

However, simulation results in Spectre are expected to be the same regardless of whether these additional connection nodes are present or not. This behavior is preserved in ADSsim.

white_noise simple_expr v|i types - white noise expression

flicker_noise simple_expr v|i types - flicker noise expression

kf value r|g types - flicker noise coefficient 0

af value r|g types - flicker noise exponent 2

fexp value v|i|r|g types - flicker noise frequency exponent 1

m value multiplicity factor 1

Table 3-63. Behavioral Source Parameters

Parameter Expression Description Default

3-118 Sources

Bsource Hierarchical Nodes

The new Spectre front-end allows hierarchical nodes described by a relative path down from the current level of the hierarchy. These relative paths include the separator “.”. ADSsim does not support hierarchical nodes. This means that except for global nodes, both the connection nodes and the voltage probe nodes must be the nodes from the current subcircuit.

Bsource Current Probes

The new Spectre front-end allows any component to serve as a current probe. Similar to older versions of Spectre, ADSsim supports only a limited set of these components, basically all the components for which the current is calculated. These components include the ADSsim counterparts of the following Spectre components:

vsource, ccvs, pccvs, vcvs, pvcvs, iprobe, inductor

and three types of bsource:

l, phi, v

Limited Syntax for Referencing Current Probes

The new Spectre front-end enables you to specify the pin of the current probe component in the form:

i("component:index")

where index can be either the pin name or a corresponding numeric. Also, in the latest releases of Spectre, the quotes are optional.

In ADSsim, similar to the older versions of Spectre, the quotes are required and the index can only assume the value of 0 (zero, default in Spectre), which corresponds to the positive direction of the current through the component. It is recommended to not use the index at all, that is, use the following syntax only:

i("component")

If an index is specified, even it is set to zero, a warning message will be issued.

Bsource Current Probes Across the Circuit Hierarchy

The ADSsim bsource implementation does allow current probes from outside of the current subcircuit. However, this may potentially lead to inconsistent results between Spectre and ADSsim. This is because ADSsim treats the component path as relative

Sources 3-119


down from the current level of the hierarchy, while Spectre assumes that the component path is an absolute path from the top level circuit.

max_val and min_val Clipping

If both max_val and min_val bsource parameters are specified, then min_val is applied first. This means if the specified value of min_val is greater than max_val, the resulting expression value will settle at the value of max_val.

Temperature Scaling

As for Spectre, ADSsim temperature scaling is applied after the max_val and min_val clipping, if any is requested. This means that the actual final value may fall outside of the [min_val, max_val] range.

Differentiation and Integration operators

A differentiation operator ddt(simple_expr) and the integration operator idt(simple_expr) are allowed only within the generic bsource expression defining either the v or i type of the bsource. They are not allowed anywhere outside of the bsource component. Nested operators are not allowed.

The Scope of the Integration Operators

Similarly to the Spectre bsource, ADSsim bsource accepts only one field in the integration operator idt(simple_expr), that is the simple_expr to be integrated. The general Verilog-A syntax for the operator allows other fields, namely the initial condition, assert, nature and abstol. None of these are currently supported in bsource.

User-defined Functions

In general, ADSsim allows Spectre user-defined functions. However, their definition cannot include the probe functions v() and i(). The probe functions can only be used as arguments when the user-defined functions are actually used inside of bsource expressions. For example,

real myfunc( real x ) { return 50.0 + abs(x);}..mybs1 net1 net2 bsource r=myfunc( v(net1,net2) )

3-120 Sources

Spectre behavioral resistor, inductor and capacitor

A resistor, inductor, or capacitor in Spectre with main parameter r, l, and c, respectively, may be defined using behavioral expressions as shown here:

inst_name (n1 n2) resistor r = simple_expr parameters = expression_values

inst_name (n1 n2) inductor l = simple_expr parameters = expression_values

inst_name (n1 n2) capacitor c = simple_expr parameters = expression_values

If any of these components are defined using a behavioral expression, the ADSsim simulator, similar to Spectre, produces an equivalent bsource component:

inst_name (n1 n2) bsource r | l | c = simple_expr parameters = expression_values

For more information on the bsource model in Spectre, refer to Behavior Source (bsource) in Chapter 1 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

Cadence Provided LibrariesCadence Design Systems provides reference libraries that contain basic design objects that are available to use in your designs.

ahdlLib

The ahdlLib contains behavioral definitions for a large number of analog and digital primitives. These cells have not all been simulated in RF Design Environment. However, RFDE can utilize veriloga definitions, provided the veriloga license is available.

The crossing_detector is not supported in RFDE. This feature has an ahdl view, but no veriloga view. All other cells have a veriloga definition that can be utilized with RFDE.

Note Digital components simulated in frequency domain simulations may cause issues with convergence, or may be inaccurate if a suitable number of harmonics is not used in the simulation.

Cadence Provided Libraries 3-121


analogLib

The Cadence Analog Library (analogLib) is a standard component library provided within the Cadence Analog Design Environment. The library contains basic components such as resistors, capacitors, and transistors that can be used in building more complex analog blocks such as amplifiers.

Each component in analogLib can be supported by different simulators such as the ADSsim or Spectre simulators. Table 3-64 shows a list of components that are included in analogLib. If a component includes a Y in the Spectre-Compatible [Y/N]? column, then RFDE will be able to netlist and simulate the spectre view of this component. However, if a component includes an N in the Spectre-Compatible [Y/N]? column, then RFDE cannot netlist and simulate the spectre view.

For more information on Spectre-Compatiblity for each individual component in analogLib, refer to “Viewing Effective RFDE Library Compatibility for Library Cells” on page 2-4.

Table 3-64. analogLib Component Support

Component Name

Spectre-Compatible (Y/N)? Comments

bcs N

bvs N

cap Y

cccs Y

cccs4 n/a No spectre view for this component. The ads view is only available in the Agilent supplied analogLib.

ccvs Y

ccvs4 n/a No spectre view for this component. The ads view is only available in the Agilent supplied analogLib.

cmdmprobe N

core N

corefragment N

delay Y

diode Y

dummy N

fourier N

fourier2ch N

gnd Y

gnda Y

3-122 Cadence Provided Libraries

gndd Y

iam N

ibis_buffer N

idc Y

ideal_balun Y

iexp Y

ind Y

iopamp N

iprobe Y

ipulse Y

ipwl Y

ipwlf N

isffM N

isin Y

isource [type] Y* * If type = “piecewise linear file”, it is not Spectre-Compatible

ixfmr N

mind Y

MOS_a2d N

MOS_d2a N

msline N

mtline N

n1port Y

n2port Y

n3port Y

n4port Y

nbsim Y

nbsim4 Y

njfet Y

nmes Y

nmes4 N

nmos Y

nmos4 Y

nodeQuantity N


Component Name




noise N

npn Y

nport Y

nsoi N

pbsim Y

pbsim4 Y

pcapacitor Y

pcccs Y

pccvs Y

pdc Y

pdiode Y

pexp Y

pgen N

phyres N

pinductor Y

pjfet Y

pmind Y

pmos Y

pmos4 Y

pmsin N

pnp Y

port [type] Y* * If type = “piecewise linear file”, it is not Spectre-Compatible

powerSupply N

pppulse Y

ppwl Y

ppwlf N

presistor Y

psin Y

psoi N

pvccs Y

pvccs2 Y

pvccs3 Y

pvccsp N


Component Name



pvcvs Y

pvcvs2 Y

pvcvs3 Y

pvcvsp N

rcwireload N

res Y

scasubckt N

scccs N

sccvs N

schottky Y

scr N

sp1tswitch N

sp2tswitch N

sp3tswitch N

sp4tswitch N

svccs N

svcvs N

switch N

tline N

TTL_a2d N

TTL_d2a N

u1wire N

u2wire N

u3wire N

u4wire N

u5wire N

usernpn N

userpnp N

vam N

vcc Y

vcca Y

vccap N

vccd Y

vccs Y


Component Name




For more information on the Cadence analogLib, refer to the Cadence Analog Library Reference Guide.

vccsp N

vcres N

vcvs Y

vcvsp Y

vdc Y

vdd Y

vdda Y

vddd Y

vee Y

veea Y

veed Y

vexp Y

vpulse Y

vpwl Y

vpwlf N

vsffm N

vsin Y

vsource [type] Y* * If type = “piecewise linear file”, it is not Spectre-Compatible

vss Y

vssa Y

vssd Y

winding N

xfmr Y

zcccs Y

zccvs Y

zener Y

zvccs Y

zvcvs Y


Component Name



basic

The Cadence basic library (basic) contains schematic and symbol views of various connectors, pins, and supplies. The Cadence basic library is now 100% compatible with RFDE; therefore, an RFDE provided basic library is no longer required.

rfLib

The Cadence RF Library (rfLib) contains behavioral model components. These behavioral components are based on Verilog-A model files. The Cadence rfLib library components that use veriloga models are compatible with RFDE; however, components that use ahdl are not compatible with RFDE.

Third-Party LibrariesThe information provided in this section relates to spectre-language netlists that reference third-party device libraries such as MINT or UCM devices. The spectre-style convention for distinguishing NPN from PNP is to use a type={npn|pnp|n|p} parameter; however, the MINT-style equivalent is Gender={+1|-1}. Therefore, in the spectre-language translation layer, the software searches for the type parameter and converts it to the Gender parameter.

This generic translation rule is used to map the instance parameters listed in Table 3-65.

Table 3-65. Supported Third-Party Instance Parameters

spectre ADSsim

type=p Gender=-1

type=pnp Gender=-1

type=n Gender=+1

type=npn Gender=+1

mult Mult

l L

w W

Third-Party Libraries 3-127


This generic translation rule is used to map the model parameters listed in Table 3-66.

Case-Preferential Parameter Matching

Parameters in the simulator (i.e. device parameters, model parameters, subcircuit parameters) are not always required to match their definitions exactly. An exact match is always preferred; however, when an exact match is not found, a case-insensitive match is attempted. This case insensitive match helps with incorporating third-party spectre libraries.

For example, consider a subcircuit with one parameter, ABC. If there is a subcircuit instance with the parameter ABC, that is an exact match. If the instance instead has a parameter called abc, this would fail an exact match due to the difference in case. However, it will be matched up on the second pass, which is case-insensitive.

As a second example, consider a subcircuit with two parameters, ABC and Abc. If there is a subcircuit instance with parameter ABC, that is an exact match for the first defined parameter. If the instance instead has a parameter Abc, that is an exact match for the second defined parameter. However, if the instance instead has a parameter abc, that is ambiguous, and the simulator will issue an error.

Table 3-66. Supported Third-Party Model Parameters

spectre ADSsim

type=p Gender=-1

type=pnp Gender=-1

type=n Gender=+1

type=npn Gender=+1

3-128 Third-Party Libraries

Third-Party Libraries 3-129


3-130 Third-Party Libraries

Chapter 4: Compatible FeaturesThis chapter provides a detailed list of the Spectre-Compatible features that are supported by the ADS Analog/RF simulator (ADSsim) for use with Spectre-Compatible PDKs. The chapter highlights compatible features such as inline and nested sub-circuits, process mismatch, structural if-else, sectional includes, Boolean/algebraic expressions, Verilog-A support, etc. The chapter provides references to additional information in the RF Design Environment and/or Cadence documentation set where appropriate.

ExpressionsFor information on simulator functions in RFDE, refer to the Simulator Expressions documentation. For information on post processing functions in RFDE, refer to the Measurement Expressions documentation.

The tables provided in the sections below include various Spectre expression capabilities and their compatible ADSsim equivalents.

Note In Spectre-Compatibility mode, only the Spectre expression capabilities are valid. In native RFDE mode, only the ADSsim expression capabilities are valid.

For information on expressions in Spectre, refer to Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Operators

The operators listed in Table 4-1 are supported by the ADSsim simulator unless otherwise noted and are listed in order of decreasing precedence.

Table 4-1. Arithmetic and Boolean Operator Precedence

SpectreOperator

Spectre Symbol(s)

ADSsim Symbol(s) Value

Unary +,Unary -

+-

+-

Value of the operand, negative of the operand

To the power of ** **^

First operand to be raised to the power of the second operand

Expressions 4-1

Compatible Features

For more information, refer to the section on Expressions in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Multiply,Divide

* /

* /

Product, quotient of the operands

Binary Plus,Binary Minus

+-

+-

Sum, difference of the operands.

Shift <<>>

First operand shift by the number of bits specified by the second operand; first operand shifted right by the number of bits specified by the second operand.

Relational < <= >>=

< <= >>=

Less than,less than or equal to,greater than,greater than or equal to

Equality ==

!=

===equals

!=notequals

True if the operands are equal; true if the operands are not equal.

Bitwise AND & Bitwise AND (of integer operands)

Bitwise Exclusive NOR

~^(or ^~)

Bitwise exclusive NOR (of integer operands)

Bitwise OR | Bitwise OR (of integer operands)

Logical AND && &&and

True only if both operands are true.

Logical OR || ||or

True if either operand is true.

Conditional selection (cond) ? x : y (cond) ? x : y Returns x if cond is true, y if not; where x and y are expressions.

( ) Function call

[ ] Indexer, array

:: Sequence operatorwildcard

Table 4-1. Arithmetic and Boolean Operator Precedence (continued)

SpectreOperator

Spectre Symbol(s)

ADSsim Symbol(s) Value

4-2 Expressions

Algebraic and Trigonometric Functions

The ADSsim simulator in RF Design Environment supports all Spectre built-in algebraic and trigonometric simulator functions. There are only two functions whose names in ADSsim are different than in Spectre.

• The log(x) function in Spectre is equivalent to ln(x) in ADSsim

• The atan(x) function in Spectre is equivalent to arctan(x) in ADSsim

Table 4-2 displays a list of the algebraic and trigonometric simulator functions. Operands for the trigonometric and hyperbolic functions should be specified in radians.

Table 4-2. Built-in Algebraic and Trigonometric Simulator Functions

SpectreFunction

ADSsimFunction

FunctionDescription

FunctionDomain

log(x) ln(x) Natural logarithm X > 0

log10(x) log(x), log10(x) Decimal logarithm X > 0

exp(x) exp(x) Exponential x < 80 in Spectre, default to 60 and can be user specified in ADSsim

sqrt(x) sqrt(x) Square root x > 0

min(x,y) min(x,y) Minimum value All x, all y

max(x,y) max(x,y) Maximum value All x, all y

abs(x) abs(x) Absolute value All x

pow(x,y) pow(x,y) x to the power of y All x, all y

sin(x) sin(x) Sine All x

cos(x) cos(x) Cosine All x

tan(x) tan(x) Tangent All x, except x=n*(pi/2), where n odd

asin(x) asin(x) Arc-sine -1 <= x <= 1

acos(x) acos(x) Arc-cosine -1 <= x <= 1

atan(x) arctan(x) Arc-tangent All x

atan2(x,y) atan2(x,y) Arc-tangent of x/y All x, all y

hypot(x,y) hypot(x,y) sqrt(x*x+y*y) All x, all y

sinh(x) sinh(x) Hyperbolic sine All x

cosh(x) cosh(x) Hyperbolic cosine All x

tanh(x) tanh(x) Hyperbolic tangent All x

asinh(x) asinh(x) Arc_hyperbolic sine All x

acosh(x) acosh(x) Arc_hyperbolic cosine x

atanh(x) atanh(x) Arc_hyperbolic tangent -1 <= x <= 1

Expressions 4-3

Compatible Features

For more information, refer to the section on Expressions in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Expressions (expressions) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Built-in Constants

The Spectre netlist language contains built-in mathematical and physical constants. All Spectre built-constants are supported in RFDE.

For more information on built-in constants, refer to the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Built-in Mathematical and Physical Constants (constants) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

SubcircuitsSubcircuits are used to describe the circuit hierarchy and to perform parameterized modeling. You can nest subcircuits, and a subcircuit definition can contain both instances and definitions of other subcircuits.

For more information on subcircuits, refer to the section on Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Nested Subcircuits

Subcircuit definitions can be nested, in which case the inner-most subcircuit definition can only be referenced from within the subcircuit in which it is defined. The nested subcircuit cannot be referenced from anywhere else. Nested subcircuits define the functional scope for all of the possible references contained inside of a

int(x) int(x) Integer value of x All x

ceil(x) ceil(x) Smallest integer >= x All x

floor(x) floor(x) Largest integer <= x All x

fmod(x,y) fmod(x,y) Floating-point modulus All x, all y, except y=0

Table 4-2. Built-in Algebraic and Trigonometric Simulator Functions

SpectreFunction

ADSsimFunction

FunctionDescription

FunctionDomain

4-4 Subcircuits

subcircuit definition, for example, parameters, models, measurements, instances, sub-definitions, etc.

The RFDE solution provides equivalent results to the Spectre behavior with regard to nested subcircuits.

For more information, refer to the section on Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Inline Subcircuits

An inline subcircuit is a special case where one of the instantiated devices or models within the subcircuit does not get its full hierarchical name but inherits the subcircuit call name. The inline subcircuit is called in the same manner as a regular subcircuit.

RF Design Environment supports Spectre’s inline subcircuit behavior.

For more information, refer to the section on Inline Subcircuits in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Subcircuit Parameters

Parameters can be declared on the first line of a subcircuit definition. As a result, their default values are specified. The default values can be modified when creating subcircuit instances. The value or a default value for a parameter can be a constant, expression, a reference to a previously defined parameter (note that parameters must be declared before they are used), or any combination of these. The subcircuit definition or subcircuit instance inherit parameters from their parent (enclosing subcircuit definition, or top-level definition).

For more information on subcircuit parameters, refer to the section on Parameters Statement in Chapter 5 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See also Subcircuit Definitions (subckt) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Subcircuits 4-5

Compatible Features

Process Variation and MismatchProcess design kit users need to be able to run an ADSsim simulation in RF Design Environment and analyze a circuit that uses components from a Cadence PDK. Almost every process design kit includes the specifications for process and mismatch variations. These are used in Monte Carlo analysis to predict circuit performance due to process and/or mismatch variations. Support for Spectre’s syntax has been added for process and mismatch variations. Process and mismatch variations are defined in the model files.

Spectre’s process and mismatch variations functionality can be activated through the following RFDE Monte Carlo user interface analysis options:

Analysis Variations:

• Process Only

• Mismatch Only

• Process & Mismatch

For more information, refer to the section on Monte Carlo Analysis in Chapter 6 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The statistics Statement

The Spectre statistics control statement enables you to specify a batch-to-batch (process) and per-instance (mismatch) variations for netlist parameters.

The statistics statement is supported in RF Design Environment.

For more information on the Spectre statistics statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Structural if-elseThe structural if-else statement can be used to conditionally instantiate other instance statements. RF Design Environment supports Spectre’s structural if-else conditional instance.

For more information, refer to Conditional Instances under the Binning section of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41. See

4-6 Process Variation and Mismatch

also The Structural if-statement (if) in the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Sectional IncludesRF Design Environment supports Spectre’s sectional include statement in Spectre netlists. When the Spectre simulator reads the include statement in the netlist, the simulator locates the new file, reads it, and then resumes reading the netlist file.

For more information, refer to the section on Library - Sectional Include (library) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Special Character SupportBoth the Spectre and ADS Analog/RF (ADSsim) simulators assign special meaning to certain characters and words. RF Design Environment manages these special characters and reserved words in names from Spectre netlists so that it can provide equivalent Spectre behavior in ADSsim. This helps to avoid any undesired simulation results.

Note The dot, open parentheses, close parentheses, and pound characters in subcircuit, model, parameter, and node names in Spectre netlists are all mapped to the underscore ( _ ) character in the ADSsim simulator output files.

When the ADSsim simulator comes across a name in Spectre that happens to be a reserved word in ADSsim, the Spectre name is mapped using the following formula:

<Spectre_name> maps to _<Spectre_name>_ads

For example, the Spectre name logRforce, which happens to be a reserved word in ADSsim, would be mapped to _logRforce_ads.

. ( ) # all map to underscore ( _ )

Sectional Includes 4-7

Compatible Features

Special character support should be considered when interpreting error messages. Error messages may include modified names. For a similar example, refer to “Unsupported Parameters on Supported Devices” on page 5-1.

For more information on the ADSsim simulator reserved words, refer to Table 5-14 in Chapter 5 of the Using Circuit Simulators documentation.

Verilog-A Support (ahdl_include)The Spectre ahdl_include statement is used to include Verilog-A modules in your netlist. You can access Verilog-A files in RF Design Environment from Spectre netlists. Agilent’s Verilog-A compiler/interpreter is accessible from the RFDE Spectre parser. When the netlist is parsed, the Verilog-A filename is extracted and passed to the Verilog-A code. The Verilog-A code then manages all further operations.

For more information on Verilog-A, refer to Using Verilog-A in RF Design Environment and the Verilog-A Reference Manual.

See also Verilog-A Usage and Language Summary (veriloga) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Using Design VariablesDesign variables are netlisted in ads format only so all design variables in RFDE must use ads equation syntax only. If your design variables are setup to use Spectre equations, they must be modified to use ads equivalent equations in design variables in order for your design variables to netlist properly in RFDE.

4-8 Verilog-A Support (ahdl_include)

Chapter 5: Managing Unsupported FeaturesThis chapter provides information on identifying problems and known incompatible features, or features that are not supported for use in Spectre-Compatible PDKs.

Many incompatible features are described in detail in the RFDE and/or Cadence documentation set; therefore, references to additional information in the RF Design Environment documentation and/or Cadence documentation are provided where appropriate.

Identifying Unsupported FeaturesThis section includes information to help you identify and understand problems that you may encounter when attempting to use Agilent’s Spectre-Compatible solution with unsupported features.

Unsupported Parameters on Supported Devices

Supported devices are listed under “Supported Devices and Models” on page 3-4. Each of the supported devices and models includes a list of supported parameters and their mapping. If your device or model parameter is not listed in the Supported Devices and Models section, the component or model should be considered unsupported.

When you encounter an unsupported parameter in a device that is known to be supported, you will receive an error message. Error messages may initially be confusing due to aliasing and parameter mapping. For example, consider the message below:

hpeesofsim (*) 2005A.day May 25 2005 (built: 05/25/05 21:46:44)Copyright Agilent Technologies, 1989-2005.

Warning detected by hpeesofsim during netlist flattening. parameter dtoxcv for mosfet model nmos25 is not currently supported.

Warning detected by hpeesofsim during netlist flattening. parameter dtoxcv for mosfet model pmos25 is not currently supported.Warning: parameter va for BJT model npn is not currently supported.Warning: parameter va for BJT model pnp is not currently supported.Warning: parameter pbsw for Diode model I3.I9.R1.R1.polyhres.polyhreslw_diode is not currently supported

Warning detected by hpeesofsim during netlist flattening Instance ‘polyhreslw’: ‘Length’ is not a valid parameter for an instance of ‘R’. Ignoring it.

Warning detected by hpeesofsim during netlist flattening. Instance ‘polyhreslw’:

Identifying Unsupported Features 5-1

Managing Unsupported Features

Width’ is not a valid parameter for an instance of ‘R’. Ignoring it.

Error detected by hpeesofsim during netlist flattening. Undefined parameter ‘trise’ used by ‘I3.I9.R1.R1.Trise’.

Warning: parameter pbsw for Diode modelI3.I9.R1.R0.polyhres.polyhreslw_diode is not currently supported.Flushing data (please wait) ...

Resource usage: Total stopwatch time: 0.45 seconds.

hpeesofsim terminated due to an error.ds2psf--ERROR: Cannot access file /users/johnqp/CadenceGPDK/rfic217a/design/simulation/sim_G7VCO/ADSsim/schematic/netlist/data.ds.

Note that the “Error detected by hpeesofsim during netlist flattening” reports “Undefined parameter ‘trise’ used by ‘I3.I9.R1.R1.Trise’.” You can use the information provided in the error message to work backwards and decipher the specific problem.

In this case, you can see that the this is a resistor instance (R1) is using the Trise parameter. Because Trise uses initial capitalization, you can quickly identify this as an ADSsim parameter (Spectre parameters do not use initial capitalization). Using this information, you can return to the information on the “Resistor” on page 3-5 and use Table 3-2 (the resistor instance mapping table) to identify the equivalent Spectre parameter, trise in this case. Spectre’s trise parameter maps to the RFDE equivalent Trise. Once you find the equivalent parameter that you are looking for, you can use the tools described in “Generating Debugging Output” on page 5-3.

The error message above is fairly straight forward; however, some error messages can be difficult to decipher due to parameter aliasing. If a Spectre parameter is actually an alias for another parameter, the process of understanding the parameter mapping can quickly become less straightforward.

Take the time you need to understand the mapping before proceeding to the next section.

5-2 Identifying Unsupported Features

Generating Debugging Output

ADSsim provides a method for dumping the internal data structures that make up a circuit in a form that looks like an ADSsim netlist. This is a flattened (all subcircuits expanded, no hierarchy) version of the simulated netlist with all instances, flattened node numbers, and models. Instance and model parameters are printed with the numerical value that was used in the simulation; this provides a good way to determine how expressions that may be used to define model parameters are actually evaluated. The netlist is printed after DC simulation is finished, so some simulation controller must be present in the netlist.

Insert the following line in the circuit netlist:

Options DumpFile="dumpfile.txt" DumpLevel=288

DumpFile is the name of the file that will be created to hold the output. Any existing file is overwritten without warning.

DumpLevel should be set to one of two values:

• DumpLevel=256 - Print a flattened netlist with all instances and models; only those parameters specified in the input netlist are printed.

• DumpLevel=512 - Print a flattened netlist with all instances and models; all readable parameters are printed; parameters that weren’t specified in the input netlist have their default values printed.

There are a number of options to DumpLevel that are available. They can be activated by adding the values described in Table 5-1 to the primary DumpLevel.

Instances and models that are secured (either from an encrypted library or via the Secured parameter) do not have their nodes and parameters printed. There are some instance and model parameters that are not printed. Indexed and repeated parameters are currently not printed (e.g. SDD I[1,0]).

Table 5-1. DumpLevel Options

Value Description

+1 Print numbers in engineering format with unit strings (Slew=25.6 MV/s); the default is scientific format (Slew=2.56e+07).

+8 Print one parameter per line; the default is to print as many parameters as fit in an 80 character line.

+16 Print all aliases for parameters (e.g. Tnom=25 Tref=25); by default only one aliased parameter name is printed.

+32 Print parameters that default to zero; normally default values of zero are not printed.

Identifying Unsupported Features 5-3


You can use the Simulation File Setup form to point to a file that includes the DumpFile and DumpLevel command options. To use the Simulation File Setup form instead of editing the netlist directly,

1. Save the following line in a file named something like DumpOutput.txt.

Options DumpFile="dumpfile.txt" DumpLevel=288

Ensure the permissions on the file will allow the software to execute the file.

2. From the Analog Design Environment window, choose Setup > Simulation Files. The Simulation File Setup form appears.

3. Enter the path to the DumpOutput.txt file in the Include Path field.

4. Enter the name of your file, DumpOutput.txt in this case, in the Definition Files field.

5. Click OK and then run your simulation.

When your simulation runs, the DumpOutput.txt file will be included in your netlist and the flattened output will be sent to the dumpfile.txt file, or whatever you had defined the output file to be.

For more information on Simulation File Setup, refer to Setting Up Simulation Files for Direct Simulation in Chapter 2 of the Cadence Virtuoso Analog Design Environment User Guide, Product Version 5.1.41.

Incompatible FeaturesThis section includes information on known incompatible features.

In some cases, it may not be clear if a feature is unsupported or you may encounter a difficult problem that is not documented in this manual. In this case, you may find helpful information to address your particular problem on the Agilent EEsof EDA Knowledge Center. You can access the Knowledge Center from the Agilent EEsof EDA Web site at:

http://www.agilent.com/find/eesof-knowledgecenter/

Spectre Analyses

Spectre Analyses are not supported by RFDE. If the simulator encounters a Spectre Analysis statement in the netlist, a warning message similar to the following will be reported:

5-4 Incompatible Features

Warning detected by hpeesofsim during netlist parsing. Skipping instance `dc1' of type `dc'.

For more information on Spectre Analyses, refer to Chapter 6: Analyses in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Case Insensitivity

The Spectre simulator line includes an optional parameter to disable case sensitivity. This option is not supported by RFDE. If the simulator encounters a Spectre insensitive parameter in the netlist, the parameter will be ignored.

simulator lang=spectre insensitive=yes

Spectre Control Statements

The Spectre circuit simulator includes multiple control statements that can be sequenced in a Spectre netlist. Many of these control statements are not supported by RF Design Environment. The information below will help you understand some of the issues related to these control statements and how you might work around a particular situation.

The alter and altergroup Statements

The Spectre alter statement is used to modify individual parameters for devices, models, circuit, and subcircuit parameters during a simulation. The Spectre altergroup statement is used to change model file parameters by listing the device, model, and circuit parameter statements as you would in the main netlist.

The alter and altergroup statements are not supported in RF Design Environment. If the simulator encounters a Spectre alter statement in the netlist, a warning message is reported and the statement is ignored.

If the simulator encounters a Spectre altergroup statement in the netlist, an error message is reported and the simulation is terminated.

For more information on the Spectre alter and altergroup statements, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Incompatible Features 5-5


The assert Statement

The Spectre assert statement enables you to set custom checks to determine the safe operating area of your circuit.

The assert statement is not supported in RF Design Environment. If the simulator encounters a Spectre assert statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre assert statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The check Statement

The Spectre check statement enables you to perform a check analysis at any point in a simulation to be sure that the values of component parameters are reasonable.

The check statement is not supported in RF Design Environment. If the simulator encounters a Spectre check statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre check statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The checklimit Statement

The Spectre checklimit statement enables you to enable or disable an assert or group of asserts.

The checklimit statement is not supported in RF Design Environment. If the simulator encounters a Spectre checklimit statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre checklimit statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The ic and nodeset Statements

The Spectre ic and nodeset statements enable you to provide state information to DC and transient analyses.


The ic and nodeset statements are not supported in RF Design Environment. If the simulator encounters a Spectre ic or nodeset statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre ic and nodeset statements, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The info Statement

The Spectre info statement is used to generate lists of component parameter values. The info statement enables you to access the values of input, output, and operating-point parameters in Spectre and print a capacitance table.

The info statement is not supported in RF Design Environment. If the simulator encounters a Spectre info statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre info statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The options Statement

The Spectre options statement enables you to enter initial parameters for your simulation that you do not specify in your environment variables or on your command line.

The options statement is not supported in RF Design Environment. If the simulator encounters a Spectre options statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre options statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The paramset Statement

The Spectre paramset statement enables you to specify a list of parameters and their values for the sweep analysis.

The paramset statement is not supported in RF Design Environment. If the simulator encounters a Spectre paramset statement in the netlist, a warning message is reported and the statement is ignored.



For more information on the Spectre paramset statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The save Statement

The Spectre save statement enables you to save signals for individual nodes and components or save groups of signals.

The save statement is not supported in RF Design Environment. If the simulator encounters a Spectre save statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre save statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The set Statement

The Spectre set statement enables you to modify any options statement parameters you set at the beginning of the netlist, with the exception of temperature parameters and scaling factors.

The set statement is not supported in RF Design Environment. If the simulator encounters a Spectre set statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre set statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

The shell Statement

The Spectre shell statement enables you to pass a command given in a SHELL environment variable to the operating system command interpreter.

The shell statement is not supported in RF Design Environment. If the simulator encounters a Spectre shell statement in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre shell statement, refer to Chapter 7: Control Statements in the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.


The paramtest Component

The Spectre paramtest component enables you to test the value of subcircuit parameters.

The paramtest component is not supported in RF Design Environment. If the simulator encounters a Spectre paramtest component in the netlist, a warning message is reported and the statement is ignored.

For more information on the Spectre paramtest component, refer to Range Checking on Subcircuit Parameters in Chapter 13 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Model Scale Factor (scalem)

The Spectre model scale factor (scalem) capability is used to set scaling factors for model parameters. The scalem feature is not supported by RF Design Environment and there is no equivalent model scale factor in RFDE. The model scale factor is specified in the Spectre options statement. If a scalem statement is encountered, a warning message is generated and the options statement is ignored.

For more information on scalem, refer to Scaling Factors (scale and scalem) in Chapter 3 of the Cadence Virtuoso Spectre Circuit Simulator Components and Device Models Manual, Product Version 5.1.41.

Missing Devices and Models

Supported devices and models are listed under “Supported Devices and Models” on page 3-4. If your device or model is not listed in the Supported Devices and Models section, the component or model should be considered unsupported.

Spectre High-Level Description Language (HDL)

The Spectre High-Level Description Language (HDL) is a language that uses functional description text files (modules) to model the behavior of electrical circuits and other systems.

Spectre HDL is not supported in RF Design Environment; however, RFDE does support Verilog-A models. Therefore, if you have a Spectre HDL model that you want to use, the recommendation is to convert your Spectre HDL model to a Verilog-A model. If you attempt to netlist an HDL module, an error will be generated.



For more information on Spectre HDL, refer to the Cadence SpectreHDL Reference, Product Version 5.0.

For more information on Verilog-A, refer to Using Verilog-A in RF Design Environment and the Verilog-A Reference Manual.

See also Verilog-A Usage and Language Summary (veriloga) in Chapter 4 of the Cadence Virtuoso Spectre Circuit Simulator Reference, Product Version 5.1.41.

Cadence Compiled-Model Interface (CMI)

Custom models created using Cadence Compiled-Model Interface (CMI) are not supported in RFDE. If a CMI model is encountered, an error will be generated.

RFDE does however support user-defined models. In order to use CMI, the recommendation is to convert your CMI models to RFDE user-defined models or Verilog-A models.

For more information on Verilog-A models, refer to the RFDE Verilog-A documentation in the Simulation and Optimization section of your RFDE documentation set.

For more information on user-defined models, refer to the Advanced Design System User-Defined Models documentation in the ADS Model Development section. The ADS documentation set can be accessed from the Agilent EEsof EDA Web site at:


Spectre Encryption

RFDE cannot simulate models that have been encrypted by Spectre. If a Spectre encrypted model is encountered, an error will be generated.

If you have a Spectre encrypted model that you would like to use, you will need to acquire an un-encrypted version of the Spectre model.

SPICE Format Compatibility

Using simulator lang=<mode>, you can specify a language mode for subsequent statements. Spectre supports the simulator lang=spice statement; however, if RFDE encounters the simulator lang=spice statement, it will not be able to parse anything other than comments, blank lines, and other simulator lang=<mode> statements. Any other SPICE statements will generate error messages.


If you have a file that is compatible with Spectre and includes a mix of Spectre and SPICE syntax, you can use the Spectre Pre-Parser (SPP) command (spectrespp) from the Cadence directory to enable the SPICE Reader and output the file so that it is 100% Spectre syntax. The recommendation is to use the spectrespp command to output a 100% Spectre syntax file and then use that file with RF Design Environment.

For more information on the running the SPICE Reader, refer to SPICE Compatibility in Chapter 3 of the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Alternatively, you can translate a 100% SPICE netlist using the nettrans command to convert your SPICE netlist into an ads netlist. The issue here is that the netlist must be 100% SPICE syntax. The nettrans command will not accept a netlist with a mix of Spectre and SPICE syntax.

For more information on the nettrans command, refer to the Advanced Design System Netlist Translator for SPICE and Spectre documentation. You can access this documentation from the Agilent EEsof EDA Web site at:




Error Handling

When a syntax error (including an unknown feature) is encountered by the system, an error is reported to the user. Any simulation that attempts to netlist an unsupported format will generate a syntax error. In general, any time the simulator encounters an error, the simulation will be terminated.

For more information on error messages that may be generated, refer to “Identifying Unsupported Features” on page 5-1. See also the Agilent EEsof EDA Knowledge Center for the latest up-to-date information.


Chapter 6: The RFDE NetlisterThis chapter provides information on the RFDE Netlister. The chapter covers information on the following topics:

• “Instance Netlisting” on page 6-2

• “Basic Spectre Formatting” on page 6-2

• “Instance Name Mapping” on page 6-3

• “Node Name Mapping” on page 6-3

• “Adding Instance Pins for pinMapping” on page 6-3

• “Subcircuit Netlisting” on page 6-4

• “Scoping Rules” on page 6-4

• “Verilog-A Netlisting” on page 6-5

• “Include Files” on page 6-5

• “Default Switch and Stop View Lists, Hierarchy Editor” on page 6-6

• “Error Messages” on page 6-6

• “Alias Warning Messages” on page 6-7

• “Backward Compatibility” on page 6-7

A netlister is used to create a text based representation of a circuit database. The format of the netlist is specific to the tool that will use it. It is a tried and true method of passing information from one tool to another, and the format of the netlist provides a basis for the two tools to understand one another. Typically, this is used by a database tool, such as Cadence’s schematic environment, to talk to a simulator such as Cadence’s Spectre or Agilent’s ADSsim in RFDE.

Cadence requires that a library be set up to create a proper netlist for a simulator. Multiple simulators can be set up for a particular component in a library; however, each of these setups can take time and require a resource to perform verification of the setups. Setup also requires specific knowledge of specific simulator components and simulator syntax.

Agilent EEsof EDA now provides a product that operates with Cadence library components that are setup to work with the Cadence Spectre netlister. The RFDE netlister has been updated so that it can switch between using the RFDE native formatter and the Spectre formatter. The net result of this is that little or no RFDE

6-1

The RFDE Netlister

specific setup in addition to existing Spectre setup is required. The RFDE user interface has also been enhanced so that you can specify Spectre model files from a PDK to have them read in by the ADSsim simulator properly.

Instance NetlistingInstances can be netlisted in either RFDE native format or in Spectre format. To enable this, several functions have been modified. Control over the formatting is determined by the stop view that is encountered, and upon user definable compatibility setups. When an ads stop view is encountered, the netlister will choose to format the instance using the existing RFDE native formatter. If the stop view is not ads, the software will check to see if the component has been marked as being incompatible with RFDE’s Spectre-Compatibility. If the component is determined to be incompatible, the RFDE formatter will be used; if there is no ads tool setup, this will result in a netlisting error. If the component is determined to be compatible, the Spectre formatter will be used to output the instance. A simulator lang=spectre or simulator lang=ads line will be output as necessary, depending on whether spectre or ads format is being utilized.

Basic Spectre FormattingTo specify a component in Spectre, you need to use an instance statement. The example below shows the general format for a Spectre instance statement.

name (node1...nodeN) type [param1=value1...paramN=valueN]

where

name is the component name you supply for the instance statement.

node1...nodeN are the pin names for each node of the component.

type is the name of a built-in primitive (such as a resistor), a model, a subcircuit, or an AHDL module.

param1=value1...paramN=valueN are used to specify parameter values for your component.

All functions called during Spectre formatting come from the Spectre formatter. Custom netlist functions should be written for the Spectre formatter. The Spectre simInfo is utilized to determine formatting. In

6-2 Instance Netlisting

s where a viewInfo exists, the viewInfo is assumed to be set up for the Spectre formatter, not the ads formatter. If no netlisting function is specified, the nlPrintInst function from the Spectre formatter is used to format the instance. For custom netlisting functions, the formatter passed to the function will be of the spectreFormatter class, not the adsFormatter class. All calls will be scoped based on using the spectreFormatter.

For more information, refer to the Cadence Virtuoso Spectre Circuit Simulator User Guide, Product Version 5.1.41.

Instance Name MappingAll instance name mappings are stored in the netlist/amap directory. RFDE is compatible with OASIS, and utilizes identical files to Spectre. When Spectre mapping is used, the map and amap directories are created under the ADSsim tool directory for the cell, and can be used directly by RFDE for back annotation. In cases where the name is mapped, nlGetSimName will return the Spectre mapped name.

Note Instance mapping will affect measurement equation generation. Measurement equations may need to be manually set up to account for the netlisting mapping.

Node Name MappingNode names are mapped based on the ADSsim reserved word rules and node name rules. This is to ensure that node names within ADS and Spectre sections will be identical. The Spectre formatter is altered after it is created so that the Spectre mapping rules are replaced with the ADSsim mapping rules.

Adding Instance Pins for pinMappingFor storage of pin currents, the netlisting code has been set up to automatically add the proper pinMapping information to the session in the function nlSetCurrentInstance. In previous releases, it was necessary to call rfdeNetlistPinMapping_addInstance( _inst ) in a custom netlisting function to get the pin mapping data added. This is no longer required.

Instance Name Mapping 6-3

The RFDE Netlister

Subcircuit NetlistingBecause of potential scoping rule differences, the mode that a subcircuit is netlisted in can affect the final outcome. This is a rare situation; however, to ensure compatibility, it is still possible to have RFDE netlist a subcircuit in Spectre mode. To do this, you must explicitly add Spectre compatibility to your user-defined compatibility file for the library containing your subcircuits. If this is done, the Spectre formatter will be used to output the subcircuit header, parameters, and footer. If nothing is set, the existing RFDE formatter is used to output the subcircuit header, parameters, and footer in native RFDE format.

Example

The following is an example of Spectre subcircuit output.

simulation lang=spectresubckt name ( node1 ... nodeN )parameters param1= ... paramN=...ends name

Scoping RulesThe process of name resolution is slightly different for ADSsim-language subcircuits versus Spectre-language subcircuits. The language of a subcircuit, and therefore the scoping rules used by that subcircuit, follow from the language used for the subcircuit header. For example:

simulator lang=ads define mysubckt1 [...] end mysubckt1 simulator lang=spectre subckt mysubckt2 [...] ends mysubckt2

For evaluating references in expressions, both Spectre-language and ADSsim-language subcircuits use dynamic scoping rules, which resolve a name by searching upward through the instantiation hierarchy. This is consistent with how the Spectre simulator behaves.

6-4 Subcircuit Netlisting

For locating a component type, an ADSsim-language subcircuit uses dynamic scoping rules, and a Spectre-language subcircuit uses static scoping rules. Static scoping looks upward through the definition hierarchy, rather than the instantiation hierarchy.

Note The component type referred to above is the model or subcircuit used to instantiate the instance. In ADSsim syntax, it is the name on the left side of the colon. In Spectre syntax, it is the last name given before the list of parameters begins.

This example shows that it is possible to construct a case where the behavior of a subcircuit may depend on whether static scoping rules or dynamic scoping rules are used. Construction of such a problem requires that at least one subcircuit contain a model definition or a nested subcircuit. A netlist without such nested definitions is not subject to any scoping problems of this sort. This problem also requires that the same name be used for differing component types, in different parts of the netlist. The easiest way to be free from worry about this problem is to use unique names for models and subcircuits.

Note If you depend on scoping rules and use ambiguous names for component types to avoid simulation problems, you are likely to confuse your foundry kit users. It is highly recommended that you use unique names and avoid relying on particular scoping rules.

Verilog-A NetlistingComponents that are set up to utilize veriloga using viewInfo setups will use the RFDE native formatter, unless the component is explicitly set up to be listed as compatible with RFDE Spectre-Compatibility.

Include FilesThe model include, definition, and stimulus files will all be checked for netlist format. The following rules apply:

• If the file ends with a .scs suffix, it is assumed to be a Spectre syntax file. The file will be output using Spectre include/section syntax.

Verilog-A Netlisting 6-5

The RFDE Netlister

• If the file ends with a .een suffix, it is assumed to be an EEsof netlist, and will be output with the existing #define/#include syntax for backward compatibility.

• If the file does not end with either of the above suffixes, the file will be opened and parsed. If a simulator lang=spectre line is found, the file is assumed to be a Spectre syntax file, and is output using Spectre include/section syntax.

• If the file does not have a simulator lang=spectre line, or if non-comment lines are found prior to encountering a simulator lang=spectre line, the file is assumed to be RFDE native syntax, and the existing #define/#include syntax is output.

Note If a non-Spectre or non-RFDE file is included (e.g. an hspice netlist), it will still be output and included as RFDE syntax. This will cause a syntax error in the simulator.

Default Switch and Stop View Lists, Hierarchy EditorThe RFDE environment files have been updated to add spectre to the default switch and stop view lists for ADSsim. In addition, spectre has been added to the ads template for the Hierarchy Editor. In the event that an existing state that stored environment settings is loaded, you will need to add spectre to the switch and stop view list in order to use it. If an existing Hierarchy Editor config file is opened, you will need to add spectre to the switch and stop view lists manually.

For more information on the Hierarchy Editor, refer to the Cadence Hierarchy Editor User Guide, Product Version 5.1.41.

Error MessagesThe following example errors are specific to Spectre-Compatibility:

Spectre view not added to the switch view list and stop view list for a compatibility enabled library.

Spectre simInfo does not exist for a compatibility enabled library.

Bad simulation results obtained due to scoping differences between Spectre and RFDE.

Model file specified with Spectre library and sections that include other files, but the file does not have a .scs extension.

ads stop view and simInfo not added to a library that will not be used in compatibility mode.

6-6 Default Switch and Stop View Lists, Hierarchy Editor

OASIS traps numerous error conditions; however, these error messages cannot be readily trapped and overridden in RF Design Environment. There are also numerous issues that can relate to mis-configuring your PDK setup for Spectre. For example, specifying a non-existent netlisting function for Spectre. These are not covered here, the netlister assumes that a PDK is properly configured and installed to work with Spectre.

Alias Warning MessagesThis section provides information on how to interpret simulator warning messages generated by RFDE and what actions you need to take to understand the issue when these messages appear.

Incompatible Spectre Definition

Warning!: The spectre definition for the cell <cell> in the library <library> is not compatible with RFDE.

The ads definition will be used instead.

This warning is issued if there is an ads definition available to use for netlisting. If there is no definition available, an alternate error message is generated:

Error!: The spectre definition for the cell <cell> in the library <library> is not compatible with RFDE.

There is no ads definition for the cell, this component cannot be netlisted.

In the error condition above, there will additionally be an OASIS generated error message that specifies that a master could not be found for the instance.

All other errors and warnings are generated by OASIS.

Backward CompatibilityAll components that have been set up to work with RFDE in prior releases will continue to be output identically in the current release, provided the component is set up to be netlisted in RFDE native mode. RFDE native mode is the default netlisting mode. RFDE native mode will be used for a component if an ads stop view is encountered, or if the component is not listed as being Spectre-Compatible in one of the compatibility setup files.

Alias Warning Messages 6-7

The RFDE Netlister

6-8 Backward Compatibility

Chapter 7: Spectre-Compatible Process Design Kit VerificationThis chapter describes how to compare Spectre and RFDE results using the Cadence Results Browser, DC annotation, and DC operating points through the Cadence environment.

Setting Up and Running a SimulationBefore comparing your results, you will need to perform a simulation on your design using both Spectre and RF Design Environment. Note that your RFDE output data must be translated into Cadence’s native data format, parameter storage format (PSF), in order for you to compare your results in the Cadence Results Browser. The procedure below will guide you through setting up and running your simulation.

1. Open your design by choosing File > Open from the CIW. Use the Open File form to open the schematic window with your design.

2. From the schematic window, choose Tools > Analog Environment. The Cadence Analog Design Environment window appears.

3. Setup the Analog Design Environment for your Spectre simulation by selecting the spectre simulator.

4. From the Cadence CIW, choose File > Open. Use the Open File form to open a new schematic window with your design.

Note Be aware that when you make a change in one schematic window, the other window will automatically update with the change you made in the first window. You may want to save a backup copy of your design using the Design > Save As menu item in the schematic window. You can name your backup design something like <schematic_name>_original.

5. Setup the Analog Design Environment for your RFDE simulation by selecting the ADSsim simulator.

6. In the Analog Design Environment window for your RFDE simulation, choose Results > Data Display Options. The Data Display Options form appears.

Setting Up and Running a Simulation 7-1

Spectre-Compatible Process Design Kit Verification

7. Enable the Translate Results to PSF option in the Data Display Options form and click OK.

This will ensure that your output is saved as PSF and enable you to view and compare your data in the Cadence Results Browser.

8. Run a simulation on both the Spectre and RFDE setups. After your simulations have completed successfully, you will be able to compare your results in the Cadence Results Browser.

Using the Results BrowserThis section briefly describes how to launch the Cadence Results Browser and view your results from multiple simulations.

The Results Browser is a standalone front-end to the Cadence Waveform Viewer. The tool enables you to send plots to a graph, a table, or to the Cadence Calculator. The prerequisite is that your RFDE output data is translated into PSF.

For a tutorial on using the Cadence Results Browser stand-alone, refer to Chapter 2 of the Cadence WaveScan Tutorial, Product Version 5.1.41.

To verify your results using the Results Browser from RF Design Environment,

1. Access the Analog Design Environment (ADE) window.

2. Choose Tools > Results Browser. The Results Browser window appears.

7-2 Using the Results Browser

You will notice that the PSF directory output names from Cadence are different from the PSF output names for RFDE. This is due to data format differences between Agilent’s Data Display and Cadence’s Spectre. Generally speaking, Cadence provides names that are doubled-up for the simulation that was run. For example, dc-dc (for a DC simulation), sp-sp (for an S-parameter simulation), etc. Results with these types of names will contain swept data. RFDE results, especially for sweeps, typically have a sweep name in the directory name. For example, a DC sweep will be output into something like srcSweep, as opposed to dc-dc. Refer to Table 7-1 for several examples.

Table 7-1. Example PSF Output Directory Names

Spectre Directory Name RFDE Directory Name

dc-dc srcSweep

dcOpdc dcOp-dc

sp-sp sp-sp

variables variables

Using the Results Browser 7-3


Note If you are using the Cadence Calculator, various expressions will not gather the data properly. A large number of Cadence functions default to Spectre-specific data names (e.g. aaSp will look in sp-sp). To obtain the data from RFDE, you can use the getData() function. For example, to get the result of S[1,1] from RFDE, use the command getData("S[1,1]" ?result "sp-sp"). If you use the built in calculate aaSp() function, it will return nil and generate error messages. Some operations in the Cadence Calculator will work, while others will not. You may need to manually insert and use the getData() function in order for the Calculator to operate properly.

To run Spectre and RFDE simultaneously, you must open two separate schematics as described in “Setting Up and Running a Simulation” on page 7-1. This is because each schematic window is associated with a particular session. When you have two schematic windows open, both editing the same design, each window can be associated to a distinct ADE session. This enables you to make changes in one window, but run the simulations in both, the Cadence schematic windows are linked, changes in one are immediately reflected in the other.

Annotating DC ResultsThis section describes how to annotate DC results for multiple simulators and also how to view currents instead of voltages. Ensure you have saved your annotation data in RFDE before attempting to view the results. For information on Saving Annotation Data in RFDE, refer to the DC Simulation Results section of the DC Simulation documentation.

Annotating DC Voltages

After running a simulation, you can annotate DC Voltages on your schematic design by choosing the Results > Annotation > DC Node Voltages menu option in the Analog Design Environment window. Notice that there is no DC Currents option in the menu selection. For more information on DC currents, refer to “Annotating DC Currents” on page 7-5.

DC voltages only depend on the node name, there is no dependence on Spectre-Compatibility mode. If you are not seeing annotated results, it probably means one of three things:

7-4 Annotating DC Results

• The data was not saved. For information on Saving Annotation Data in RFDE, refer to the DC Simulation Results section of the DC Simulation documentation.

• There was an unresolved mapping issue.

• There is no interpreted label to display the annotation. When you choose to annotate DC node voltages, the DC voltage for the nodes are displayed on the schematic. The schematic will only display DC node voltages for components where an interpreted label is available. Note that most user-created schematics use the Design > Create Cellview > From Cellview menu option, and that the default digital mode does not create interpreted labels on the terminals. This results in the node voltages not being reported in the schematic.

Note To view DC Voltage annotation, you must be zoomed in enough to see the displayed annotation. In order to speed up rendering, Cadence does not display the interpreted labels unless you are zoomed in past a certain zoom point. Use the Window > Zoom options in the schematic window to view your results.

Annotating DC Currents

To display DC currents, you must access the Edit Component Display Options form from the schematic window. To display DC currents on the schematic,

1. Run your simulation.

Ensure you have saved your annotation data in RFDE before attempting to view the results. For information on Saving Annotation Data in RFDE, refer to the DC Simulation Results section of the DC Simulation documentation.

2. In the schematic window, choose Edit > Component Display.

The Edit Component Display Options form appears.

3. Click the terminal Select Label option and then click a component in the schematic.

The Edit Component Display Options form is modified for the component.

4. Set the Terminal Labels option to display DC current and click OK.

If you have multiple schematic windows open, both windows will be updated with the DC results if you use the Analog Design Environment window. You must use the

Annotating DC Results 7-5


Component Display Options form, and use the Results > Select menu item to access the Select Results form to get both windows to display different DC operating points. This will need to be done for each re-simulation.

Displaying DC Operating PointsThis section describes how to view DC operating point results and change the operating points being displayed.

To display DC operating points,

1. Run your simulation.

Ensure you have saved your annotation data in RFDE before attempting to view the results. For information on Saving Annotation Data in RFDE, refer to the DC Simulation Results section of the DC Simulation documentation.

2. From the Analog Design Environment window, choose Results > Annotate > DC Operating Points.

This will use the Spectre operating point annotation, unless the operating point label set is already setup to use the RFDE outputs. It will additionally map operating point expressions.

To change the operating point being shown,

1. Choose Edit > Component Display.

The Edit Component Display Options form appears.

2. Click the parameter Select Label option.

3. Set the Parameter Labels to display operating points DC and click OK.

A cyclic list appears that will enable you to change the operating points being displayed.

As with DC voltages and currents, the operating point display will update multiple schematics if you have them open. You need to use the Component Display Options form and Select Results options to have each schematic display results from a different simulator. This will need to be done for each re-simulation.

7-6 Displaying DC Operating Points

Index
Aadministrative tasks, 2-1ADSsim, 1-3
mapping rules, 6-3ahdl_include, 4-8alter and altergroup control statements, 5-5analyses

Monte Carlo, 4-6annotating DC results, 7-4assert control statement, 5-6

Bback annotation, 6-3backward compatibility, 1-6, 6-7behavioral expressions, 3-122behavioral source, 3-118built-in constants, 4-4

CCadence

Calculator, 7-2, 7-4Hierarchy Editor, 6-6OASIS, 6-3, 6-7Results Browser, 7-2Waveform Viewer, 7-2website address, 1-7

Calculator, 7-2, 7-4case-preferential

parameter matching, 3-129check control statement, 5-6checklimit control statement, 5-6classes

adsFormatter, 6-3spectreFormatter, 6-3

close parentheses character, 4-7CMI, 5-10commands

spectrespp, 5-11comparing results, 7-1compatible features, 4-1components

backward compatibility, 6-7connection nodes

bsource, 3-119control statements, 5-5

alter and altergroup, 5-5assert, 5-6check, 5-6checklimit, 5-6ic and nodeset, 5-6info, 5-7options, 5-7paramset, 5-7save, 5-8set, 5-8shell, 5-8statistics, 4-6

crossing_detector, 3-122current probes

bsource, 3-120

DDC currents, 7-5DC operating point, 7-1, 7-6

bht, 3-29bjt, 3-24bjt503, 3-33bjt504, 3-37bjtst, 3-44bsim3v3, 3-65bsim4, 3-88capacitor, 3-8diode, 3-15inductor, 3-10isource, 3-117jfet, 3-116juncap, 3-17mos1, 3-93mos2, 3-98mos3, 3-104mos902, 3-109mos903, 3-113resistor, 3-6vbic, 3-49vsource, 3-117

DC Voltages, 7-4default values, 3-1design flow

RF Design Environment, 1-4RFIC Dynamic Link, 1-4

Index-1

design variables, 4-8devices, 3-1, 3-4

device mapping, 3-1device names, 3-2

differentiation operator, 3-121digital components, 3-122directories

amap, 6-3artist state, 2-15map, 6-3PSF, 7-3tool, 6-3

documentationAgilent, 1-6Cadence, 1-7

dot character, 4-7DumpFile, 5-3DumpLevel, 5-3dynamic scoping rules, 6-5

Eencrypted models, 5-3, 5-10environment settings, 6-6environment variables

ADSsim.envOpts, 2-4translateResults, 2-4

errorserror messages, 3-1, 4-8, 5-1, 6-6, 6-7, 7-4netlisting, 6-2syntax, 6-6

expressions, 6-4, 7-4

Ffiles

.cdsenv, 2-2

.cdsinit, 2-1

.een, 6-6

.scs, 6-5ads.ini, 2-2cds.lib, 2-2, 2-3file suffixes, 6-6rfde.lib, 2-2rfdeSpectreCompatibility.cfg, 2-3setup and configuration, 2-1setup.loc, 2-2

functionsaaSp, 7-4getData, 7-4

nlGetSimName, 6-3nlPrintInst, 6-3nlSetCurrentInstance, 6-3

HHDL, 5-9hierarchical nodes

bsource, 3-120Hierarchy Editor, 6-6hspice netlist, 6-6

Iic and nodeset control statements, 5-6include files, 6-5incompatible features, 5-1, 5-4info control statement, 5-7instance

bht, 3-26bjt, 3-19bjt503, 3-31bjt504, 3-35bjtst, 3-42bsim3v3, 3-51bsim4, 3-68capacitor, 3-7conditional, 4-6diode, 3-12inductor, 3-9jfet, 3-115juncap, 3-16mos1, 3-90mos2, 3-95mos3, 3-101mos902, 3-106mos903, 3-110mutual inductor, 3-11name mapping, 6-3netlisting, 6-2resistor, 3-5statements, 6-2vbic, 3-46

integration operator, 3-121internal data structures, 5-3inter-process communication, 1-4

KKnowledge Center

website address, 5-4

Index-2

Llibraries

adsLib, 2-2ahdlLib, 3-122analogLib, 2-2, 3-123basic, 2-3, 3-128Cadence, 3-122library defaults, 2-5rfLib, 3-128testing for compatibility, 2-9

librarysetup, 6-1

Mmapping, 3-1, 4-7measurement equations, 6-3mismatch variation, 4-6models, 3-1, 3-4

bht, 3-26bjt, 3-19bjt503, 3-31bjt504, 3-35bjtst, 3-42bsim3v3, 3-52bsim4, 3-69capacitor, 3-7cell model parameters, 2-17diode, 3-12encrypted, 5-10include path, 2-13inductor, 3-9jfet, 3-115juncap, 3-16model definition, 6-5model file setup, 2-13model include, 2-16, 6-5model names, 3-2mos1, 3-90mos2, 3-95mos3, 3-101mos902, 3-106mos903, 3-110resistor, 3-5vbic, 3-46

Monte Carlo analysis, 4-6multi-language simulator, 1-3multiplicity factor, 3-1

Nnested subcircuits, 6-5netlist

EEsof, 6-6functions, 6-2hspice, 6-6

netlister, 6-1netlisting

errors, 6-2Verilog-A, 6-5

node name mapping, 6-3

OOASIS, 6-3, 6-7open parentheses character, 4-7operators, 4-1

differentiation, 3-121integration, 3-121

options control statement, 5-7

Pparameter matching

case-preferential, 3-129parameter storage format (PSF), 2-4, 7-1parameters

max_val, 3-121min_val, 3-121temp, 3-119trise, 3-119

paramset control statement, 5-7paramtest, 5-9pin

currents, 6-3mapping, 6-3

post processing functions, 4-1pound character, 4-7probe functions, 3-121process design kit (PDK), 1-1, 1-4process variation, 4-6

Rreserved words, 4-7Results Browser, 7-2RF Design Environment, 1-3, 1-4

compatibility setting status, 2-6native netlisting mode, 6-7

RFDE Netlister, 6-1rfdeSpectreCompatibility.cfg, 2-3

Index-3

priority, 2-4

Ssave control statement, 5-8scalem, 5-9schematic environment, 6-1scoping rules, 6-4sectional include, 4-7set control statement, 5-8shell control statement, 5-8simInfo, 6-2simulator

front end, 1-3functions, 4-1, 4-3language, 5-10, 6-2, 6-6

sourcesbsource, 3-118linear controlled, 3-116polynomial controlled, 3-116supported, 3-117

special character support, 4-7Spectre

analyses, 5-4expressions, 4-1help, 3-1mapping rules, 6-3Pre-Parser, 5-11simulator, 1-3

Spectre-Compatible PDK, 1-1SPICE

Reader, 5-11syntax, 5-11

static scoping rules, 6-5stop view, 2-3, 2-18, 6-2, 6-6, 6-7structural if-else, 4-6subcircuits, 4-4

inline, 4-5nested, 4-4netlisting, 6-4parameters, 4-5

supported devices, 5-1switch view, 2-18, 6-6

Ttemperature scaling, 3-121tools, 2-1, 2-2

Uunderscore character, 4-7unique names, 6-5unsupported parameters, 3-1, 5-1user-defined functions, 3-121

VVerilog-A, 4-8

netlisting, 6-5viewInfo, 6-3, 6-5

Wwarnings

warning messages, 3-1, 6-7Waveform Viewer, 7-2website

address, 1-4, 1-7, 5-4, 5-10, 5-11

Index-4

spectre-compatible process design...

Documents