specifications for high speed demodulator and …...decoding, cadu and packet de-commutation ) frame...
TRANSCRIPT
Annexure-1
SPECIFICATIONS FOR HIGH SPEED DEMODULATOR AND
RECEIVER SYSTEM
Items
1
‘Integrated High Speed demodulator and Receiver’ comprising
of,
a. Demodulator and Bit Synchronizer b. Frame synchronizer and CCSDS Data Processor c. Server and Data Storage Unit
2 Data Simulator and Test Modulator
(Integrated with Item 1 or as Standalone Unit)
3 GPS based Time Code Generator (TCG)
QPSK Demodulator with Single Data Processing Chain
QPSK Demodulator with Dual Data Processing Chains
Data Processing Chain (DPC) 10 GbE
RF Section
Demodulator
&
Bit Synchronizer
I
Q
Differential
Decoding
Frame
Synchronizer
De-randomizer RS Decoder &
De-interleaving
CCSDS CADU
and Packet
Decoding
Storage
Disk
Frame
Synchronizer
De-randomizer RS Decoder &
De-interleaving
CCSDS CADU
and Packet
Decoding
Storage
Disk
10 GbE
Differential
Decoding
Viterbi
Decoder
Viterbi
Decoder
IF Section + Demodulator
10 GbE
I + Q
QPSK
Demodulator &
Bit Synchronizer
RF Section
Frame
Synchronizer
De-Randomizer
RS Decoder&
De-interleaving
CCSDSCADU
and Packet
Decoding
Storage
Disk
(RAID5)
Data Processing Chain (DPC)
Differential
Decoding
Viterbi
Decoder
IF Section + Demodulator
SPECIFICATIONS OF HIGH SPEED DEMODULATOR AND RECEIVER
SYSTEM
The system consists of following three items
Item 1
Section A:
De-modulation and Decoding
IF Receiver
Demodulator
Bit Synchronizer
Viterbi Decoder & Differential decoding
Section B:
Frame synchronizer and CCSDS Data Processing
Frame Synchronization and De-randomization
Reed Solomon & LDPC Decoder
Channel Access Data Unit (CADU) and Packet De-commutation
Section C:
Server and Data Storage Unit
Item 2
Data Simulator & Test Modulator
Item 3
GPS based Time Code Generator (TCG)
ITEM 1: SECTION A: IF RECEIVER+DEMODULATOR + BIT SYNCHRONIZER + DECODER
Sr.
No Parameter Specifications
IF RECEIVER
1 IF Input frequency 1200 ± 250 MHz
2 Input impedance 50 Ohms
3 Input Range (power) -10 dBm to - 50 dBm
4 IF Tunability ±1 MHz Step size or better
5 Acquisition Range ±10KHz to ±1 MHz
6 Input Connector SMA connector
DEMODULATOR
7 Demodulation Type BPSK,QPSK, 8PSK (Selectable)
8 Spectrum Inversion
All possible combinations with spectral inversion on/off.
I & Q swap, & Q , I & , &
9 Symbol Rate 300 Msps or better
10 Acquisition Time ≤ 0.350 sec
11 Data Filtering FIR RRC (Root Raise Cosine) filter with Programmable Roll of factor with enable and disable option
12 Synchronization
Retention Threshold
Es/No ≤ 2.5 dB for QPSK
BIT SYNCHRONIZER
13 PCM Code NRZ –L/M/S ,BP-L/M/S, DNRZ (selectable)
14 Acquisition Range +/- 0.1 % of Symbol rate
15 BER Performance Un-coded degradation,
BPSK/QPSK: <0.6db,10-6BER with diff encoding
16 Data rate
Data Rate as given below :
For BPSK Modulation:
300 Mbps (1x300Mbps)
For QPSK Modulation:
600 Mbps (2x300Mbps)
For 8PSK Modulation:
900 Mbps
VITERBI DECODER & DIFFERENTIAL DECODING
17
Decoding mode
Viterbi Decoding
Separate decoder on I&Q (Dual mode) chain and
Single decoder for I+Q (Merged) chain
Compliant to CCSDS Recommended Encoder
Configurations as per blue book ' CCSDS 131.0- B-2
Blue book Aug 2011'
Code Rate (r): 1/2
Constraint length (K): 7 bits
Connection Vector: G1 = 1111001(171 octal)
G2 = 1011011(133 octal)
Phase relationship: programmable association of G1
or G2 with first symbol, programmable inversion on
output path of G2
G1 – G2 inverted, G1 – G2
G2 inverted – G1, G2 – G1
Puncturing
Rate 1/2 Punctured to 2/3 & 7/8 as per CCSDS
Standards (selectable)
for example
Punctured pattern (for rate 7/8):
C0:1000101
C1:1111010
Convention1 pattern:
C0(1)C1(1)C1(2)C1(3)C1(4)C0(5)C1(6)C0(7)...
Convention2 pattern: (desirable) (for certain commercial
encoders)
C0(1)C1(1)C1(3)C1(2)C1(5)C0(4)C1(7)C0(6)
18 Viterbi decoding Enable/Disable
19 Decoder status Locked/Unlocked
20
Differential Decoding for
QPSK
DNRZ
1. Without Viterbi Convolution Decoding
1.
Other possible options selectable through GUI
2. NRZ- M (With Viterbi Convolution Decoding)
21 Differential Decoder Enable/Disable
22 Output Ports
Polarity: Normal /Inverted for Data & Clock
Separate I, Q channel: Data & Clock
Merged (I + Q) channel: Data & Clock
+ swap: Normal I & Q,
I inverted & Q,
I & Q inverted,
I inverted & Q inverted
Normal Q & I,
Q inverted & I,
Q & I inverted,
Q inverted & I inverted
23
Output (electrical)
(O/P available after
Viterbi decoding & Diff.
decoding)
LVDS, ECL, Ethernet (desirable)
24 Output connector SMA (Preferred) / D-type, RJ45 (desirable)
SECTION B: FRAME SYNCHRONIZER AND CCSDS DATA PROCESSING
(CCSDS compliant Frame Synchronization, De-Randomization, RS and LDPC Decoding, CADU and Packet De-commutation )
FRAME SYNCHRONIZATION AND DE-RANDOMIZATION
25 Input Specifications
1. NRZ (L, M, S) Selectable
2. Internally connected with Bit Synchronizer, Viterbi
Decoded, differential decoded outputs (data + clock)
3. Provision for external input (desirable) through
LVDS on D-type/SMA (data + clock)
Maximum Data Rate:
BPSK(1 X 300) Mbps
QPSK(2 X 300) Mbps
8PSK 900 Mbps
26
Data Merging For QPSK modulation:
(1) Separate processing chains for I & Q (2 DPC)
(2) Merged chain for I + Q (one DPS)
27 Frame Synchronization
1. Sync Pattern : Programmable length and pattern
( up to 64 bits)
2. Frame Length:16 byte to 1 Mbytes(Programmable)
including CCSDS defined Frame lengths as per CCSDS
131.0- B-2 Blue book Aug 2011’
3. Error threshold on the synchronization word : SYN = 0 to 15 errors Check to Lock threshold : CTL = 0 to 15 frames
Lock to Search threshold : LTS = 0 to 15 frames
4. Bit Slip Window(BSW): 0, 1 or 2
5. Frame Sync strategy: Programmable Search,
Verify & Lock
6. Fly-wheeling : 0 to 15
28
De-Randomization with
Enable/ Disable
(Programmable)
1. De-randomizer compliant to CCSDS recommendation
as per CCSDS-131-0-B-2 Aug 2011 (Mandatory)
and
2. Programmability for polynomial, seed word
(Initialization Value) and length (7 to 15)
( Preferable)
REED SOLOMON & LDPC DECODER
29
Reed Solomon
Decoding
(With Enable/Disable
(Programmable)
Should be compliant to both CCSDS recommended
configuration i.e.
(a) RS(255,223) with Virtual fill and Interleaving
(b) RS(255,239) with Virtual fill and Interleaving
The specification of Generator polynomial, Virtual fill and
interleaving are as specified by CCSDS document
(CCSDS-131-0-B-2 Aug 2011)
30 LDPC (desirable)
Should be able to decode CCSDS recommended
rate 7/8 configuration Specified as per CCSDS
document (CCSDS-131-0-B-2 Aug 2011)
DATA DE-COMMUTATION AND ARCHIVAL
31
CCSDS Compliant
Data De-commutation
1. Data De-commutation to retrieve CADU/VCDU
as per CCSDS recommendation
“TM Space Data Link Protocol CCSDS 132.0-B-1
Sep 2003” and
“AOS Space Data Link Protocol CCSDS 732.0-
B-2 Sep 2006” or their latest version ( if any) including
Technical Corrigendum
2. Data De-commutation to retrieve CCSDS Packets
as per CCSDS recommendation “Space Packet
Protocol CCSDS 133.0-B-1” or its latest version (if
any) including Technical Corrigendum (desirable)
Facility to select/ Deselect CADU/VCDU/Packet
De-commutation.
32 Base band Data
Archival and Output
1. Simultaneous Raw and Processed Archival
(Frames: CADU/VCDU/Packets) with time tagging at
start of frame
2. Near Real time Playback output through 10 GbE
(copper) Ethernet interface RJ45 to User Computer
Decoded data output format with details and
protocol / files formats to be provided.
33
Monitor and Control
(M & C)
IF section
IF Input Frequency (M,C)
Acquisition Range (M,C)
Input level (M)
Demodulator
BPSK/QPSK/8PSK Demodulation Schemes (M,C)
Demodulator Lock Signal (M)
Filtering Roll off factor (M,C)
Eb/No (M)
Symbol Rate (M,C)
BER (M)
Spectrum, Constellation (M)
Bit Synchronizer
PCM Input Codes (M,C)
Bit Rates (M,C)
Bit Sync Lock Status (M)
Data, Clock Polarity Selection (M,C)
Viterbi decoder & Differential decoding
Viterbi Decoding include/exclude (M,C)
Single/Dual Viterbi selection (M,C)
Viterbi Decoding selection (Rate, puncturing) (M,C)
Differential Decoding include/exclude (M,C)
Selection for G1 Poly.: inverted/not inverted (M,C)
Selection for G2 Poly.: inverted/not inverted (M,C)
Selection of G1-G2 or G2- G1 (M,C)
Differential Decoding equations (M,C)
Frame Sync and De-randomizer
Frame Sync length (M,C)
Frame Sync Pattern (M,C)
Frame Sync Error Allowance (M,C)
Frame Sync Lock/unlock Status (M)
No. of Frame for Fly wheeling (M,C)
Frame Length (M,C)
Frame Drop Counter in real-time (M)
De-randomization Include/exclude (M,C)
De-randomizer poly. Initialization word (M,C)
RS,LDPC channel Coding
RS Decoding include/exclude (M,C)
RS Decoding Error Status (M)
Symbol De-interleave selection (C)
Code RS (n, k) selection (C)
Virtual fill selection (M,C)
LDPC decoding include/exclude(M,C)
LDPC Code selection (M,C)
LDPC Decoding Error Status (M)
Data De-commutation
CADU/VCDU/Packet specification, analysis ,monitor and
store (M, C, Store)
SECTION C : SERVER AND DATA STORAGE
1 Data Server (in-built)
Enterprise class server with Linux or Windows
Operating System (latest) with minimum 4GB RAM, 2 USB
Port, Keyboard, Optical mouse,1 Serial port , Min. 21“ flat
LCD Monitor (external)
Up - gradation support
2 Storage HDD and
Capacity
RAID-5, 6 TB - Raw Internal Storage with
SAS/SATA-2 Disks
3 Interfaces 1. Network port: 10 GbE (for Data Transaction)
2. Network ports: 1GbE (for all other purposes)
4 Time Synchronization NTP time synchronization with supplied TCG
COMMON SPECIFICATIONS
1 Dimensions 4U (max), 19” Rack mountable
2 Operating Temperature 25 ± 15° C
3
Operating Relative
Humidity (Non-
condensing)
5 % to 90 %
4 Power supply
Configuration Redundant Power Supplies
5 Power Supply Voltage 230 V ± 10 % , 50 Hz
6 Warranty period 3 years Comprehensive warranty on site
7 Service supports In SAC, Ahmedabad, India
8 Documents & Software User Manuals, Hardcopy & Softcopy, OS, drivers and
Installable in CD/DVD with 1 year free upgrade
ITEM 2 : DATA SIMULATOR AND TEST MODULATOR
Integrated with item 1 or separate
1 All parameters/features for comprehensive testing of Demodulator, Bit
synchronizer and Data Processing Chain (DPC) section as specified above.
Differential Encoding for QPSK
Modulation
without Convolution encoding
NRZ-M (with Convolution encoding)
2 Input :
1. Provision for user defined data patterns through GUI or External data file.
Read facility using suitable interface like Ethernet/USB
2. Digital input (LVDS) from SMA/D-type connector
3
Output:
1. TM simulator - Digital Output, (LVDS ) on SMA/D-type
2. Modulated IF output should be on SMA connector
4 In-built noise generator with external digital/Pseudo random input
ITEM 3 : GPS BASED TIME CODE GENERATOR (TCG)
1 Antenna
Outdoor GPS antenna with required fittings for wall
mounted/floor mounting
Minimum 6m cable length, Connectivity of cable
antenna side and GPS receiver/Time code generator
side connectivity including Power connectivity.
2 GPS Receiver Minimum 12 channel GPS receiver
3 Time Code Generator
Accuracy: 1 PPS @ < 500µsec
Drift: 30 ms/day if no GPS signal
Indicator: GPS ‘Lock ‘ indicator on front panel
4
Time Zone Offset
setting using keys on
Front panel
Soft Key on front panel
5 Display
LED/LCD display for day of year, time-hour, minute
and seconds, GPS lock indicator, continuous display
on front panel.
6 Interface with Computer
1. NTP Server, minimum 100/1000 Mbps network
port with day/date and time output on RJ45
connector in standard NTP format.
2. RS 232C, @9600 Baud rate.
S/W suite (CD or Download Access) for Windows
7 Mechanical 19 “ Rack mountable enclosures , 1U size
8 Power 230 V, 50 Hz
9 Operating Temperature 25 ± 15° C
10 Operating Relative
Humidity (Non-
condensing)
5 % to 90 %
11 Warranty 3 Years at site (SAC, Ahmedabad)
Notes and Essential Terms & Conditions
1 Supplier should submit quotations in two parts, 1. Technical & 2. Commercial
2 Only offers providing integrated solution consisting of all Items will be accepted.
3 Supplier should submit quotation along with point by point compliance with
supporting technical documents. Supplier must bring out deviations, if any.
4 Supplier must produce OEM certification for the primary components (Item 1&2) along
with the offer.
5 Items 1&2 have to be OEM integrated solution and supplier to produce certification
from OEM for same.
6 The supplier must include the Factory Test Reports and certificate with the items 1&2.
7 Supplier must provide cables/accessories required for connectivity among all items.
8
Additionally supplier has to offer all cables (length: 2m min.) for external
interfaces offered on the Rear Panel. Pricing information must be provided for
such items separately.
9 Vendor to provide a list of all onsite up-gradable features with apportioned cost.
10 Vendor should quote for new product only.
11 Vendor has to indicate previous installed base of such/similar items in India and other
International Installations.
12
Supplier should install the equipment at indenter’s site. Any additional
equipment/cables required shall be brought by the vendor for the entire system,
required for the installation.
13 If needed Vendor may be asked for NC-NC (No cost No commitment trial) before the
technical recommendation of the bid by the committee.
14 Vendor is required to quote in slab quantity of one and two units. SAC reserve the
right to choose quantity one or two at the time of ordering
15 Acceptance test plan is to be prepared by vendor and finalized in consultation with
indenter.
16
All functionalities to be demonstrated to indenter satisfaction. As part of acceptance
test, the instrument including Data Server and Storage will be subjected to minimum
168 hours burn-in test in lab environment.
DELIVERABLES
1
Unit comprising of,
a. Demodulator and Bit Synchronizer b. Frame synchronizer and CCSDS Data Processor c. Server and Data Storage Unit
2 Data Simulator and Test Modulator (Integrated with Item1 or as Standalone Unit)
3 GPS based Time Code generator (TCG)