Specification

BTHQ 128064AVG-FFEMN-06 LED02WHITE-COG (BT45182)

Version April 2007

Doc. No.: COG-BTG12864-01

DOCUMENT REVISION HISTORY

DOCUMENTREVISION

FROM TO DATE DESCRIPTION

CHANGEDBY

CHECKEDBY

A 2007.04.25 First Release. Based on a.) Test Specification:

VL-TS-COG-BTG12864-XX REV.A 2006.11.17

b.) VL-QUA-012B REV.W 2004.03.20

(According to VL-QUA-012B, LCD size is small because Unit Per Laminate=35 which is more than 6pcs/Laminate.)

XIAO LI LAN

VIVIANLUO

2

CONTENTS

Page No.

1. GENERAL DESCRIPTION 4

2. MECHANICAL SPECIFICATIONS 4

3. INTERFACE SIGNALS 8

4. ABSOLUTE MAXIMUM RATINGS 104.1 ELECTRICAL MAXIMUM RATINGS – FOR IC ONLY 104.2 ENVIRONMENTAL CONDITION 10

5. ELECTRICAL SPECIFICATIONS 11 5.1 TYPICAL ELECTRICAL CHARACTERISTICS 11 5.2 TIMING SPECIFICATIONS 125.3 INSTRUCTION SET 155.4 COMMAND DESCRIPTION 17

6. LCD SPECIFICATIONS 20

7. LED CHROMATICS COORDINATES 28

8. ELECTRO-OPTICAL CHARACTERISTICS 28

9. OPTICAL CHARACTERISTICS DEFINITION 29

10. 30LCD COSMETIC CONDITIONS

3

Preliminary Specification

of

LCD Module Type

Model No.: COG-BTG12864-01

1. General Description

128 x 64 dots FFSTN Negative Black transmmsive LCD graphic module.

Viewing angle: 6 o’clock.

Driving scheme: 1/65 duty, 1/9 bias.

Driving IC: ‘NOVATEK’ NT7534H-BDT (COG) LCD controller/driver or equivalent.

Logic voltage: 3.3V.

White LED02 backlight.

FPC connection.

“RoHS” compliance.

2. Mechanical Specifications

The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.

Table 1Parameter Specifications Unit

Outline dimensions 45.24(W) x 29.14(H) x 8.5(D) (Excluded FPC) mm Viewing area 37.04(W) x 20.24(H) mm Active area 34.545(W) x 17.265(H) mm Display format 128(W) x 64(H) dotsDot size 0.255(W) x 0.255(H) mm Dot spacing 0.015(W) x 0.015(H) mm Dot pitch 0.270(W) x 0.270(H) mm Weight Approx: 10.5 gram

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5

Figure 2: Block Diagram

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Figure 3: Reference test circuit

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3. Interface signals

Table 2 (a): Pin assignmentPin No. Symbol Description

1 LED_K Cathode of LED backlight. 2 LED_A Anode of LED backlight. 3 N.C No Connection.4 N.C No Connection.

5 P/S

This is the parallel data input/serial data input switch terminal P/S = “H”: Parallel data input P/S = “L”: Serial data input The following applies depending on the P/S status:

P/S Data/Command Data Read/Write Serial Clock “H” A0 D0 to D7 /RD, /WR -“L” A0 SI (D7) Write only SCL (D6)

When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or Open. /RD (E) and /WR (R/W) are fixed to either “H” or “L”. With serial data input, RAM display data reading is not supported.

6C86

This is the MPU interface switch terminal: C86 = “L”: 6800 Series MPU interface, C86 = “L”: 8080 Series MPU interface.

7 V0

8 V4

9 V3

10 V2

11 V1

LCD driver supplies voltages. The voltage determined by the LCD cell is

impedance-converted by a resistive driver or an operation amplifier for

application. Voltages should be according to the following relationship:

V0 V1 V2 V3 V4 VSS2

When the on-chip operating power circuit is on, the following voltages are

supplied to V1 to V4 by the on-chip power circuit. Voltage selection is

performed by the LCD Bias Set command.

LCD bias V1 V2 V3 V4

1/4bias 3/4 V0 2/4 V0 2/4 V0 1/4 V0

1/5bias 4/5 V0 3/5 V0 2/5 V0 1/5 V0

1/6bias 5/6 V0 4/6 V0 2/6 V0 1/6 V0

1/7bias 6/7 V0 5/7 V0 2/7 V0 1/7 V0

1/8bias 7/8 V0 6/8 V0 2/8 V0 1/8 V0

1/9bias 8/9 V0 7/9 V0 2/9 V0 1/9 V0

12 C2- Capacitor 2- pad for internal DC/DC voltage converter. 13 C2+ Capacitor 2+ pad for internal DC/DC voltage converter. 14 C1+ Capacitor 1+ pad for internal DC/DC voltage converter. 15 C1- Capacitor 1- pad for internal DC/DC voltage converter. 16 C3+ Capacitor 3+ pad for internal DC/DC voltage converter. 17 VOUT DC/DC voltage converter output18 VSS Ground.

Table 2 (b): Pin assignmentPin No. Symbol Description

19 VDD Power supply input. 20 D7 (SI) 21 D6 (SCL) 22 D523 D424 D325 D226 D127 D0

This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit

standard MPU data bus. When the serial interface is selected (P/S=“L”),

then D7 serves as the serial data input terminal (SI) and D6 serves as the

serial clock input terminal (SCL). At this time, D0 to D5 are set to high

impedance. When the chip select is inactive, D0 to D7 are set to high

impedance.

28 RD______

(E)

When connected to an 8080 MPU, it is active LOW. This pad is connected to

the /RD signal of the 8080MPU, and the NT7534 data bus is in an output status

when this signal is “L”. When connected to a 6800 Series MPU, this is active

HIGH. This is used as an enable clock input of the 6800 series MPU

29 WR______

(R/W)

When connected to an 8080 MPU, this is active LOW. This terminal

connects to the 8080 MPU WR______

signal. The signals on the data bus are

latched at the rising edge of the WR______

signal.

When connected to a 6800 Series MPU, this is the read/write control signal

input terminal.

When R/W = “H”: Read

When R/W = “L”: Write

30 A0

This is connected to the least significant bit of the normal MPU address

bus, and it determines whether the data bits are data or a command. A0 =

“H”: Indicate that D0 to D7 are display data A0 = “L”: Indicates that D0 to

D7 are control data

31 RES_______ When /RES is set to “L”, the settings are initialized. The reset operation is

performed by the RES_______

signal level

32 CS1______

This is the chip select signal.

When CS1______

=“L” and CS2=“H”, then the chip select becomes active, and

data/command I/O is enabled.

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4. Absolute Maximum Ratings

4.1 Electrical Maximum Ratings – For IC Only

Table 3

Parameter Symbol Min. Max. UnitDC supply voltage (logic) VDD - VSS -0.3 +4.0 VDC supply voltage (Vout) Vout -0.3 +15.0 VDC supply voltage (V0) V0 -0.3 +15.0 VInput voltage VIN -0.3 VDD +0.3 V

Note:

The modules may be destroyed if they are used beyond the absolute maximum ratings.

All voltage values are referenced to VSS = 0V.

4.2 Environmental Condition

Table 4

Operatingtemperature

(Topr)

Storage temperature

(Tstg) (Note 1)

Item

Min. Max. Min. Max.

Remark

Ambient temperature -20 C +70 C -30 C +80 C Dry

Humidity (Note 1) 90% max. RH for Ta 40 C< 50% RH for 40 C < Ta Maximum operating temperature

No condensation

Vibration (IEC 68-2-6) cells must be mounted on a suitable connector

Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction.

3 directions

Shock (IEC 68-2-27) Half-sine pulse shape

Pulse duration: 11 ms Peak acceleration: 981 m/s2 = 100g Number of shocks: 3 shocks in 3 mutually perpendicular axes.

3 directions

Note 1: Product cannot sustain at extreme storage conditions for long time.

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5. Electrical Specifications

5.1 Typical Electrical Characteristics

At Ta = 25 C, VDD = 3.3V 5%, VSS=0V.

Table 5Parameter Symbol Conditions Min. Typ. Max. Unit

Supply voltage (Logic)

VDD-VSS 3.14 3.3 3.47 V

Ta = -20 C, Character mode, VDD = +3.3V, Note 1

- 11.3 - V

Ta = +25 C, Character mode, VDD = +3.3V, Note 1

10.5 10.7 10.9 V

Supply voltage (LCD)(Built-in)

VLCD=V0-VSS

Ta = +70 C, Character mode, VDD = +3.3V, Note 1

- 10.2 - V

Low-level input signal voltage

VILC Note 2 VSS - 0.2xVDD V

High-levelinput signal voltage

VIHC Note 2 0.8xVDD - VDD V

Character mode, VDD = +3.3V,Note 1

- 0.3 0.5 mA Supply Current (Logic & LCD)

IDDChecker board mode, VDD = +3.3V,Note 1

- 0.3 0.5 mA

Supply current of white LED02 backlight

VLED - 30 40 mA

Luminance of backlight (on the backlight surface)

Forward voltage =4.0VNumber of LED dies =2

490 650 - cd/m2

Note 1: There is tolerance in optimum LCD driving voltage during production and it will be

within the specified range.

Note 2: A0, D0 to D5, D6 (SCL), D7 (SI), RD_____

(E), WR______

(R/W), CS1, C86, P/S, RES_______

terminals.

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5.2 Timing Specifications

8080 Series MPU Timing

At Ta = -20 C to +70 C, VDD = +3.3V 5%, VSS = 0V.

Table 6

Note 1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less.

(tr + tf) < (tCYC8 - tCCLW - tCCHW) for write, (tr + tf) < (tCYC8 - tCCLR - tCCHR) for read.

Note 2. All timing is specified using 20% and 80% of VDD as the reference.

Note 3. tCCLW and tCCLR are specified as the overlap interval when /CS1 is low (CS2 is high) and /WR

or /RD is low.

Figure 4: 8080 Series MPU Timing

6800 Series MPU Timing

At Ta = -20 C to +70 C, VDD = +3.3V 5%, VSS = 0V.

Table 7

Note 1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less.

(tr + tf) < (tCYC6 - tEWLW - tEWHW) for write, (tr + tf) < (tCYC6 - tEWLR - tEWHR) for read.

Note 2. All timing is specified using 20% and 80% of VDD as the reference.

Note 3. tEWHW and tEWHR are specified as the overlap interval when /CS1 is low (CS2 is high) and E is high.

Figure 5: 6800 Series MPU Timing

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Reset Input Timing

At Ta = -20 C to +70 C, VDD = +3.3V 5%, VSS = 0V.

Table 8

Figure 6: Reset Timing Diagram

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5.3 Instruction Set

Table 9(a): Command table

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Table 9(b): Command table

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5.4 Command Description

Instruction Setup: Reference

Initialization

Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3

(SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM.

When electric charge is remaining in the smoothing capacitor connecting between the LCD driving

voltage output pins (V0 - V4) and the VDD pin, the picture on the display may instantaneously

become totally dark when the power is turned on. To avoid such failure, we recommend the following

flow sequence when turning on the power.

When the built-in power is being used immediately after turning on the power:

17

When the built-in power is not being used immediately after turning on the power:

18

Data Display

Power OFF

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6. LCD Specifications

Figure 7: LCD Drawing 1

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Figure 8: LCD Drawing 2

Figure 9: LCD Drawing 3

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Figure 10: LCD Drawing 4

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Figure 11: LCD Drawing 5

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Figure 12: LCD Drawing 6

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Figure 13: LCD Drawing 7

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Figure 14: LCD Drawing 8

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7. LED Chromatics Coordinatesx 0.296 0.287 0.307 0.311

Colour Coordinate y 0.276 0.295 0.315 0.294

Note: The LED Chromatics Coordinates tolerance is 0.01.

8. Electro-Optical Characteristics

Table 10Value

Item SymbolTemp.

C Min. Typ. Max.Unit Condition

-20 - 11.3 -+25 - 10.9 -Driving voltage Vop+70 - 10.2 -

V Vop= optimum voltage

Ton - TBD -Toff

-30- TBD -

msec

Ton - TBD -Toff

+25- TBD -

msec

Ton - TBD -

Response time

Toff+80

- TBD -msec

Vop= Optimum voltage = 0 , = 0

1(6 o’clock) - TBD -2(12 o’clock) - TBD -

= 0

1(3 o’clock) - TBD -

Optimumviewing area

Cr TBD 2(9 o’clock)

+25

- TBD -DEG

= 0

Vop= Optimumvoltage

(Remark 1)

Contrast ratio Cr +25 - TBD --

Vop = Optimum voltage= 0 , = 0

Remark 1: Due to hardware limitation, the maximum measurable angle is 70 O.

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9. Optical Characteristics Definition

a.)Viewing Angle

b.) Contrast Ratio

B1 = segments luminance in case of non-selected waveform

B2 = segments luminance in case of selected waveform

c.) Response Time

Contrast Ratio is defined by

Cr = B2/B1

Select waveform

Non-select

waveform

1

B2

Lum

inance

00

B1

Vop

Non-Selected dot Selected dot

Lum

inance

OFF ON OFF

90%

10%

rise time fall time

10. LCD Cosmetic Conditions

a.) Reference document follow VL-QUA-012B.

b.) LCD size of the product is small.

- END -

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