Specification and Design of Quasi-Delay-Insensitive Java Card

Microprocessor

Fu-Chiung Cheng & Chuin-Ren Wang

Dept. of Computer Science and EngineeringTatung University

Taipei 104, Taiwan R.O.C.

Outline

1. Motivation

2. Smart Card Architecture

3. Introduction of Java Card

4. Java Card Processor Organization

5. Specification : Data Dependency Graph

6. Implementation and Optimizations

7. Conclusion

1. Motivation

• ID card, driver license, credit cards, bank Cards, library card, pay-phone card, ...

=> Smart Card• Other applications :[Henry97]

– fraud control for credit and debit cards– access control for buildings or computer syste

ms – ticketless travel on airlines, subways, buses or

trains.• Java Card is a smart card using Java technology.

1. Motivation

• Why Asynchronous circuit for Java Card Microprocessor? [Hauck95,Cheng97]

– low power consumption– average-case performance– robust– Modularity, Composability, Reusability

2. Smart Card Architecture

• Smart card architecture consists of – CPU

– memory

– communication interface

• The front and back of Smart card:

2. Smart Card Architecture

• Smart Card CPU:– 8-bit, single-tasking devices with 1KB

of RAM or less.• On-Card Memory

– ROM (Read-Only Memory) – RAM (Random Access Memory)– EEPROM (Electrically Erasable

Programmable Read Only Memory)

2. Smart Card Architecture

• Communication Interface– A smart card does not contain its own power supply, display, or keyboard.

• Card Acceptance Device (CAD)– A smart card interacts with a Card Acceptance Device (CAD) through the communication interface

3. Java Card

• Java Card is a smart card using Java technology.• Java programs run on Java Virtual Machine (JV

M).• JVM is an interpreter to execute bytecodes (Java

instructions). • JVM is a stack-based machine. • Java Card instruction set is a subset of Full Java’

s.

3.1 Data type in Java Card • Two kinds of types: primitive types and reference t

ypes.• Primitive types

– byte : 8-bit signed two’s-complement integer.– short :16-bit signed two’s-complement integers.– int : 32-bit signed two’s-complement integers.– Boolean : 8-bit, TRUE or FALSE.

• Reference types– class types, interface types, and array types.

3.2 Java Card Instruction Set

• Java Card 2.0 has 104 instructions.

1. Load/ Store Instructions: iload, istore, ....

2. Arithmetic Instructions: iadd, isub, ior, ....

3. Type Conversion Instructions: i2b, i2s.

4. Control Transfer Instructions: ifnull, if<cond>

5. Operand Stack Management: pop, dup, ....

6. Object Creation and Manipulation: new, getfield

7. Method Invocation and Return Instructions: invokespecial, invokestatic, return, .....

8. Throwing and Handling Exceptions: athrow.

4. JAVA Card Processor Organization

PC: program counter SP: stack pointer IR: instruction register

MAR: memory address register MI: memory interface

A, B: two general-purposed registers FB: Frame-based register

: Control line

: Bus line

M em ory

M I

P C S P FBIR A B A LU

M em oryaddress

data

C ontro lle r

M A R

A LU B us

A B us

B B us

5. Specification: Data Dependency Graph

• Given an instruction set + a processor organization, micro-operations of instructions may be specified by data dependency graphs [Nanya94].

• The micro-operations can be directly mapped into quasi-delay-insensitive components.

• Five basic components: fork, join,select, merge and oval (micro-operation).

5.1 DDG: Five Basic Elements

c:=f(a,b)

Merge

Select

Join

Fork

Microoperation

5.2 DDG: Java Card Processor

MAR := PC

MI := Readmem(MAR)

decode

IR := MI

Load/S tore A rithm etic

Typeconvers io

n

O bjectcreation

m anipu la tion

O perandTransfer

C ontro lT ransfer

M ethodinvocatio

n andR eturn

Throw ingand

H andling

A := ALU(add, PC, 1)

PC := A

Fetch Instruction

Decode

Execution

5.3 DDG: iadd instruction

MAR := SP - 4

MI := Readmem(MAR)

B := MI

decoder

MAR := SP - 4

W ritemem(MAR)

iadd

Arithmetic

isub ........A

B

C

D

E

F

G

H

I

A := MI

SP := MAR + 4

MI := A + B

MI := Readmem(MAR)

pop value2

pop value1

calculate

push result

SP := MAR

SP := MAR

J

K

MAR := SP

L

value1

value2SP

...

before

SP

result

...

after

6. Implementation:

• Goal: four-phase handshaking QDI circuits [Nanya94,Cheng97].

• Mapping DDGs to QDI Components

• TITAC: point-to-point data transfer

• Our Java Card Processor: shared bus architecture.

6.1 Shared Bus Architecture

6.2 QDI Library

6.3 Deriving Control Path from DDGs

c:=f(a,b) Q Datapath

C

Datapath

Merge

Select

Join

Fork

microoperation

Decoder

6.3 C-element and Q-element

A B0 0 00

01

11 1 1

Input O utputO

Nochange

CAB O

C-elem ent

C

U i

U o

Lo

Li

U i

Lo

LiUo tim e

Control Path: iadd

Q

Q

Q

AsAf

BsBf

CsCf

Q DsDf

Q EsEf

QFsFf

Q GsGf

QHsHf

Q IsIf

Q JsJf

Q KsKf

Q LsLf

6.3 Deriving Datapath from DDGs:

• For each micro-operation, M, and its Q-element with the start (Ms) and finish (Mf) of this micro-operation:– If M read a register R then connect Ms to the rea

d signal of R.– If M write to a register R then connect Ms to the

write signal of R and add a demultiplexer to send out the write acknowledge to Mf.

– If there are multiple signals connecting to a read/write signal, add an OR gate.

DatapathIs

Gf

A

read

write

Din

Dout

WackGs

Kf

Memory

read

write

Din

Dout

Wack

Bs

Fs

Ks

Addr.

BsDsFs

AfMAR

read

write

Din

Dout

WackAsEs

As

Ks

Es

Ef

HsLs

JsDEM UX

s0s1s2

o2o1o0 Jf

Jf

As

Ds

Es

Df

Js

HsLs

D E M U X

s0s1s2

o2o1o0

HfLf

Df

HfLf

SP

read

write

Din

Dout

Wack

BsFs

Gs

BfFfIf

MI

read

write

Din

Dout

WackIs

Cs

DEM UX

s0s1s2

o2o1o0

BsFsIs

IsKs

Cf

B

read

writeDin

Dout

Wack

Is

Cs

Q

Q

Q

AsAf

BsBf

CsCf

Q DsDf

Q EsEf

QFsFf

Q GsGf

QHsHf

Q IsIf

Q JsJf

Q KsKf

Q LsLf

Control Path

6.4 Optimization:

• Goal: better performance, less power consumption and/or less logic.

• Three optimization schemes:– Redundancy Elimination– Parallel Execution– Common Modularity

6.4 Optimization: Example 1

MAR := SP - 4

MI := Readmem(MAR)

B := MI

W ritemem(MAR)

A

B

C

D

E

F

G

H

I

A := MI

SP := MAR

MI := A + B

MAR := SP - 4

MI := Readmem(MAR)

pop value2

pop value1

calculate

push result

B := MIC DSP := MAR

MAR := SP - 4

MI := Readmem(MAR)

A

B

W ritemem(MAR)

E

F

G

H

I

A := MI

MI := A + B

MAR := SP - 4

MI := Readmem(MAR)

(a) (b)

6.4 Optimization: Example 2

• Sharing Common modules:

6.4 Optimization: Results

• Redundancy Elimination– Micro-operations: 12 9– Cost and power consumption: save one additio

n and three data transmission operations.

• Parallel Execution: – Micro-operations: 9 8

• Common Modularity:– Cost: save (n-1)*getTwoOperands.

(n is number of instructions in Arithmetic).

• A new asynchronous Java Card microprocessor architecture is presented.

• Data dependent graph is used to specify the micro-operations of Java card microprocessor.

• Three optimization schemes are applied for better performance, less power consumption and/or logic.

• New Java Card 2.1 (Mar. 1999) spec contains 186 instructions.

• We are developing CAD tool.

7. Conclusions