Confidential

Specialty Technology I- eNVM

Yau Kae SheuAssociate Vice President

Specialty Technology DevelopmentMay 27, 2015

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Outline

• UMC Advanced eNVM Solutions• Technology Introduction at 55/40nm• Application Driven Platform

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Leading eFlash Solution

• Continuous cell size migration to support application such as MCU, SmartCard, Touch IC and coming IoT

32014 2016DevelopingDevelopingAvailableAvailable

eFla

sh c

ell (

um2 )

40nm1.1V/2.5V40nm

1.1V/2.5V

0.11um1.2V/3.3V0.11um1.2V/3.3V

0.18um1.8V/3.3V0.18um1.8V/3.3V

8”

12”

0.25um2.5V/3.3V0.25um2.5V/3.3V

0.35um3.3V

0.35um3.3V

55nm1.2V/2.5V55nm1.2V/2.5V 28nm

1V/2.5V28nm1V/2.5V

>2017Under PlanningUnder Planning

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UMC Advanced eNVM Solutions

• Build NVM cell on top of UMC advanced logic platform (55/40nmLP)

• Basic Technical Requirement• Logic compatibility to ensure functionality of

fundamental IPs• Nonvolatile memory capability for different

applications• NVM bitcell selection

• SST ESF3: Embedded Super Flash generation 3• Cypress SONOS

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Comprehensive Understanding of Bitcells

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Key Concerns SSTESF3

CypressSONOS

Logic Compatibility

Temp. Coverage

ApplicationMCU,Auto,

Industrial

IOT,Consumer

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Bitcell Introduction

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• Program• Source-side-injection• Max voltage 10.5V on CG

• Erase• Poly-Poly FN tunneling• Max voltage 11.5V on EG

• Program• FN tunneling thr channel• Max voltage 4V

• Erase• FN tunneling thr channel• Max voltage 4V

SST ESF3• Triple poly• Floating gate as storage

layer

Cypress SONOS• Single poly• SiN as storage layer

e-FG

SiN

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Comparison - Process

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Key Features SSTESF3

CypressSONOS

Structure 1.5T (split-gate) 2T

Poly layers 3 1

Storage node Polysilicon Nitride

HV 12V 4V

Gox scheme Core/IO/HV Core/IO

Extra masking 13 5

Cell size<0.1um2 @55nm

<0.08um2 @40nm<0.12um2 @55nm<0.1um2 @40nm

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Comparison - Macro Performance

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Technology SSTESF3

CypressSONOS

PGM/ER Mechanism CHE/FN FN/FN

PGM/ER Time 10us/4ms 2ms/6ms

Operation temp. -40C ~ 125C -40C~110C

Isb < 1uA

Read Current (total) ~ 60uA/MHz

Access Time < 25ns

Endurance 100K

Data Retention , 85C 10yrs

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Key Milestones

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Technology SSTESF3

CypressSONOS

Node 55 40 55 40

TC0 Bitcell & HV V V V V

TC1Array-Level Chz

Logic IP VerificationV Jun/’16 V V

TC2Macro qual

(1st lot)V Feb/’17 Jan/’16 May/’16

55nm SST platform has been officially released in Jan/’15

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55nm SST Technology Status

• TC2(Generic 4Mb Vehicle) yield trend >90%• 1st product 3.44Mb yield trend >90%• 2nd product 13Mb pilot yield 92%• >10 customization IPs under verification• >10 product T/Os under planning• Wide application spectrum including smartcard,

fingerprint, RFID, MCU, green energy, IoT, Automotive, etc.

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Product Yield Trend Chart

• Yield >90% for both Marco and Product• CP2 retention loss <2%

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Application Driven Platform

• Macro customization• Design support to fit to specific application

requirement• Technology capability enhancement

• IoT ultra low power requirement• Auto high temp. requirement with stringent

reliability criteria

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Customization Version at 55nm ESF3

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Macro Spec. Gen Ver. LC Ver. LP Ver. HS Ver.

Application MCU SIM/SmartCard IoT Auto

Operation temp. -40C~125C -40C~85C -40C~125C 40C~150C

Bus Width X32 X64 X32 X38 X32 X144

Standby Current< 1uA@ 25C

< 1uA@ 25C

< 1uA@ 25C

< 1uA@ 25C

Read Current (total)< 5mA/ 33MHz

< 5mA / 33MHz

< 2.4mA / 40MHz

<40mA/110Mhz

Access Time < 20ns < 40ns < 25ns <10ns

Endurance 100K 100K 100K 10K

Data Retention@85C 10yrs 10yrs 10yrs 10yrs

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IOT Platform Requirement

• Low Vcc Capability Active Power• Nominal Vcc range down to 0.9V• Fundamental IPs, SRAM compiler, eFlash macro

• uHVT Device Offering Leakage Power• Reduce transistor leakage further

• Build uLP(ultra-Low-Power) platform on top of existing LP platform

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55uLP Platform Offering Summary

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55nm uLP Technology

Core Devices Devices

Native VT

Bipolar

NCAP/MOM

Resistors

Diodes

I/O Devices

5V LDMOS

Inductor

uLP SRAM

6T 0.525 um2

8T 0.798 um2

SONOS

2.5V_UD1.8V/OD3.3V

LVT 0.9V

RVT 0.9V

HVT 0.9V

uHVT 0.9V

:55uLP extra offering

SST

eFlash

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40uLP Platform Offering Summary

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40nm uLP Technology

Core Devices Devices

Native VT

Bipolar

NCAP/MOM

Resistors

Diodes

I/O Devices

5V/8V LDMOS

2.5V_UD1.8V/OD3.3V

Inductor

uLL SRAM

6T 0.242 um2 (0.9V)

eFlash

SONOS

:40uLP extra offering

LVT 0.9V

RVT 0.9V

HVT 0.9V

eLVT 0.9V

eHVT 0.9V

SST

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IOT Macro at 55nm ESF3 & SONOS

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Macro Spec.(LP Ver.) ESF3 SONOS

Application IoT IoT

Operation temp. -40C~125C -40C~110C

Voltage (Vcc/Vcc1) 0.9~1.2V 0.9~1.2V

Standby Current < 10uA @ 25C < 10uA @ 25C

Read Current < 2.4mA / 40MHz ~ 2.4mA / 40MHz

Access Time< 25ns

(< 60ns @ 0.9V) < 25ns

(< 60ns @ 0.9V)

Endurance 100K 100K

Data Retention , 85C 10yrs 10yrs

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Auto Application

• Extend temperature working range from 125C to 150C• Model and fundamental IP at 150C• SRAM compiler and eFlash macro at 150C

• Manufacturing capability enhancement• Tighten up in-line process parameters• Control of golden tools and process route

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55nm ESF3 Macro For Auto.

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Macro Spec. HS Ver.

Application Auto

Operation temp. -40C~150C

Standby Current < 1uA @ 25C

Read Current (total) < 40mA / 110MHz

Access Time 9ns

Endurance 10K

Data Retention , 85C 10yrs

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Summary

• 55nm SST eFlash solution has been officially released and is now ramping to production. Many more T/Os are on the way.

• Derivative platforms are deployed to support IOT and auto applications.

• SONOS is a cost-effective, logic compatible technology now being developed on both 55nm and 40nm .

• UMC can customize eFlash macro performance for specific requirements.

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