solutions to common questions - logic

1 SOLUTIONS TO COMMON QUESTIONS - LOGIC EBOOK TEXAS INSTRUMENTS

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Solutions to Common QuestionsLogic

SLYY153


Introduction

This interactive e-book is designed to help you understand more about Logic devices from Texas Instruments.

Table of contents: Clicking the image within the table of content will lead you to the frequently asked questions.

Navigating between FAQs: Clicking on the upper left corner of the e-book will return to your current section. If you click the top right corner it will return you to the table of contents.

Additional information: There are opportunities to learn more about specific topics on the columns of each question.

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TOC For additional information please visit TI’s support and training for logic here.

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Table of contents

Device functionality Input parameters Output parameters Power and thermals Timing

Package and pinout Part numbers Quality and support Simulation models

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4 FREQUENTLY ASKED QUESTIONS - LOGIC EBOOK TEXAS INSTRUMENTS

1. How do you determine the output pulse width and the ‘K value’ of a monostable multivibrator?

2. Can I connect the Cext pin to ground?

3. How do I configure the SN74LVC1G123 inputs for rising/falling edge triggering?

4. How stable is the output pulse length across temperature?

5. How stable is the output pulse length across changes in VCC?

6. What is the maximum output pulse length of a monostable multivibrator?

7. Which inputs of the SN74LVC1G123 have Schmitt triggers?

8. What are some applications that use monostable multivibrators?

Device Functionality

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For additional information please visit TI’s support and training for logic here.

1a. How do you determine the output pulse width of a monostable multivibrator? What does the ‘K value’ mean for a monostable multivibrator?

The output pulse length (tw) for most monostable multivibrators is calculated with this equation:

tw = K * Rext * Cext

Rext : The external resistance value of the timing circuit for the device.

Cext : The external capacitance value of the timing circuit for the device.

K : A constant related to the specific device being used, the external component values, and the supply voltage. It is listed in the datasheet. The K value is a common source of questions because there is no defined equation to determine it. This value is typically determined through experimentation -- you can connect a monostable multivibrator using a specific Rext and Cext value and measure the output pulse, then use that measurement to calculate the K value,

K = tw / ( Rext * Cext ).

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http://www.ti.com/logic-circuit/support-training.html

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For more information about designing your system, please visit Designing with Logic application note.

Please refer to the table below. For additional information, refer to the datasheet or the Designing with the SN74LVC1G123 Monostable Multivibrator application note.

2. Can I connect the Cext pin to ground?

When considering whether or not to connect the Cext pin to ground, it is best to follow the datasheet recommendations. If your monostable multivibrator recommends not connecting Cext to ground, then do not connect it to ground.

In some monostable multivibrators the Cext pin is internally tied to ground, but in others it is not. If the datasheet is unclear and the information is required, use an ohmmeter to check the resistance between the two pins. If the resistance reads less than 1 Ω, it is safe to connect both to ground.

3. How do I configure the SN74LVC1G123 inputs for rising/falling edge triggering?

Trigger Method Selection

Desired Trigger Method A B CLR

Falling Edge INPUT HIGH HIGH

Rising Edge LOW INPUT HIGH

Rising Edge with output pulse interrupt when LOW LOW HIGH INPUT

http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

http://www.ti.com/lit/an/slva720/slva720.pdf



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HeaderDevice Functionality


4. How stable is the output pulse length across temperature?

This is a deceptively complex question. All TI monostable multivibrators are rated to operate in a particular temperature range – many from -40C° to +85C°. We have data that shows that these parts remain ± 1% accurate over this temperature range, however, that is only the accuracy for our part. There are two additional parts that will be subjected to these temperatures that will drastically affect the operation of the system – the external capacitor and resistor.

Using a Class 2 X7R 5% capacitor, you may think that your output will only sway by 5% over temperature, but don’t be fooled! That 5% is the manufacturing tolerance, not the temperature tolerance. The ‘R’ in that designator means the part will vary up to ± 15% over temperature. Also, this is not a linear effect on the pulse width.

You can use the pulse width equation to determine the expected tolerance based on the components. If K swings up to 1%, Rext by 5%, and Cext by 20% (15% temp + 5% manufacturing)

tw = K(1 + 0.01) * Rext(1 + 0.05) * Cext(1 + 0.20)

= K * Rext * Cext * (1 + 0.2726)

Note that just adding the tolerances gives 26% (20% + 5% + 1% = 26%), but the total tolerance is actually 27.26%. This is an easy trap to fall into.

So, at this point you might be wondering, “if my pulse length changes by that much, what use is a part that puts out a specific pulse length?”

Well — you can definitely mitigate these issues. By using Class 1 capacitors (very high temperature stability) and low tolerance resistors, the output can be kept with ± 2% of the expected pulse width. If greater accuracy than that is required, you will need to find a different solution.

If you recall the pulse width equation: tw = K * Rext * Cext You can use this equation to determine the expected tolerance based on the components.

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Most monostable multivibrators are only specified up to 0.1 µF, which just means that data is not available for larger capacitor values and it is recommended to test pulse lengths at the prototype stage.

5. How stable is the output pulse length across changes in VCC?

The output pulse length does change with Vcc. The amount of change is reflected in K and can be found in the plots on the part’s datasheet.

6. What is the maximum output pulse length of a monostable multivibrator?

There is no limit on resistance or capacitance in theory, but in practical applications there are some guidelines.

It’s generally a good idea to keep your resistance below approximately 1 Mohm. This is because the resistance between traces on many board can be in the 1 to 10 Mohm range, and these parasitics can cause unexpected operation.

Capacitance should be kept below approximately 1000 µF. This is to ensure that the device can fully discharge the capacitor.

By pushing the limits of both values, a pulse length of approximately 16 minutes can be achieved. Longer times are possible, but it seems that if you have reached a requirement with this length of time, a different solution would likely be better.

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A Schmitt trigger is a bistable circuit in which the output increases to a steady maximum when the input rises above a certain threshold, and decreases almost to zero when input voltage falls below another threshold.

For more information about designing your system, please visit the Understanding Schmitt triggers application note.

7. Which inputs of the SN74LVC1G123 have Schmitt-triggers?

A\ and B have Schmitt-triggers. This means that they both can handle slow or noisy inputs without creating multiple trigger events or causing damaging shoot-through current.

The CLR input is NOT a Schmitt-trigger input.

?Want to ask this team a question? Click here to post a question on the E2E Forum.

—

http://www.ti.com/lit/an/scea046/scea046.pdf


https://e2e.ti.com/support/logic/f/151

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It is best to refer to the applications report, Designing with the SN74LVC1G123 Monostable Multivibrator for applications information on these devices.

8. What are some applications that use monostable multivibrators?

Pulse stretcher - when a pulse is too short to be read properly by a device

Debounce - when a clean, single input pulse is required from a switch

Edge detector - when a pulse needs to be generated at a rising or falling edge of a signal

Long delays in logic - Logic circuits generally operate very quickly and sometimes a delay of a large value is required (milliseconds, seconds, or even minutes) to allow some action to happen (such as warming up a particular component, or allowing a physical device to move)




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Input Parameters

1. Can I leave CMOS inputs floating? What do I do with unused inputs?

2. Can VIN be higher than VCC/lower than GND? Can I apply a voltage to the input when VCC = 0?

3. What is Delta VT and how is it defined?

4. What is the transition voltage for a device with a Schmitt trigger on the input?

5. What are the IIH and IIL parameters and how are they different from Ii?

6. How does the bus-hold circuit work? What does the ‘H’ mean in a device with a name such as SN74LVCH244A?

7. How are bus-hold parameters specified?

8. How is input capacitance defined? Are there maximum specification provided for input capacitance?

9. What is hold time? How is hold time defined?

10. What is setup time? How is setup time defined?

11. What is Δt/Δv? What happens if I have a slower transition rate than specified?

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HeaderInput Parameters


For a full explanation, please read our application report entitled Implications of Slow or Floating CMOS Inputs.

Still have a question about this? Ask a related question on E2E

1. Can I leave CMOS inputs floating? What do I do with unused inputs?

Our datasheets list a maximum edge rate for input signals to CMOS devices which should not be violated, labelled as Δt/Δv in the Recommended Operating Conditions section of the datasheet.

To keep this answer short and to the point, slow or floating inputs on CMOS devices can cause excessive supply currents, oscillations, and damage to the device.

http://www.ti.com/lit/an/scba004d/scba004d.pdf


https://e2e.ti.com/p/addpost?rt=737694

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To understand more about your input signal please visit the Logic Minute informational videos.

2. Can VIN be higher than VCC/lower than GND? Can I apply a voltage to the input when VCC = 0?

This information is found in the Absolute Maximum Ratings table in the datasheet, however the data has to be interpreted.

Each device will have a maximum and minimum input voltage value given. If the VI maximum is a specific number, like “7 V”, then the input voltage is independent of VCC., meaning that a voltage higher than VCC can be applied to the input without causing damage (so long as it remains below the listed absolute maximum). However, if VCC is included in the VI absolute maximum, such as “VCC + 0.5 V,” then there is a clamp diode between that input and VCC and you cannot drive the input above VCC + 0.5 V without activating that diode.

EXCEPTION 1. On a clamped input (i.e. VI max is listed as “VCC + 0.5 V,” then the input signal can drive above VCC + 0.5 V as long as the current is limited to the value of IIK in the datasheet. This will result in current sourcing from the VCC pin, so be sure that this is not a problem for your system if you plan to make use of this exception.

EXCEPTION 2. Some devices have the Ioff specification in the datasheet (in the Electrical Specifications table),which basically mentions the conditions where VCC=0 V/0.2 V and the test conditions have input/output at 5.5 V or GND. Ioff indicates that there is protection circuitry built into the design allowing user to have inputs while VCC is turned off or 0 V . The statement of “5-V tolerant inputs” usually accompany this datasheet. With Ioff specification, even though the abs max conditions indicate forward biasing diode to VCC, you can apply any voltage at the inputs with VCC powered down.

https://training.ti.com/logicminute


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3. What is Delta VT and how is it defined?

The difference between the positive-going and negative-going input threshold voltages.

Hysteresis has been incorporated into logic devices for many years and exists in bipolar as well as CMOS circuitry. Although the circuitry is different, the implementation is the same: the input voltage threshold actually changes internally from one level to another, as the input logic level itself switches.

The benefit of a device that has built-in dc hysteresis is that, depending on the amount of hysteresis and the amount of noise present, the input is immune to such noise. This digital form of filtering out unwanted noise can be beneficial in a system where noise caused by electromagnetic interference (EMI) or crosstalk cannot be reduced.

For more information about Delta VT visit Understanding Schmitt triggers


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When should I use a Schmitt trigger? Schmitt triggers should be used anytime you need to translate a sine wave into a square wave as shown in this oscillator application. Or they should be used where a slow or noisy input needs to be sped up or cleaned up as in the switch de-bouncer circuit.

4. What is the transition voltage for a device with a Schmitt trigger on the input?

Logic parts without a Schmitt trigger on the input specify VIH, minimum input voltage level for HIGH, and VIL, maximum input voltage level for low. These values are guaranteed by TI for the device to switch at those levels.

Devices with a Schmitt trigger input switch at a threshold voltage, VT. Due to the hysteresis property of a Schmitt trigger, this threshold voltage will vary based on if the transition is positive or negative. For Schmitt triggers, the VIH should be taken as the maximum value of VT+, and VIL should be taken as the minimum of VT-.

?Need more information about Schmitt triggers? Click here to learn more!


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CMOS devices usually have only leakage current at the inputs and use the II parameter, but are measured at both low- and high- input conditions.

5. What are the IIH and IIL parameters and how are they different from Ii?

IIH – High Level Input Current – The current into an input when a high-level voltage is applied to that input.

IIL – Low Level Input Current – The current out of an input when a low-level voltage is applied to that input.

IIH and IIL typically are found only on devices with bipolar inputs that usually require a significantly different amount of pulldown current on the input to provide a logic low, rather than pullup current to provide a logic high.

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To read more technical information about the bus-hold circuit, please refer to the Bus-Hold Circuit application report.

6. How does the bus-hold circuit work? What does the ‘H’ mean in a device with a name such as SN74LVCH244A?

A bus-hold circuit is implemented in selected logic families to help solve the floating-input problem inherent in all CMOS inputs (refer to the Implications of Slow or Floating CMOS Inputs application report). The bus-hold circuit maintains the last good input state into the device and, as an additional benefit, pull-up or pull-down resistors no longer are needed. The advantages of devices with this circuit are board-space savings and reduced component costs.

Internal Circuit

VCC

GND

Q3

Q4

Q1

Q2

D2D1

D3

D4

Input

Simplified Circuit Diagram of Bus - Hold Circuit

http://www.ti.com/lit/an/scla015b/scla015b.pdf



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For additional information about the bus-hold feature, refer to the TI application report, Bus-Hold Circuit. Also, see II(hold) input hold current for further information.

7. How are bus-hold parameters specified?

IBHHO - Bus Hold High Overdrive Current – The current that an external driver must sink to switch this node from high to low.

IBHLO - Bus Hold Low Overdrive Current – The current that an external driver must source to switch this node from low to high.

IBHH - Bus Hold High Sustaining Current – The bus-hold circuit can source at least the minimum high sustaining current at VIH min.

IBHH should be measured after raising the input voltage to VCC, then lowering it to VIH min.

IBHL - Bus Hold Low Sustaining Current – The bus-hold circuit can sink at least the minimum low sustaining current at VIL max.

IBHL should be measured after lowering the input voltage to GND and raising it to VIL max.



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Ci - Input Capacitance – The capacitance of an input terminal of the device.

8. How is input capacitance defined? Are there maximum specifications provided for input capacitance?

This parameter is the internal capacitance encountered at an input of the device. The values that are given are not production-tested values. Normally, they are typical values given for the benefit of the designer. These values are established by the design, process, and package of the device. This capacitance is measured between the input pin and the ground pin of the device. We cannot guarantee a maximum input capacitance unless it is explicitly stated in the datasheet.

?Have more questions about picking the right capacitor? Click here to post a question on the E2E Forum.


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For additional information about hold time, refer to the Metastable Response in 5-V Logic Circuits application report.

9. What is th? How is hold time defined?

The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input.

NOTE 1: The hold time is the actual time interval between two signal events and is determined by the system in which the digital signal operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is to be expected.

NOTE 2: The hold time may have a negative value, in which case, the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit is to be expected.

Hold time is tested by holding an input at a fixed logic level for the specified time after the transition of the other input. The device passes if the outputs switch to their expected logic levels and fails if they do not. Hold times are not checked simultaneously with other inputs or other recommended operating conditions.

http://www.ti.com/lit/an/sdya006/sdya006.pdf


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To understand more about setup and hold time please visit the Logic Minute informational videos.


The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal.

NOTE 1: The setup time is the time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is specified.

NOTE 2: The setup time may have a negative value, in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation of the digital circuit is specified.


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If you must supply a slowly changing voltage to the input of a logic device, select a device that has Schmitt-trigger inputs. These inputs have been specifically designed to tolerate slow edges. An example of such a device in the LVC family is the SN74LVC14.

11. What is Δt/Δv? What happens if i have a slower transition rate than specified?

The rate of change of the input voltage waveform during a logic transition (low-to-high or high-to-low).

You often place external capacitors on a trace to ensure the driver does not switch rapidly from one logic state to another. This is sometimes done to prevent unwanted overshoot and undershoot voltage conditions that could cause ringing, degrade signal integrity or in switch debounce circuits. However, this could cause problems at the input. Therefore, TI provides input transition rise or fall rates. The problem may not arise due to external capacitive loading, but may be the result of choosing a device with a weak driver. In either case, the end result is a voltage waveform that is too slow for the device.

Slow transition rates wreak havoc on CMOS inputs because a slowly changing input voltage will induce a large amount of current from the power supply to ground. This phenomenon is known as through current. Through currents are normal ac transient currents, but when they are sustained indefinitely - as are those caused by slow input transition rates - the device will not perform as expected. Its output voltage may oscillate, or even worse, damage the device.

This surge of current, if large enough, will disturb the ground reference because of the inductive nature of the package [V = L × (di/dt)] and produce a positive-going glitch on the ground reference. The glitch may, in turn, reduce the relative magnitude, causing the output node of the input inverter to switch states. Ultimately, this erroneous data propagates to the output of the device, thereby causing oscillations. The more inputs that are being switched in the same manner, the worse this condition becomes, as more current is being forced into ground during a short time. TI data sheets specify the slowest input transition rate to avoid this problem. For additional information, refer to our Implications of Slow or Floating CMOS Inputs application report and Solving CMOS transition rate issues using Schmitt triggers white paper.

http://www.ti.com/lit/ds/symlink/sn74lvc14a.pdf

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=scba004

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=scba004

http://www.ti.com/lit/wp/slla364a/slla364a.pdf

Output Parameters


1. Can I combine/parallel the outputs of a device to get higher current drive?

2. What is the output of a clocked device when powered up?

3. Why does the output of the device have overshoot? How can I reduce ringing on the outputs?

4. What logic devices have series damping resistors? What advantage do series damping resistors provide?

5. What is power-up 3-state? How do I know if a device has power-up 3-state?

6. What is the output voltage (VOH or VOL) when the output current is X or the supply voltage is Y?

Output Parameters


Learn more about the initial states and solutions to it in our Power-Up Behavior of Clocked Devices application report.

1. Can I combine/parallel the outputs of a device to get a higher current drive?

Yes. Three-state, push-pull, and open-drain logic outputs may be tied to other outputs of the same chip to handle more current - so long as the inputs are tied together as well. Never drive connected outputs from separate signal sources - this is called ‘bus contention’ and can damage all devices involved. Care should be taken to not violate the maximum current ratings in the Absolute Maximum specifications.

2. What is the output of a clocked device when powered up?

The initial state of any clocked device on power up is usually unknown or undefined until a valid clock signal comes in .There are few techniques which helps in defining a state which includes using CLR and PRESET pins to define initial state regardless of clock input.

http://www.ti.com/lit/an/scha005a/scha005a.pdf

http://www.ti.com/lit/an/scha005a/scha005a.pdf

Output Parameters


3. Why does my output have overshoot? How can I reduce ringing on the outputs?

A common problem designers experience when testing a design is over/undershoot on the output of a logic part, called ringing.

Ringing typically occurs when a device is driving more current than is needed by the load. This can be fixed by choosing a logic device with lower drive capability, by adding a resistor in series with the load, or by adding a capacitor in parallel with the load. The level of drive strength varies greatly depending on logic family. Most functions are available in every logic family.

For more information: check out http://www.ti.com/lit/an/szza010/szza010.pdf

http://www.ti.com/lit/an/szza010/szza010.pdf


Output Parameters


4. What logic devices have series damping resistors? What advantage do series damping resistors provide?

Select devices in TI Logic families such as ABT, ALVC, ALVT, BCT, F, HSTL, LVC, and LVT incorporate Series Damping Resistors on the outputs.

Part Number Examples: ABT162244, ALVCHR16245

The extra `2` in ABT162244 indicates damping resistor on outputs only. The `R` in ALVCHR16245 indicates damping resistors on both A and B ports. Some device names (e.g. SN74LVCR162245) contain both `R` and `2`. Also, this means the device has integrated series damping resistors on both A and B ports.

Integrated series damping resistors reduce overshoot and undershoot by providing better impedance matching without the need for external resistors.

Learn more about the benefits of having damping resistors here.


Output Parameters


For additional information regarding Power-Up 3-State, refer to Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

5. What is power-up 3-state? How do I know if a device has power-up 3-state?

The power-up 3-state (PU3S) feature ensures the high-impedance state during power up and power down. The output enable pin (OE) must be tied high (to VCC) through an external pullup resistor to keep the outputs in 3-state during the entire power up region as shown in the image below.

If the device is specified for power-up 3-state, then it will have the IOZPD and IOZPU specifications in the electrical characteristics section of the datasheet.

PU35

6 V

3.3V

OverlapRegion

OE

loff

VCC

RPULLUP

IN OUT

OE




Output Parameters


It is important to note that the output resistance for a CMOS driver changes across supply and output current. Given that the supply voltage is held constant, the output resistance is relatively linear over the typical operating range.

6. What is the output voltage (VOH or VOL) when the output current is X or the supply voltage is Y?

There are circumstances where you might want to know a VOH or VOL value that is not given. I will describe two cases:

If you want VOH for a supply voltage that is not given (for example, 3.3V when only 3.0V is given):

In this case, it is best to use the existing data to your advantage. For example, a circuit with VOH = 2.3 V at a current of 24 mA. This is a voltage drop across the output pFET of 0.7 V. It is safe to assume that the voltage drop will be slightly less than this at higher voltages (due to decreasing resistance as supply voltage increases). Therefore, at 3.3 V supply and 24 mA output current, VOH = 3.3 V - 0.7 V = 2.6 V.

If you want VOH for an output current that is not given (for example, 10 mA at 3.0 V supply):

In this case, it is best to use the output resistance calculated from the given datasheet values. Since the value will be relatively linear, the resistance can be used to calculate VOH or VOL. Using the same example, the circuit gives VOH = 2.3 V at a current of 24 mA. To get the maximum output voltage at a current of 10 mA, first the output resistance must be calculated:

ROUT = (VCC - VOH)/IOH = (3.0 - 2.3)/0.024 = 29.167Ω

This value can then be used to determine the new voltage drop at 10 mA:

VCC - VOH = 0.01 * Rout = 0.29167 V. Solving for VOH yields: VOH = VCC ~ 0.29167 ~= 2.71 V

Power & Thermals


1. What is the maximum junction temperature for a given device?

2. Why does the device have excessive ICC? Why does the device have an ICC current larger than the datasheet specification?

3. What is ΔICC? How does ΔICC affect current consumption?

4. Can you provide θJC (or other thermal impedances) for a given device?

5. What is the TA specification? Can I go beyond the TA specification if the TJ is higher? What might happen to the device if I exceed TA?

6. What is Cpd (power-dissipation capacitance) and how can I use it to calculate power consumption?

Power & Thermals


If you are interested in learning more about power dissipation in logic devices, please read our CMOS Power Consumption and Cpd Calculation application report.

1. What is the maximum junction temperature for a given device?

The vast majority of logic devices do not list a maximum junction temperature (TJ(max)) on the datasheet.

For logic devices, TJ(max) is equal to the maximum storage temperature (Tstg(max)) as listed in the Absolute Maximum Ratings table of the datasheet unless otherwise specified.

http://www.ti.com/lit/an/scaa035b/scaa035b.pdf


Power & Thermals


Notice the ICC is highest when the IN voltage is about halfway between VCC and GND

2. Why does the device have excessive ICC? Why does the device have an ICC current larger than the datasheet specification?

If you are observing excessive ICC, confirm that all control inputs are being held at one of two rails: VCC or GND level. Control inputs include OE, IN, Select pins and inputs of any type of combinational or sequential logic. Output pins are excluded, however, they could be the cause of high current consumption if there is bus contention at the outputs.

If a control input is somewhere between VCC and GND, there can be partial turn-on of both NMOS and PMOS transistors. In some cases, this can provide a slightly lower parasitic impedance to GND from the supply voltage, which can increase the current consumption. Shown is an example of ICC vs. VIN for a signal switch control input (IN) when the switch is operating at 1.95 V VCC.

ICC (uA)6.00

0.50/dv

-.500.00 0.20/dv

VIN (V)

Material: HIGH

2.00

Power & Thermals


Refer to the Understanding and Interpreting Standard-Logic Data Sheets application note for more information and definitions.

3. What is ΔICC? How does ΔICC affect current consumption?

Delta Icc specification in the datasheet relates to the increase in the supply current consumption when one on the inputs is not at the rails. Usually, VIN = Vcc - 0.6 V is taken as one of the inputs, but it could change from device to device.

4. Can you provide θJC (or other thermal impedances) for a given device?

The θJA, θJC, and other thermal impedance values should be contained in the datasheet within the thermal information section. If a datasheet does not contain the required information, please create a post on the E2E section and we will be able to provide the thermal impedance values within one to two weeks.

http://www.ti.com/lit/an/szza036c/szza036c.pdf




Power & Thermals


5. What is the TA specification? Can I go beyond the TA specification if the TJ is higher? What might happen to the device if I exceed TA?

The TA range is the range of free air temperatures within which our devices are specified. The functionality and specifications of our devices are not guaranteed outside of operating conditions.

It is not recommended to exceed the TA specification, even if the TJ specification is met. In this case, the device functionality is not guaranteed and we cannot theorize if the device will fail or not and furthermore cannot address potential failure modes.

6. What is Cpd (power-dissipation capacitance) and how can I use it to calculate power consumption?

This parameter is the equivalent capacitance used to determine the no-load dynamic power dissipation per logic function for CMOS devices.

PD = Cpd (Vcc)² f + Icc Vcc

The Cpd test is a measure of the dynamic power a device requires with a specific load. The values given on the data sheet are typical values that are not production tested. These values are defined by the design and process of the device. For more information on Cpd, refer to the CMOS Power Consumption and Cpd Calculation application report.


Timing


1. What is the difference in timing between gates in the same device? How much skew is expected within a given logic device? What is the part-to-part skew?

2. What is the fMAX value for a given device? What is the maximum operating frequency of a device where fMAX is not specified?

3. What is tPZH?

4. What is tPZL?

5. What is hold time? How is hold time defined?


Timing


1. What is the difference in timing between gates in the same device? How much skew is expected within a given logic device? What is the part-to-part skew?

Some logic devices contain a tsk specification in the datasheet, please refer to this specification in the switching characteristics table for the skew measurement.

For any TI logic devices that do not specify a skew parameter, it is safe to assume that the skew will be ≤ 1ns typical between channel outputs when driving into equal loads within the same chip. We do not guarantee any part-to-part skew.

?Want to ask this team a question? Click here to post a question on the E2E Forum.

JEDEC Standard 65 (EIA/JESD65) Defines skew as “the magnitude of the time difference between two events that ideally would occur simultaneously.”


Timing


The fmax and fclock parameters are two sides of the same coin. The fclock parameter tells you, the user, how fast you can reliably switch the input to the device. The fmax parameter informs TI when to reject a device that fails to function below a minimum speed.

2. What is the fMAX value for a given device? What is the maximum operating frequency of a device where fMAX is not specified?

fMAX is the highest rate at which the clock input of a bistable circuit can be driven through its required sequence, while maintaining stable transitions of logic level at the output with input conditions established that should cause changes of output logic level in accordance with the specification.

The fMAX value is the value of the upper limit of the fclock specification, and is specified in the data sheet as a minimum limit. The circuit is specified to operate up to the minimum frequency value. See fclock for additional fMAX testing information. Due to test-machine capability limitations, it may be necessary to test fMAX or minimum recommended operating conditions (i.e., pulse duration, setup time, hold time) in accordance with the following paragraph.

The fMAX parameter may be tested in either of two ways. One method is to test simultaneously the responses to the symmetrical clock-high and clock-low pulse durations that correspond to the period of the specified minimum value of fMAX. The second method is to test individually the responses to the minimum clock-high and clock-low pulse durations under specified load conditions. A pulse generator is used to propagate a signal through the device to verify device operation with the minimum pulse duration. When clock-high and clock-low pulse durations are equal to or less than the corresponding fmaxpulse duration, fmax testing suffices for testing clock-high and clock-low pulse durations.

Timing


3. What is tPZH? What is the propagation delay time for changing from 3-State to High/Low output?

tPZH – Enable Time (of a 3-State Output) to High Level – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined high level.

This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined high level. Output enable time, tPZH, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a high logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZH, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pulldown resistor to obtain a valid logic-low level when the output is in the high-impedance state.

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ

OutputWaveform 1S1 at VLOAD

OutputWaveform 2S1 at GND

VOL + VΔ

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing


4. What is tPZL? What is the propagation delay time for changing from 3-State to High/Low output?

tPZL – Enable Time (of a 3-State Output) to Low Level – The time interval between the specified reference points on the input and output voltage waveforms, with the 3-state output changing from the high-impedance (off) state to the defined low level.

This parameter is the propagation delay time between the specified reference point on the input voltage waveform and the specified reference point on the output voltage waveform, with the 3-state output changing from the high-impedance (off) state to the defined low level. Output enable time, tPZL, is tested by generating a transition on the specified input that will cause the designated output to switch from the high-impedance state to a low logic level. Trip points used for the timing measurements and output loads used during testing are defined in the individual data sheets in the parameter measurement information section, typically found after the switching characteristics over recommended ranges of supply and operating free-air temperature table. Output enable time, tPZL, is not checked simultaneously with other outputs or with other recommended operating conditions. Outputs not being tested should be set to a condition that minimizes switching currents. The tested output load includes a pullup resistor to obtain a valid logic-high level when the output is in the high-impedance state.

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing


For additional information about hold time, refer to the Metastable Response in 5-V Logic Circuits application report.

5. What is th? How is hold time defined?

The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input.

NOTE 1: The hold time is the actual time interval between two signal events and is determined by the system in which the digital signal operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is to be expected.

NOTE 2: The hold time may have a negative value, in which case, the minimum limit defines the longest interval (between the release of the signal and the active transition) for which correct operation of the digital circuit is to be expected.

Hold time is tested by holding an input at a fixed logic level for the specified time after the transition of the other input. The device passes if the outputs switch to their expected logic levels and fails if they do not. Hold times are not checked simultaneously with other inputs or other recommended operating conditions.

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing Input VM

VI

0 V

VM VM

VI

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tsu

Data Input

th



Timing


6. What is tsu? How is hold time defined?

The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal.

NOTE 1: The setup time is the time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval for which correct operation of the digital circuit is specified.

NOTE 2: The setup time may have a negative value, in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation of the digital circuit is specified.

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

VMOutput Control VM

VI

0 V

VM

VM

VLOAD/2

VOL

tPZL tPLZ

VOH - VΔ VOH

≈ 0 V

tPZH tPHZ



VOL + VΔ

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Timing Input VM

VI

0 V

VM VM

VI

0 V

tsu

Data Input

th

Package & Pinout


1. How should the thermal pad on my device be connected? Can the thermal pad be left floating or should it be attached to ground?

2. How can I tell what part I have based on a part marking? What is the device part marking for a specific device?

Package & Pinout


1. How should the thermal pad on my device be connected? Can the thermal pad be left floating or should it be attached to ground?

Unless otherwise noted in the datasheet, the thermal pad may be connected to the ground plane or left floating. It is not recommended to have the thermal pad connected to any signal traces.

2. How can I tell what part I have based on a part marking? What is the device part marking for a specific device?

To search a TI part number from the top-side marking of a physical part, visit the TI Part Mark search page: http://www.ti.com/packaging/docs/partlookup.tsp.

If there is a suspected device, then the Package Option Addendum in the datasheet provides the device markings for a given device.

For additional information please visit TI’s support and training for logic here.

http://www.ti.com/packaging/docs/partlookup.tsp


Part Numbers


1. Why does a device have an E4/G4 suffix? What is the difference between SN74xxG4 and SN74xx?

2. Can you help me understand the Logic device part numbers? There are so many part numbers, is there a logic part number naming convention?

3. What is Little Logic? Is there a part naming convention for Little Logic?

Part Numbers


1. Why does a device have an E4/G4 suffix? What is the difference between SN74xxG4 and SN74xx?

In short, there will be no difference between a device labelled SN74xxG4 and SN74xx.

Historically, G4 and E4 suffixes meant that the devices were rated to be “Green” or “Lead Free.” However, as time has passed, all devices have been pushed to these new “Green” or “Lead Free” standards, but the specific part orderables have remained available so that customers have had a consistent orderable part number.

To check on the “Green” status of a part, you can enter your part number on our Material Content Search Tool page.

For definitions of E4, G4 suffixes, please refer to our Environmental Information and Environmentally Friendly Solutions from TI pages.

You can also refer to the end of the datasheet in the Part Orderable Addendum to see the “Eco Plan” of a specific part orderable, where the terminology is defined by the following document: Green and Lead Free Definitions.

http://www.ti.com/quality/docs/materialcontentsearch.tsp

http://www.ti.com/lsds/ti/quality/environmental_info/lead-free/lead_free_conversion.page

http://focus.ti.com/pdfs/logic/Environmentally_Friendly_Solutions.pdf

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szzq088&fileType=pdf&keyMatch=szzq088&tisearch=Search-EN-Everything

Part Numbers


Anatomy of a Logic Part Number

2. Can you help me understand the Logic device part numbers? There are so many part numbers, is there a logic part number naming convention?

SN74 ABT H 16 2 224 A DGG R Standard PrefixMilitary (54) Commercial (74)

FamilyABT/EAC/ACTAHC/AHCT ALBALSALVCALVTASAUCAUPAVCBCTCBT/LV/CB3xCD4000FFB

FCTGTLGTLPHC/HCTHSTLLSLV-A LVCLVTSSSTL SSTU SSTV/SSTVFTTL TVCVME

Special FeatureBlank = no special featuresA, B, C = Configurable VCCD = Level Shifting Diode H = Bus Hold K = Undershoot Clamp R = Damping Resistor on Inputs/ Outputs S = Schottky Clamping Diode Z = Power Up 3 State

Package TypeD,DW = SOIC DB, DL = SSOPDBB,DGV = TVSOPDCT, DCU = TSSOP DBV, DCK = SOT DGG, PW = TSSOPFK = LCCCGB = PLCC GKE,GKF = LFBGA GQL = VFBGA HFP, HS, HT, HV = CQFP J, JT = CDIP N, NP, NT = PDIP PAG, PAH, PCA, PCB, PM, PN, PZ = TQFP PH, PQ, RC = QFP RGY, RGQ = QFN W,WA, WD = CFP YEP, YZP = DSBGA

Bit Width Blank = Gates, MSI, and Octals1G = Signal Gate 2G = Dual Gate 3G = Triple Gate 8 = Octal IEEE 1149 (JTAG) 16 = Widebus™ (16,18, and 20) 18 = Widebus IEEE 1149.1 (JTAG)32 = Widebus+™ (32 and 36 bit)

OptionsBlank = No Options2 = Series Damping Resistor on Output 3 = Level Shifter4 = Level Shifter25 = 25Ω Line Driver

Standard 7400 Logic Functions

Device RevisionBlank = No RevisionLetter Designator A - Z

Tape & ReelR = 3000 unitsT = 250 units

https://training.ti.com/tlm-bol-partnumber?cu=1134826

https://training.ti.com/tlm-bol-partnumber?cu=1134826

Part Numbers


Want to learn more about Little Logic? Check out our Little Logic Guide.

To learn how to select the correct Little Logic, visit the application note here.

3. What is Little Logic? Is there a part naming convention for Little Logic?

ASICHigh Low

SingleGate

SingleGate

High

Dual-Gate8-pin DCU11,8 mm2

Up to 35% less space

Quad-Gate14-pin TSSOP

33,66 mm2

Up to 35% less spaceSingle-Gate

5-pin YEA1,26 mm2

Up to 96% less space

Low

Principle Naming

Tape & ReelR = 3000 pieceT = 250 piece

Package TypeYEP = NanoStar™ (230u)YZP = NanoFree™ (230u)DCK = SC-70DBV = SOT-23DBV = SOT-23DCU = US-8DCT = SM-8

Logic Functhinxx

Gate Count1G - Single Gate2G - Dual Gate3G - Triple Gate

Product FamilyAHC/T, AUC, AUP,CBT, LVCStantard Prefix

SN74 LVC 1G xx YEP R

http://www.ti.com/lit/sg/scyt129g/scyt129g.pdf

http://www.ti.com/lit/sg/scyt129g/scyt129g.pdf

http://www.ti.com/lit/an/scya049a/scya049a.pdf


Quality & Supply Chain

1. Where can I find general information regarding the quality and reliability of TI devices?

2. Where can I find more information about product change notifications?

3. What is the reflow profile for “device name”?

4. What are the limits for hand soldering “device name”?

5. How does TI implement it’s Tin plating process? I see that some devices use Tin plating for their leads, are there measures that TI takes to ensure that there is no Tin whisker growth?

6. When will “device name” be obsoleted?



1. Where can I find general information regarding the quality and reliability of TI devices?

Many questions regarding the quality and reliability of TI Devices can be found at http://www.ti.com/quality.

Additionally, the quality page has it’s own set of FAQs that you can access at http://www.ti.com/lsds/ti/quality/faqshome.page.

2. Where can I find more information about product change notifications?

Information on product or process change notifications for all TI SC business groups can be found on the PCN home page.

http://www.ti.com/quality

http://www.ti.com/lsds/ti/quality/faqshome.page

http://www.ti.com/lsds/ti/quality/quality_policies_procedures/product_change_notification.page



3. What is the reflow profile for “device name”?

We do not have reflow information for specific devices, but our parts are qualified to the JEDEC J-STD-020.

Please refer to the following links for more information:

• http://www.ti.com/lit/an/snoa550e/snoa550e.pdf

• http://www.ti.com/lsds/ti/packaging/packaging_resources/SMT_and_application_notes.page

4. What are the limits for hand soldering “device name”?

Some devices have specific information for temperature and duration of temperature applied to the device. This information would be found in the Absolute Maximum Ratings Table for the device and is typically described as “Lead temperature 1,6 mm (1/16 in) from case.”

If this information is not provided in the datasheet, please refer to the AN-2029 Handling and Process Recommendations application report which describes the recommended handling and process conditions.

Additionally, our Surface Mount Package Removal application note discusses SMT package removal.

http://www.ti.com/lit/an/snoa550e/snoa550e.pdf

http://www.ti.com/lsds/ti/packaging/packaging_resources/SMT_and_application_notes.page

http://www.ti.com/lsds/ti/packaging/packaging_resources/SMT_and_application_notes.page



http://www.ti.com/lit/an/slva439a/slva439a.pdf



5. How does TI implement it’s Tin plating process? I see that some devices use Tin plating for their leads, are there measures that TI takes to ensure that there is no Tin whisker growth?

TI’s Tin plate process meets and exceeds qualification and monitoring standards set in JESD201, with Class 1 and Class 2 levels inspection per JESD 22A121. In addition, TI has taken the following actions for Tin plating products to meet JESD201 Class 2 requirement:

• Leadframe base material (alloy) control

• Tin plating control (chemistry, process and thickness)

• Post-plate annealing (150° C minimum within 24 hours of plating)

TI uses leadframe materials such as Cu194, Cu7025, TAMAC2 and TAMAC4.

As a whisker mitigation measure, TI anneals all of its tin plated, leadframe-based packages for 1 hour at 150°C within 24 hours of plating. This is the industry-accepted method for controlling whisker growth.

Please find additional information about lead finish and tin plating on our Lead finish composition & Tin plating process page.

http://www.ti.com/support-quality/environmental-info/lead-finish-tin-plating.html

http://www.ti.com/support-quality/environmental-info/lead-finish-tin-plating.html



6. When will “device name” be obsoleted? What is the lifecycle of “device name?”

Page 7 of TI’s General Quality Guidelines, describes our official policy on obsoleting a device is described. This policy is also summarized below.

• TI’s Product withdrawal/discontinuance process complies with J-STD-048, latest issue.

• TI makes an effort to not obsolete products out of convenience.

• TI’s obsolescence withdrawal schedule provides a longer lead time than the industry standard.

• TI allows 12 months for the last order and an additional 6 months to take final delivery of obsolete items.

• In rare circumstances, an accelerated withdrawal schedule may be necessary. In such cases, TI will communicate the last buy and final delivery dates in the EOL notice, along with an explanation of the circumstances necessitating the early withdrawal.

http://www.ti.com/lit/ml/szzq076j/szzq076j.pdf


Simulation modules

1. Where can I find simulation models for logic devices?

Simulation models for a device are located under the “Tools & software” tab in the product folder of a device.

Our WEBENCH Design Center also has searchable model libraries.

If we do not have the model you desire, please contact your local TI field sales office and work with your FAE or TSR on the request if you have an account with us.

http://webench.ti.com/webench5/spicemodels/

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

http://www.ti.com/legal/termsofsale.html

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