software engineering 2da4 slides 5: number representation

Software Engineering 2DA4

Slides 5: Number Representation andArithmetic Circuits

Dr. Ryan Leduc

Department of Computing and Software

McMaster University

Material based on S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Ed.

c©1999-2021 R.J. Leduc, M. Lawford 1

Representation of Numbers

◮ The familiar way of representing numbers is to use 10 digits(0, 1, . . . , 9). Such numbers are called base-10, or decimalnumbers.

◮ e.g. 4831

◮ Note: the term “base” is sometimes called “radix” ie.radix-10

◮ The position of each digit represents a “power” of the base(10):

4831 = 4× 103 + 8× 102 + 3× 101 + 1× 100

◮ In logic circuits it is awkward to directly represent digits like 4,8 & 3. We want only 2 digits - 0, 1.

◮ Therefore we will use base-2, or binary numbers


Binary Integers◮ We will first only deal with unsigned (+ve) integers.

◮ Binary numbers also use positional notation. Each digitrepresents a “power of 2”. e.g.:

1101 = 1× 23 + 1× 22 + 0× 21 + 1× 20 = (13)10

◮ Since the meaning of a digit depends on the base being used,we sometimes write (1101)2, or (4813)10.

◮ Each binary digit is called a bit. Four bits is called a nibble,and eight is called a byte.

◮ The largest number that can be represented in n bits is 2n − 1as zero takes up a spot.

(1111)2 = (15)10 (1111 1111)2 = (255)10

◮ For unsigned numbers, the rightmost bit is called the leastsignificant bit (LSB) and the leftmost bit the most significantbit (MSB).


Counting in Binary◮ In decimal counting when digits are all 9’s you add another

digit (e.g. (99)10 + 1 = (100)10).

◮ Similarly in binary, when digits are all 1’s you add anotherdigit (e.g. (11)2 + 1 = (100)2).

Decimal counting binary decimal eq.0 00 01 01 1... 10 29 11 310 100 411 101 5... 110 6

99 111 7100 1000 8

... 1001 91010 10c©1999-2021 R.J. Leduc, M. Lawford 4

Converting between Decimal and Binary

◮ For decimal number D = dk−1 . . . d1d0 with value (V )10.Want to convert to binary number B = bn−1 . . . b2b1b0

◮ We would have:

V = bn−1 × 2n−1 + . . .+ b2 × 22 + b1 × 21 + b0 × 20

◮ We next note that if we divide V by 2 we get:

V

2=

bn−1 × 2n−2 + . . .+ b2 × 21 + b1 × 20︸︷︷︸

Q1 +

b02

︸︷︷︸

0 or 0.5

◮ With integer division, no fractions. Just quotient andremainder. Above, Q1 is the quotient and b0 ∈ {0, 1} is theremainder (ie. V −Q1 × 2)


Converting between Decimal and Binary - II◮ Thus, if we divide (V )10 by 2, the remainder is b0, the LSB of

B.

◮ We next note Q1 is also a binary number. If we divide Q1 by2, we get b1 as the remainder.

◮ If we repeat until ourquotient is 0, we canextract every digit of B.


Octal and Hexadecimal Numbers

◮ Have looked at radixes (bases) 10 and 2.

◮ Can have any radix r.

◮ Thus have number K = (kn−1kn−2 . . . k1k0)r

◮ Has base 10 value ofV (K) = Σn−1

i=0ki × ri

◮ For digital logic, we are interestedin octal (radix-8) and hexadecimal(radix-16).


Octal and Hexadecimal Numbers - II◮ Why? Easy to convert between binary and octal or

hexadecimal. They are more compact (for humans to use).

◮ A 16 digit binary number is only a 4 digit hexadecimalnumber.


Arithmetic Circuits: Addition◮ First, consider adding just 2 bits:

0+0

00

0+1

01

1+0

01

1+1

10

x+y

c s

◮ c is the carry bit and s is the sum bit.

◮ Problem: Design circuits to produce s, c

x y c s

0 0 0 00 1 0 11 0 0 11 1 1 0

c = xy

s = xy + xy= x⊕ y


Half Adder

◮ We have: c = xy and s = xy + xy = x⊕ y

◮ Implements a half adder.


Adding Multiple Bits

◮ Consider:

X = x4x3x2x1x0 15 01111Y = y4y3 y2 y1y0 +10 +01010

c5c4 c3 c2 c1 c0 25 011100 Carries

s4 s3 s2 s1 s0 11001 Sum

◮ For each pair of bits at position i (ie. for i = 1, we have x1and y1), the addition operation may contain a carry in (ci)from position i− 1. Typically, c0 is set to 0.

◮ Before, we designed a circuit by specifying a full truth table.Adding two 5-bit numbers would require 210 = 1024 rows!

◮ Instead, we consider input bits xi and yi and carry in fromprevious column, ci, for arbitrary position i.

◮ We want to determine sum bit si and carry out ci+1.


Full Adder Circuit

ci xi yi ci+1 si0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

◮ Using K-map, it is easy to show that

ci+1 = xiyi + cixi + ciyi


Full Adder Circuit - II

ci xi yi ci+1 si0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

◮ For si, observe that:

when ci = 0, si = xi ⊕ yiwhen ci = 1, si = xi ⊕ yi

◮ Therefore: si = ci(xi ⊕ yi) + ci(xi ⊕ yi)

= ci ⊕ (xi ⊕ yi)

= ci ⊕ xi ⊕ yic©1999-2021 R.J. Leduc, M. Lawford 13

Full Adder Circuit - III◮ Speed determined by ci+1 path with 2 gate delay.


n-bit Ripple Carry Adder◮ To make an n-bit adder circuit:

◮ Connect n FAs with ci’s connected.

◮ Because the output carry from each FA block “ripples” fromright-to-left, this is known as a “ripple carry adder”.

◮ Let 2∆t be the delay for change at input to reach carryout ofa single full adder.

◮ Worst case delay of an n-bit adder is thus 2n∆t


Making Adders in Verilog

◮ Write boolean eqns for sum & carry of Full adder. Theninstantiate these to make an n-bit adder. (Figure 3.23) Usethis for lab 3.

◮ Can also use + operator.


Signed Numbers◮ This is the idea used in computers to represent −ve values in

binary. e.g. using 3 bits:

3−4

−1

011+100

111 = −1

◮ #’S from 000 → 011 are +ve’S from 100 → 111 are −ve

◮ The leftmost bit is used as the sign bit. The number is −vewhen this digit = 1.

◮ Basic idea: For an n-bit signed number

bn−1

︸︷︷︸

sign

bn−2 . . . b1b0︸︷︷︸

magnitude

bn−1 = 1 for −ve, 0 for +ve.c©1999-2021 R.J. Leduc, M. Lawford 17

Sign and Magnitude Representation

◮ Left most bit is sign bit.

◮ 0: positive number

◮ 1: negative number

◮ The remaining digits represent magnitude.

◮ ie. +5 = 0101 -5 = 1101

◮ Problem: To add a +ve and -ve number, must first compareto determine largest, then subtract smallest from largest. Toocostly.


1’s Complement

◮ For n-bit negative number K, the 1’s complement, K1, isdefined as below. The magnitude of K is |K|.

K1 = (2n − 1)− |K|

◮ Can also determine this by complementing each bit.

◮ Problem: Sometimes needs extra step when adding +ve and-ve numbers.


2’s Complement

◮ Method normally used.

◮ For n-bit negative number K, then 2’s complement, K2 isdefined as follows:

K2 = 2n − |K|

◮ For n = 4, and K = −5, we get 10000− 0101 = 1011

◮ For an n-bit number, the smallest negative number that canbe stored is −2n−1 and the largest positive number is2n−1 − 1.


Shortcuts for 2’s Complement◮ Def: Given an n-bit vector P , the 1’s complement of P ,

denoted P is obtained by complementing each bit of P .

◮ Short-cut to compute 2’s complement:

K2 = K1 + 1 = |K|+ 1

◮ For (-52), K2 = 52 + 1= 0011 0100 + 1= 1100 1011 + 1= 1100 1100

◮ Shorter-cut to compute 2’s complement:Examine bits of |K| right-to-left. Copy bits of |K| up to andincluding 1st bit that is 1 & complement the rest:

|K| =

complement︷︸︸︷

00110 100︸︷︷︸

copy

K =

complemented︷︸︸︷

11001 100︸︷︷︸

copied


2’s Complement Addition

(+5)+(+2)

(+7)

0101+0010

0111

(−5)+(+2)

(−3)

1011+0010

1101

(+5)+(−2)

(+3)

0101+1110

61 0011

(−5)+(−2)

(−7)

1011+1110

61 1001

◮ Using 2’s complement representation, we get the correct resultby simple addition. For last two, we can ignore the carry outs.


Subtraction

◮ What’s easiest way to subtract using 2’s complementnumbers?

◮ To find X − Y , find the 2’s complement of Y and add to X.Consider:

(+5)−(+2)

(+3)

0101−0010

(+5)⇒ +(−2)

(+3)

0101+1110

610011


Subtraction - II

◮ Want to re-use our adder to create an add/subtract circuit.

◮ We will use fact that 2’s complement of number K can becalculated

◮ as follows:

K2 = 2n − |K|

= 2n − 1− |K|+ 1

= K1 + 1


Adder/ Subtractor

◮ We want to calculate either X + Y or X − Y with a singlecircuit.

◮ For input Y , we want to be able to select from Y for addition,or the 2’s complement of Y for subtraction.

◮ We can do this using an XOR gate as shown below:

ADD/SUB Y f

0 0 0 Y0 1 1 Y

1 0 1 Y

1 1 0 Y

◮ So, if signal ADD/SUB = 1, we can generate the bitwisecomplement of Y (ie 1’s complement of Y ).


Adder/ Subtractor - II

◮ To generate the 2’s complement of Y , all that remains is toadd 1.

◮ This can be achieved by connecting signal ADD/SUB to theinitial carryin of the adder.


Arithmetic Overflow◮ Consider again n-bit signed numbers.

◮ Basic idea: For an n-bit signed number.

bn−1

︸︷︷︸

sign

bn−2 . . . b1b0︸︷︷︸

magnitude

◮ 2’s complement can be used to represent #s in the range:

−(2n−1) ≤ # ≤ 2n−1 − 1

◮ We refer to the rightmost n− 1 bits that represent magnitudeas the significant bits.

◮ Q: How do we know if addition of two numbers resulted in anumber that is too “big” to be represented by the n− 1 bits?(i.e. we overflow the number of bits)

◮ A: Compare last internal carry cn−1 and carry out bit cn.


Overflow cases for 3 bits

◮ Consider 3-bit case (−4 ≤ # ≤ 3):

(+3)+(+2)

(+5)

5 > 3

011+010

101c2 = 1c3 = 0

(−3)+(+2)

(−1)

−4 ≤ −1 ≤ 3

101+010

111c2 = 0c3 = 0

Overflow No Overflow

(+3)+(−2)

(+1)

−4 ≤ 1 ≤ 3

011+110

61 001c2 = 1c3 = 1

(−3)+(−2)

(−5)

−5 < −4

101+110

61 011c2 = 0c3 = 1

No Overflow Overflow!

◮ Overflow occurs when c2 6= c3, or c2c3 + c2c3. i.e. c2 ⊕ c3.


Overflow cases for 3 bits - II

◮ For n bit adder, check cn−1 ⊕ cn

◮ Therefore can add one 2-input XOR gate to Add/Sub circuitto check for overflow.


Overflow and Software

◮ Software runs on digital logic devices. Programminglanguages define variables of a specific bit size. ie. unsignedchar in ’C’ defines positive integers stored in 8 bits.

◮ For unsigned 8 bit number, largest value that can be stored is255 (28 − 1).

◮ Try:

unsigned char i,j, result;i = 255;j = 255;result = i+j;

◮ The answer should be 510, but that doesn’t fit into 8 bits, soonly the last 8 bits (11111110) get stored; thus result = 254.


Overflow and Software - II

◮ In ’C’, one must check the size of the operands beforehand tomake sure they are not too large.

◮ In assembly, can check processor status bit after operation tosee if overflow occurred.

◮ In floating point, IEEE standard defines several floating pointflags.

◮ After several computations, can test to see if any overflowoccurred during these operations.

◮ On a Sun workstation, see: man floatingpoint for more info.


Performance Issues◮ Speed of a circuit is limited by the longest delay of the

possible paths from inputs to outputs.

◮ The path with the longest delay is called the critical path.

◮ For full adder, it is from either input to output ci+1, with 2gate delay.

◮ For n-bit ripple-carry adder, the critical path delay is 2n gatedelays.


Carry-Lookahead Adder

◮ Delay from a ripple-carry adder comes from waiting for thecarry signal to propagate. Need faster approach.

◮ Carry out for stage i is ci+1 = xiyi + xici + yici

◮ Factoring expression gives:

ci+1 = xiyi + (xi + yi)ci

◮ Can rewrite as below with gi = xiyi and pi = xi + yi.

ci+1 = gi + pici

gi: When gi is 1, ci+1 is 1, independent of ci. Hence, giis called the generate function.

pi: When pi is 1, ci is propagated to ci+1. Hence pi iscalled the propagate function.


Carry-Lookahead Adder - II◮ Consider Ripple Carry Adder below.

◮ For ith carry out bit ci, worst case gate delay is:

(2i+ 1)× (delayfor1gate)


Carry-Lookahead Adder - III

◮ Consider c2:

c1 = g0 + p0c0 (3 gate delays)

c2 = g1 + p1c1 (c1 delay +2 = 5 gate delays)

= g1 + p1(g0 + p0c0) (3 + 2 = 5 gate delays)

◮ Using the distributive law c2 can be rewritten to reduce gatedelays

c2 = g1 + p1g0 + p1p0c0

◮ Which requires only 3 gate delays (max) - (i.e. 1 to computep0 = x0 + y0, 1 to compute p1p0c0 and 1 to compute final +).


Carry-Lookahead Adder - IV

◮ Both c1 and c2 take 3 gate delays.

◮ Now s1 and s2 critical path with 4 gate delays.


General Carry-Lookahead Adder◮ Using the same trick:

c1 = g0 + p0c0

c2 = g1 + p1c1

= g1 + p1g0 + p1p0c0

c3 = g2 + p2c2

= g2 + p2g1 + p2p1g0 + p2p1p0c0

c4 = g3 + p3c3

= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

◮ The carry out of any stage takes 3 gate delays. This is calleda carry look-ahead adder.

◮ After 1 gate delay all generate (g0, g1, g2, g3) and propagate(p0, p1, p2, p3) functions are valid. After 2 more gate delays,all carries c1, c2, c3, c4 are valid.

◮ Can generalize to:

ci+1 = gi + pigi−1 + pipi−1gi−2 + . . .+ pipi−1 · · · p2p1g0 +

pipi−1 · · · p1p0c0c©1999-2021 R.J. Leduc, M. Lawford 37

Fan-in Problem

◮ For c8 of a carry-lookahead adder, would require fan-in of 9!

◮ If max fan-in 4, could factor but would introduce 2 additionalgate delays.

◮ Solution: Hierarchical carry-lookahead adder.

◮ Each block is a carry-lookahead adder, with ripple-carrybetween blocks.


Other number Representations: Fixed Point

◮ Method to represent real numbers in digital hardware.

◮ Number represented as an n-bit integer part, and a k-bitfractional part. This means the decimal point is fixed.

◮ For binary number: B = bn−1bn−2 . . . b1b0.b−1b−2 . . . b−k, itsbase-10 value is:

V (B) = Σn−1

i=−kbi × 2i

◮ For B = 000.0001001, if n = 4, and k = 3, we would get0000.000

◮ Limited usefulness.


Floating Point Numbers

◮ To represent a number as fixed point, require a digit for eachposition.

◮ Representing 2376× 10−78 would require many zeros...

◮ Floating point method represents numbers by a mantissacontaining the significant digits plus an exponent of Radix R:

Mantissa×RExponent

◮ Numbers are often normalized so that the decimal place is tothe right of the leftmost digit. ie. 5.234× 1043 or6.31× 10−28.


IEEE Floating Point Formats

◮ Two main representations are the IEEE single-precision 32 bitformat and the IEEE double-precision 64-bit format.


Floating Point Numbers - II

◮ Numbers are normalized so that most-significant bit is a 1.

◮ Base 10 value for single-precision number is:

V =+

− 1.M × 2Exponent

◮ The exponent is stored in “excess 127” format so that E isunsigned and ranges from 0 to 255. Thus Exponent = E -127

◮ The value of E = 0 is defined to be “exact zero” andE = 255 to be infinity. This means Exponent can go in range−126 to 127.

◮ Example: (13)10 = (1101)2 = 1.101× 23, E = 130

◮ Single-precision: 0 10000010 1010 . . . 0 = 0EM


Binary-Coded-Decimal

◮ Encode decimal numbers as 4 bit unsigned binary numbers.

◮ ie. 4 = 0100, 9 = 1001 thus (49)10 would be 01001001

◮ Bit patterns 1010 to 1111 are unused and thus wasted.

◮ Once common means of representations as easy to convert todigits for display.

◮ Drawbacks: complex logic for arithmetic operations, andwasted six code patterns.


ASCII Character Code◮ ASCII stands for American Standard Code for Information

Interchange.

◮ Uses 7 bits to represent a character: ie 0110001 is ’1’ and1010111 is ’W’

◮ Numbers run from 0110000 (’0’) to 0111001 (’9’).

◮ Letters run from 1000001 (’A’) to 1011010 (’Z’) and similarlyfor ’a’ to ’z’.

◮ Can sort letters by comparing the numeric value of theirASCII code.

◮ Characters that are numbers or letters are called alphanumericcharacters.

◮ Also contains punctuation and nonprinting characters like BEL(audible signal) and LF (Line feed).


ASCII Character Code - II


Parity

◮ Numbers are stored as 8 bits, not 7.

◮ The eighth bit (called the p bit) is normally used for a type oferror detection called parity.

◮ Purpose is to detect transmission error when a single bit isread as its complement. ie. Sent a 0 but receive (due tonoise) a 1!

◮ Two types of parity:

Even Parity: p bit assigned so that the total number of 1’s iseven. ie for 0110100. Currently have 3 1-bits (odd),so we set p = 1 to give 10110100 (4 1-bits - even).


Parity - II

Odd Parity: p bit assigned so that the total number of 1’s is odd.ie for 0110100. Set p = 0 to give 00110100 (3 1-bits- odd).

◮ Only can detect an error if an odd number of errors hasoccurred.


software engineering 2da4 slides 5: number representation

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