soc u1- cpu arch-part1
TRANSCRIPT
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INTERNALARCHITECTURE
INTELs 8051
ORGANIZATION
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Controllers Vs Processors:Micro - Controller Single board Micro-computer
( full fledged) on a single chip.
ALU + CU + REGs
CPU
MEMORYIO
SERIAL
PORTS
TIMERS
PARALLEL
PORTS
INTERUPT
CONTROL
ALU + CU + REGs
CPU
MEMORYIO
SERIAL
PORTS
TIMERS
PARALLEL
PORTS
INTERUPT
CONTROL
On a Single Board On a Single Chip
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8051 FAMILY
M C Features
8031 Intel's: 0KROM, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts.
8051 Intel's: 4KROM, 128-Bytes RAM, 32-I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts.
8052 Intel's: 8KROM, 256-Bytes RAM, 32-
I/O pins, 32-Regs, 3-Timers, 1-Serial
port, 8Interrupts.
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8051 FAMILY
AT89C51 Atmel's: 4KROM, 128-Bytes RAM, 32-
I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts, Vcc =5V.
AT89LV51 Atmel's: 4KROM, 128-Bytes RAM,
32- I/O pins,32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts, Vcc =3V.AT89LV52 Atmel's: 4KROM, 128-Bytes RAM, 32-
I/O pins, 32-Regs, 2-Timers, 1-Serial
port, 6-Interrupts, Vcc =3V.
DS5000-8 Dallas's: 8KROM, 128-Bytes RAM, 32-
I/O pins, 32-Regs, 2-Timers, 1- Serial
port, 6-Interrupts, Vcc =5V.
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8051 FEATURES 40- pin DI package
Harvard Architecture 8-bit Arithmetic Logic Unit
8-bit data bus multiplexed with address bus
On-chip oscillator
1 16MHz operating frequency
(2 ALEs per m/c)
Each m/c contains 6 states; 12 clock cycles;
fclk = fxtal/12.
16-bit address bus - 216 = 65,536 = 64K bytesof Locations.
4K ROM, 128 bytes RAM, 32 REGs, 16 bytesBit addressable RAM, 80 bytes user RAM.
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8051 FEATURES 4 bank of 8 registers (R0-R7); 8-bit each
2 pointers PC & DPTR
2 - 16 bit timers/counters with interrupts
4 8 bit parallel ports; with single line access
1 serial port with interrupt facility
2 external Interrupts( total - 5 Interrupts) A & B math registers
Stack- internal RAM, 8 bit SP=07H default; Store, Load
Bit addressable instructions
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C
P
U
BL
O
C
KD
I
A
GR
A
M
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C
P
U
A
R
CH
I
T
E
C
TU
RE
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Reset Operation The reset input is the RST pin, which has a Schmitt Trigger input.
A reset is accomplished by holding the RST pin high for at least 2
machine cycles (24 oscillator periods) while the Osci l lator isrunn ing.
The CPU responds by generating an internal reset with the timing
shown below.
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2 Circuits for System Reset
8.2K W 8.2K W
100 W Reset
RST RST
+5V +5V +5V
10m 10m
Manual reset Power-on reset
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General
Purpose
Memory
Bit Addressable
Memory
Register
Bank - 3
Register
Bank - 2
Register
Bank - 1
R7
R6
R5R4R3R2R1
R0
7F
30
2F
20
1F
18
1710
0F
08
07
06
05
04
03
02
01
00
8 E 0*
REG - A
8 F 0*
REG - B
8 B 8*
I P
8 A 8*
I E
8 8 9
TMOD
8 8 C
TH - 0
8 8 8*
TCON
8 8 A
TL - 0
8 8 B
TL - 1
8 8 D
TH - 1
8 9 8*
SCON
8 9 9
SBUF
8 8 7
PCON
8 D0*
PSW
8 81
S P
8 83
D P H
8 82
D P L
16P C
8 8 0*
PORT- 0
8 9 0*
PORT- 1
8 A 0*
PORT- 2
8 B 0*
PORT- 3
I
N
T
ER
N
A
L
ROM
FFF
000
8051 PROGRAMMING MODEL:
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REGISTER ORGANIZATION:
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I/O PORT ORGANIZATION:
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I/O PORT ORGANIZATION:
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Memory Types:
2- types ofexternalmemory
Program Memory
instructions (ROM-
PC) Data Memory -
variable data values
(RAM-DPTR)
3-typesofinternalmemoryon micro-controllers
Program Memory
instructions (4K-ROM)
Data Memory - variable datavalues (128 Bytes-RAM)
Special Function Registers
(SFRs - Control device
operation) & General PurposeRegisters (GPRs - RAM
storage)
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Memory Organization:
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Memory Organization
Separate memory space for program (64KB)and data (64KB).
Internal memory:
On-chip ROM (4K/8K for 51/52) On-chip RAM (128/256 for 31,51/32,52):
General purpose storage(30-7F/FF)
Bit-addressable storage(20-2Fh)
4 Register banks (00-1F)
Special function registers (80-FFh)
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MCS-51 Memory Structure
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Internal Data RAM
MOV A,5FH
MOV A,FFH
MOV Ri,#9FH (i=0 or 1)
MOV A, @Ri
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Lower128 Bytes ofInternal RAM
00H-1FH: 32 8 Bit-addressable,
bit address 00H-7FH.
30H-7FH: General purpose RAM.
20H-2FH: 128 Bit-addressable,
bit address 00H-7FH.
30H-7FH: General purpose RAM.
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Upper 128 Bytes of Internal RAM
Available only in 8052. Can be accessed by indirect
addressing only (via @R0 or @R1). Can be used as stack
area by setting SP to FFH.
FFH
80H
Non-continuous SFR addressspace
Available as stackspace in devices
with 256 bytes RAM (Notimplemented in 8051)
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Alternate Pin Functions for Port
Pins
Timer/counter 2 capture/load91HT2EXP1.1
Timer/counter 2 external input90HT2P1.0
External data memory read strobeB7HRD P3.7
External data memory write strobeB6HWR P3.6
Timer/counter 1 external inputB5HT1P3.5
Timer/counter 0 external inputB4HT0P3.4
External interrupt 1B3HINT1 P3.3
External interrupt 0B2HINT0 P3.2
Transmit data for serial portB1HTxDP3.1
Receive data for serial portB0HRxDP3.0
ALTERNATE FUNCTIONBIT ADDRESSNAMEBIT
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RegisterBit Address
P0808182838485868780
SPNot bit addressable81
DPLNot bit addressable82
DPHNot bit addressable83
PCON87
TCON88898A8B8C8D8E8F88
TMODNot bit addressable89
TL0Not bit addressable8A
TL1Not bit addressable8B
TH0Not bit addressable8C
TH1Not bit addressable8D
P1909192939495969790
SCON98999A9B9C9D9E9F98
SBUFNot bit addressable99
Byte
Address
Register
Bit Address
Byte addr
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TH2Not bit addressableCD
TL2Not bit addressableCC
RCAP2HNot bit addressableCB
RCAP2LNot bit addressableCA
T2CONC8C9CACBCCCDCECFC8
A8A9AAABAC--
B0B1B2B3B4B5B6
D0-D2D3D4D5D6
E0E1E2E3E4E5E6
F0F1F2F3F4F5F6
RegisterBit Address
P2A0A1A2A3A4A5A6A7A0
IEAFA8
P3B7B0
IPB8B9BABBBC---B8
PSWD7D0
A or ACCE7E0
BF7F0
Byte addr
SFR M M
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SFR Memory Map
Memory Organization:
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Memory Organization:
8051
Micro-controller
Various SFRs:
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Various SFRs:
BLUE background are I/O port SFRs
YELLOW background are Control SFRs
GREEN background are other SFRs
SFR Addresses:
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SFR Addresses:
Program Status Word
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Program Status Word
TIMERS/COUNTERS:
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TIMERS/COUNTERS: 2 - 16 bit UP_COUNTERS , each is 2-8bit counters
TCON &TMOD for controlling & Mode setting
4 different modes of operation
ISR at 0013h; indicate
control
ISR at 0003h; indicate
control
O (89 )
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TMOD (89H):
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
GATE Gate bit. When set, timerx only runs while INTx is highC/T Counter/timer select bit.
1 = event counter driven by external clock source0 = interval timer driven by internal clock source
M1 M0 Mode Description0 0 0 8048 13-bit timer mode0 1 1 16-bit timer mode
1 0 2 8-bit auto-reload mode (for baud rate generation)1 1 3 Split timer mode:Timer0: TL0 is an 8-bit timer controlled by timer0
control bits; TH0 the same except controlledby timer 1 control bits
Timer1: stopped
( )
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TCON (88H):
TIMER CONTROL LOGIC:
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TIMER CONTROL LOGIC:
CK
PULSES
Mode 0:13 bit Timer
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Mode 0:13-bit Timer
0 = Up1 = Down
INTx(P3.2)(P3.3)
12 MHz On-chipOSC
12
C/T
TRx
Gate
TLx THx TFx
(5 bits) (8 bits)
0 = Up1 = Down
Tx(P3.4)
(P3.5)
interrupt
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Mode 1: 16-bit Timer
On-chipOSC
12
C/T
TRx
Gate
TLx THx TFx
(16 bits)
0 = Up1 = Down
0 = Up1 = Down
12 MHz
Tx(P3.4)(P3.5)
INTx(P3.2)
(P3.3)
interrupt
d bi l d
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Mode 2: 8-bit Auto-Reload
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Mode 3: Split-Timer Mode
PCON SFR:
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PCON SFR:
8051 I t t
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8051 Interrupts:
8051 Interrupt Vector Table:
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8051 Interrupt Vector Table:
IP SFR:
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IP SFR:
IE SFR:
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IE SFR:
ISR at 002Bh;
ISR at 0023h;
ISR at 001Bh;
ISR at 0013h;ISR at 000Bh;
ISR at 0003h;
T2CON SFR:
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T2CON SFR:
SCON SFR:
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SCON SFR:
8051 UPON RESET:
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8051 UPON RESET:
REGISTER CONTENTS(HEX)
PC 0000
DPTR 0000
A 00
B 00
SP 07
PSW 00
P0-3 FF
IP XXX00000b
IE 0XX00000b
REGISTER CONTENTS(HEX)
TCON 00
TMOD 00
TH0 00
TL0 00
TH1 00
TL1 00
SCON 00
SBUF XX
PCON 0XXXXXXXb
Memory Interfacing:
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Memory Interfacing:
S i l P t O ti f 8051
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Serial Port Operations of 8051
Introduction
The EIA-232E or RS232 Standard
The MCS-51/52 Serial Port Interface
Application of Mode 0
Application of Mode 1
Application of Mode 2 & 3
Serial Data Communication
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Serial Data Communication
Long-distance data communication
lower transfer rate situations
Synchronous serial data communication
use a separate clock signal to synchronize the receive
and transmit.
Usually larger frame (block) and faster. Asynchronous serial data communication
does not need a separate clock signal to synchronize
the data transfer.
Character-based. Each character is framed by a startbit and stop bit.
Receiver needs to identify the start bit and stop bit to
correctly receive the data character.
Th MCS 51/52 S i l I t f
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The MCS-51/52 Serial Interface
SBUF(write-only)
Shift register
SBUF(read-only)
CLK
CLK
D
Q
8051 bus
Baud rateclock(receive)
Baud rateclock(transmit)
TxD(P3.1)
RxD(P3.0)
F f 8051 i l
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Features of 8051 serial port
Full duplex
Receive buffering (1 byte buffer)
Four operation modes (0 - 3)
Easy programming ( select baud rate (either fixed (on-chip OSC/12 or
OSC/64), or variable (T1 or T2))
select mode
run (SCON))
Easy to use
Transmit data: MOV SBUF, A
Receive data: MOV A, SBUF
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Basic Data Communication Link
Either dedicated or public phone line can be used as a
medium for asynchronous serial data communication.
Modem is used to convert digital data into analog
waveform suitable to transmission on the phone line and
vice versa.
Two types of links: Point-to-Point and Multipoint.
DTE DCE DCE DTE
Computer orterminal
Modem Modem Computer orterminal
Communication link
Point to Point & Multipoint Communication
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Point-to-Point & Multipoint Communication
Link
Station
Master
Slave 1
Station
Slave 2 Slave n
Peer Peer
Address 1 Address 2 Address n
Tx
TxRx
Rx
i f C i i i k
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Basics of Communication Links
Two-wire and Four-wire system: 2 wires: signal and ground.
4 wires: two 2 wires.
Communication link types:
Simplex link: the line is dedicated to either
transmission or reception, but not both.
Half-duplex link: the communication link can be
used for either transmission or reception, but in
only one direction at a time.
Full-duplex link: The transmission and reception
can proceed simultaneously. This link requires four
wires.
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Basics of Communication Links
5V
0V
>+3V
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EIA-232-E or RS-232
EIA-232-E or RS-232 can apply to the
following data communication schemes: Serial communications
Synchronous and asynchronous
Dedicated leased or private lines
Switched service
Two wire or four wire
Point to point or multipoint
4 aspects in EIA-232-E interface:mechanical, functional, procedural, andelectrical.
EIA 232 E Connector and Pin Assignment
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EIA-232-E Connector and Pin Assignment
Signal direction
to DCE
to DTE
to DTE
to DTE
to DCE
to DCE
to DTE
to DTEBoth
to DCE
Signal Name
Secondary TxD
Tx clock
Secondary RxD
Rx clockunassigned
Secondary Request To Send
Data Terminal Ready
Signal Quality Detect
Ring indicatorData Rate Select
Tx clock
unassigned
Signal direction
Both
to DCE
to DTE
to DCEto DTE
to DTE
Both
to DTE
to DTE
to DTE
Signal Name
protective ground
TxD
RxD
Request To SendClear To Send
Data Set Ready
Signal ground
Carrier Detect
ReservedReserved
Unassigned
Secondary Carrier Detect
Secondary Clear To Send
14 1
15 2
16 3
17 418 5
19 6
20 7
21 8
22 923 10
24 11
25 12
13
Functions of EIA 232 E Interchange Circuits
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Functions of EIA-232-E Interchange Circuits1 - Shield2 BA Transmitted data3 BB Received data
4 CA/CJ Request to send/ready for receiving5 CB Clear to send6 CC DCE7 AB Signal common8 CF Received line signal detector9,10,11 - (Reserved for testing, unassigned)12 SCF/CI Secondary received line signal detection/data range selector (DCE source)
13 SCB Secondary clear to send14 SBA Secondary transmitted data15 DB Transmitter signal element timing (DCE source)16 SBB Secondary received data17 DD Received signal element timing18 LL Local loopback
19 SCA Secondary request to send20 CD DTE ready21 RL/CG Remote loopback/signal quality detector22 CE Ring indicator23 CH/CI Data signal rate selector (DTE/DCE source)24 DA Transmitter signal element timing (DTE source)25 TM Test mode
EIA-232-E Procedural Characteristics
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Signal GND (7) Signal GND (7)DTE ready (20) -> carrier on carrier detect (8) ->
data send data receive (3) ->
send timing (24) -> receive timing (17) ->EOT send (2) -> EOT send EOT receive (3) ->send timing (24) -> receive timing (17) ->RTS off (4) -> error check
carrier off carrier off (8) ->-< CTS off (5)
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Data Transmission Errors
Framing error: when a receivedcharacter is improperly framed by the
start and stop bits; it is set by the absenceof stop bit.
Receive overrun: one or more charactersin the data stream were lost.
Parity error: received character parityerror.
N ll M d C i
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Null Modem Connection
Pin Circuit name DTE X DTE Y
22 Ring indicator CE CE20 Data terminal ready CD CD
8 Data carrier detect CF CF6 Data set ready CC CC5 Clear to send CB CB4 Request to send CA CA
3 Receive data BB BB2 Transmit data BA BA24 Transmitter timing DA DA17 Receiver timing DD DD7 Signal ground AB AB
When 2 DTEs are very close, no need to use modems to connect them.
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Alternate Pin Functions for Port Pins
Timer/counter 2 capture/load91HT2EXP1.1
Timer/counter 2 external input90HT2P1.0
External data memory read stbB7HRD P3.7
External data memory write stbB6HWR P3.6
Timer/counter 1 external inputB5HT1P3.5Timer/counter 0 external inputB4HT0P3.4
External interrupt 1B3HINT1 P3.3
External interrupt 0B2HINT0 P3.2
Transmit data for serial portB1HTxDP3.1
Receive data for serial portB0HRxDP3.0
ALTERNATE FUNCTIONBIT ADDRESSNAMEBIT
RegisterBit AddressByte
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P0808182838485868780
SPNot bit addressable81
DPLNot bit addressable82
DPHNot bit addressable83
PCON87
TCON88898A8B8C8D8E8F88
TMODNot bit addressable89
TL0Not bit addressable8A
TL1Not bit addressable8B
TH0Not bit addressable8C
TH1Not bit addressable8D
P1909192939495969790
SCON98999A9B9C9D9E9F98
SBUFNot bit addressable99
Address
RegisterBit AddressByte addr
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TH2Not bit addressableCD
TL2Not bit addressableCC
RCAP2HNot bit addressableCB
RCAP2LNot bit addressableCA
T2CONC8C9CACBCCCDCECFC8
A8A9AAABAC--
B0B1B2B3B4B5B6
D0-D2D3D4D5D6
E0E1E2E3E4E5E6
F0F1F2F3F4F5F6
P2A0A1A2A3A4A5A6A7A0
IEAFA8
P3B7B0
IPB8B9BABBBC---B8
PSWD7D0
A or ACCE7E0
BF7F0
S i l P M d f O i
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Serial Port Modes of Operation
Four modes of operation selected by SM0and SM1 bits in SCON (98H):
mode 0: fixed baud rate (OSC/12) shift
register for I/O expansion
mode 1: variable baud rate (set by timer) 8-
bit UART
mode 2: fixed baud rate (OSC/32 or OSC/64)
9-bit UART
mode 3: variable baud rate (set by timer) 9-
bit UART
SCON (98H)
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SCON (98H)
8 bit Shift R i t (Mode 0)
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8-bit Shift Register(Mode 0)
Shift registerRxD (P3.0)
8051
Clock
Data
TxD (P3.1)
8 extra outputs
parallel-in-serial-out shift register: 74165serial-in-parallel-out shift register: 74675bidirectional: HCF4034B
8-bit Shift Register (Mode 0)
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g ( )
8-bit Shift Register (Mode 0)
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8-bit Shift Register (Mode 0)
Shift clock (TxD, P3.1)): S3P1 H->L, S6P1 L->H (used as rising edge strobe).Data out (RxD, P3.0): S1P1 assert valid data and hold.Data in (RxD, P3.0): received data valid from S1P1 to S4P1 (ALE)
8-bit UART (Mode 1)
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8 bit UART w Variable Baud Rate (Mode 1)
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8-bit UART w Variable Baud Rate (Mode 1)
10 bits are transmitted on TxD or received on RxD: one startbit (always 0),
8 data bits (LSB first), and a stop bit (always 1). The stop bit goes to RB8 in SCONwhen receive. In 51, T1 is used as baud rate generator. In 52, either T1 or T2 orcombination of the two (one for Tx, the other for Rx) can be used.
Transmission is initiated by any instruction that uses SBUF as a
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Transmission is initiated by any instruction that uses SBUF as a
destination register. The write to SBUF signal also loads a 1
into the 9th bit position of the transmit shift register and flags
the TX Control unit that a transmission is requested.
Transmission actually commences at S1P1 of the machinecycle following the next rollover in the divide-by-16 counter.
(Thus, the bit times are synchronized to the divide-by-16
counter, not to the write to SBUF signal.)
The transmission begins with activation of SEND which putsthe start bit at TxD. One bit time later, DATA is activated, which
enables the output bit of the transmit shift register to TxD. The
first shift pulse occurs one bit time after that. As data bits shift
out to the right, zeros are clocked in from the left. When the
MSB of the data byte is at the output position of the shiftregister, then the 1 that was initially loaded into the 9th position
is just to the left of the MSB, and all positions to the left of that
contain zeros. This condition flags the TX Control unit to do one
last shift and then deactivate SEND and set TI. This occurs at
the 10th divide-by-16 rollover afterwrite to SBUF.
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Reception is initiated by a detected 1-to-0 transition at RxD. For
this purpose RxD is sampled at a rate of16 times whatever baud
rate has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFH is written
into the input shift register. Resetting the divide-by-16 counter
aligns its rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the7th, 8th, and 9th counter states of each bit time, the bit detector
samples the value of RxD. The value accepted is the value that
was seen in at least 2 of the 3 samples. This is done for noise
rejection. If the value accepted during the first bit time is not 0,
the receive circuits are reset and the unit goes back to looking foranother 1-to-0 transition. This is to provide rejection of false start
bits. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
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As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the shift
register (which in mode 1 is a 9-bit register), it flags the RX
Control block to do one last shift, load SBUF and RB8, and set
RI. The signal to load SBUF and RB8, and to set RI, will be
generated if, and only if, the following conditions are met at the
time the final shift pulse is generated:
1. RI = 0, and2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame
is irretrievably lost. If both conditions are met, the stop bit goes
into RB8, the 8 data bits go into SBUF, and RI is activated. Atthis time, whether the above conditions are met or not, the unit
goes back to looking for a 1-to-0 transition in RxD.
9-bit UART Fixed Baud Rate (Mode 2)
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9-bit UART Fixed Baud Rate (Mode 2)
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( )11 bits are transmitted or received. One start bit (0), 8 data bits, a programmable9th data bit, and a stop bit (1). On Tx, the 9th bit is whatever in TB8 in SCON. OnRx, the 9th bit received is placed in RB8 in SCON. The baud rate is eitherOSC/32
orOSC/64 (determined by SMOD bit in PCON).
9-bit UART variable Baud Rate (Mode 3)
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( )
9-bit UART Variable Baud Rate (Mode 3)
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9 bit UART Variable Baud Rate (Mode 3)
Same as Mode 2 except that the baud rate is programmable and provided by thetimer (T1, T2 or combination of T1 & T2)
R i E bl
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Receiver Enable
The receiver enable bit (REN) in SCONmust be set by software to enable thereception of characters:
SETB REN
MOV SCON, #xxx1xxxxB
Usually done at the beginning of a
program when the serial port, timers, etc.are initialized.
Th 9th d t bit
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The 9th data bit
The 9th data bit transmitted in mode 2and 3 must be loaded into TB8 bysoftware.
The 9th data bit received is placed inRB8 in SCON.
The 9th bit plays an important role in
multiprocessor communications.
Adding a Parity bit
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dd g a a ty b t
A common use for the 9th data bit is to add parity to acharacter in mode 2 or mode 3.
The P bit in PSW is set or reset every machine cycle toestablish even parity with the 8 bits in the accumulator.
For even parity communication:
MOV C, P
MOV TB8, C
MOV SBUF, A
If odd parity communication:
MOV C, P
CPL C
MOV TB8, C
MOV SBUF, A
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Interrupt Flags
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Interrupt Flags
The receive and transmit interrupt flags (RI & TI)
plays an important role in 8051 serial communications.Both bits are set by hardware, but must be cleared bysoftware.
RI is set at the end of reception indicates receive
buffer full. This can be tested in software or can beprogrammed to cause an interrupt.
If software wishes to receive a character from thedevice connected to serial port, it must wait until RI isset and read the character from SBUF:
Wait: JNB RI,Wait
CLR RI
MOV A, SBUF
Interrupt Flags
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Interrupt Flags
TI is set at the end of character transmission and
indicates transmit buffer empty. This can be tested insoftware or can be programmed to cause an interrupt.
If software wishes to transmit a character to the deviceconnected to serial port, it must check that the serialport is ready:
Wait: JNB TI,Wait
CLR TI
MOV SBUF, A
Multiprocessor Communications
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Master 8051 8051 Slave #1 8051 slave #2
32 I/O lines
RXD RXD
P2P0 P0P1 P1P2 P3 P3
32 I/O lines
TXD
When the master wants to transmit a block of data to one of several slaves, itfirst send out an address byte identifies the target slave. An address byte
differs from a data byte in that the 9th bit is 1 in an address and 0 in a data byte.An address byte will interrupt all slaves. The addressed slave then clear its SM2bit and prepare to receive data bytes that follow. Slaves not addressed leave theirSM2 bit set and go about their business, ignoring incoming data block.Once linkestablished, bi-directional communication can be achieved by not using the 9th bit.
Mode 2 & 3, if SM2 = 1, then RI=1 only when RB8 = 1.
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Multiprocessor Communications SM2 has no effect in mode 0
In mode 1, SM2 can be used to check the validityof the stop bit.
In mode 1 reception, if SM2 = 1, the receiveinterrupt will not be activated unless a valid stopbit is received.
In mode 2 and 3, if SM2 = 1, the receive interrupt
will not be activated unless the 9th
received bitRB8 = 1 is received.
Serial Port Baud Rates
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Serial Port Baud Rates
12
64
32
16
32
On-chipOSC
On-chip
OSC
Timer 1, 2
overflow
SMOD = 0
SMOD = 0
SMOD = 1
SMOD = 1
Baud rateclock
Baud rate
clock
Baud rate
clock
Mode 0
Mode 2
Mode 1 & 3
MOV A, PCONSETB ACC.7MOV PCON, A
Using Timer 1 as the Baud Rate Clock
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Using Timer 1 as the Baud Rate Clock
T1 in mode 2, 8-bit auto-reload mode:
MOV TMOD, #0010xxxxB
Very low baud rates can be achieved by using
T1 mode 1, 16-bit mode with interrupt enabled.
TH1, TL1 reloaded in ISR.
Use external clock source T1 (P3.5) to clock
timer 1.
The baud rate = timer 1 overflow rate /32(SMOD = 0) or /16 (SMOD = 1).
U i Ti 1 h B d R Cl k
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Using Timer 1 as the Baud Rate Clock
Baud rate Crystal SMOD TH1 Actual Baud ERROR
9600 12.000M 1 -7(F9H) 8923 7%
2400 12.000M 0 -13(F3H) 2404 0.16%
1200 12.000M 0 -26(E6H) 1202 0.16%
19200 11.059M 1 -3(FDH) 19200 0
9600 11.059M 0 -3(FDH) 9600 0
2400 11.059M 0 -12(F4H) 2400 0
1200 11.059M 0 -24(E8H) 1200 0
2400 Baud UART using Timer 1
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g
Initialization (12MHz OSC)SM0 SM1 SM2 REN TB8 RB8 TI RI
SCON: 0 1 0 1 0 0 1 0
GTE C/T M1 M0 GTE C/T M1 M0
TMOD: 0 0 1 0 0 0 0 0TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TCON: 0 1 0 0 0 0 0 0
TH1: 1 1 1 1 0 0 1 1
INIT: MOV SCON, #52H ;serial port, mode 1
MOV TMOD, #20H ;timer1, mode 2
MOV TH1, #-13 ;reload count for 2400 baud
SETB TR1 ;start timer 1
O tp t 7 bit ASCII Character
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Output 7-bit ASCII Character
with Odd Parity SubroutineOUTCHR: MOV C, P ;parity bit in C
CPL C ;change to odd parity
MOV ACC.7, C ;add to character
AGAIN: JNB TI, AGAIN ;TX empty?
CLR TI ;
MOV SBUF,A ;send character
CLR ACC.7 ;strip off parity bit
RET ;A unchanged
Input 7-bit ASCII Character Expecting
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p p g
Odd Parity Subroutine
INCHR: JNB RI,$ ;wait for character
CLR RI ;
MOV A, SBUF ;
MOV C,P ;for odd parity in A, P should
; be set
CPL C ;complementing correctly
;indicates if an error occurred
CLR ACC.7 ;strip off parity bit
RET ;C=1 indicate parity error
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TMOD (89H)
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TMOD (89H)
TCON (88H)
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TCON (88H)
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Interrupt Registers
5-source (3 internal: serial port (RI,TI),
T0, T1, and 2 external: INT0, INT1), 2-
priority levels. Interrupts are disabled after a system
reset and then enabled by writing to the
interrupt enable register (IE: A8H). The priority level is set through the
interrupt priority register (IP: B8H).