sn74aup1g02 low-power single 2-input positive-nor gate … · 2015-04-19 · product folder sample...
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SN74AUP1G02SCES568H –JUNE 2004–REVISED OCTOBER 2014
SN74AUP1G02 Low-Power Single 2-Input Positive-NOR Gate1 Features 2 Applications1• Available in the Ultra Small 0.64 mm2 Package • ATCA Solutions
(DPW) with 0.5-mm Pitch • Active Noise Cancellation (ANC)• Low Static-Power Consumption • Barcode Scanner
(ICC = 0.9 μA Max) • Blood Pressure Monitor• Low Dynamic-Power Consumption • CPAP Machine
(Cpd = 4.3 pF Typ at 3.3 V) • Cable Solutions• Low Input Capacitance (Ci = 1.5 pF Typ) • DLP 3D Machine Vision, Hyperspectral Imaging,• Low Noise – Overshoot and Undershoot Optical Networking, and Spectroscopy
<10% of VCC • E-Book• Ioff Supports Live Insertion, Partial-Power-Down • Embedded PCMode, and Back-Drive Protection
• Field Transmitter: Temperature or Pressure• Input Hysteresis Allows Slow Input Transition and SensorBetter Switching-Noise Immunity at the Input• Fingerprint Biometrics(Vhys = 250 mV Typ at 3.3 V)• HVAC: Heating, Ventilating, and Air Conditioning• Wide Operating VCC Range of 0.8 V to 3.6 V• Network-Attached Storage (NAS)• Optimized for 3.3-V Operation• Server Motherboard and PSU• 3.6-V I/O Tolerant to Support Mixed-Mode Signal• Software Defined Radio (SDR)Operation• TV: High-Definition (HDTV), LCD, and Digital• tpd = 4.6 ns Max at 3.3 V• Video Communications System• Suitable for Point-to-Point Applications• Wireless Data Access Card, Headset, Keyboard,• Latch-Up Performance Exceeds 100 mA Per
Mouse, and LAN CardJESD 78, Class II• X-ray: Baggage Scanner, Medical, and Dental• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model3 Description(A114-B, Class II)This single 2-input positive-NOR gate performs the– 1000-V Charged-Device Model (C101) Boolean function Y = A + B or Y = A × B in positivelogic.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)SOT-23 (5) 2.90 mm × 1.60 mmSOT (5) 2.00 mm × 1.25 mm
SN74AUP1G02 SOT (5) 1.60 mm × 1.20 mmUSON (6) 1.45 mm × 1.00 mmX2SON (4) 0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of ContentsPulse Duration ........................................................... 91 Features .................................................................. 1
8.2 Enable and Disable Times ...................................... 102 Applications ........................................................... 19 Detailed Description ............................................ 113 Description ............................................................. 1
9.1 Overview ................................................................. 114 Simplified Schematic............................................. 19.2 Functional Block Diagram ....................................... 115 Revision History..................................................... 29.3 Feature Description................................................. 116 Pin Configuration and Functions ......................... 39.4 Device Functional Modes........................................ 117 Specifications......................................................... 4 10 Application and Implementation........................ 127.1 Absolute Maximum Ratings ..................................... 410.1 Application Information.......................................... 127.2 Handling Ratings ...................................................... 410.2 Typical Application ............................................... 127.3 Recommended Operating Conditions ...................... 5
11 Power Supply Recommendations ..................... 147.4 Thermal Information .................................................. 512 Layout................................................................... 147.5 Electrical Characteristics........................................... 6
12.1 Layout Guidelines ................................................. 147.6 Switching Characteristics, CL = 5 pF ........................ 612.2 Layout Example .................................................... 147.7 Switching Characteristics, CL = 10 pF ...................... 7
13 Device and Documentation Support ................. 157.8 Switching Characteristics, CL = 15 pF ...................... 713.1 Trademarks ........................................................... 157.9 Switching Characteristics, CL = 30 pF ...................... 713.2 Electrostatic Discharge Caution............................ 157.10 Operating Characteristics........................................ 713.3 Glossary ................................................................ 157.11 Typical Characteristics ............................................ 8
14 Mechanical, Packaging, and Orderable8 Parameter Measurement Information .................. 9Information ........................................................... 158.1 Propagation Delays, Setup and Hold Times, and
5 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March 2010) to Revision H Page
• Updated document to new TI data sheet format ................................................................................................................... 1• Deleted Ordering Information table. ....................................................................................................................................... 1• Updated Ioff in Features. ........................................................................................................................................................ 1• Added Applications. ................................................................................................................................................................ 1• Added DPW Package. ........................................................................................................................................................... 3• Added Handling Ratings table. ............................................................................................................................................... 4• Added Thermal Information table. .......................................................................................................................................... 5• Added Typical Characteristics. ............................................................................................................................................... 8
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DBV PACKAGE
(TOP VIEW)
51
2
V
Y43
CCA
B
GND
DCK PACKAGE
(TOP VIEW)
51
2
V
Y
CC
43
A
B
GND
DRL PACKAGE
(TOP VIEW)
51
2
4
V
Y
CC
3
A
B
(TOP VIEW)
B N.C.
A 6
5
4
2
3GND Y
VCC1
GND Y3 4
2B 5
A 61
N.C.
VCC
DSF PACKAGE
(TOP VIEW)
YFP PACKAGE
( VIEW)TOP
GND
A
Y
VCC
B
3
6
2
1
4
5 DNU
A1
B1
C1
A2
B2
C2
GND
DRY PACKAGE
1 5
2
3
AGND
Y
VCC
DPW PACKAGE
(TOP VIEW)
B
4
DNU – Do not useN.C. – No internal connectionSee mechanical drawings for dimensions.
SN74AUP1G02www.ti.com SCES568H –JUNE 2004–REVISED OCTOBER 2014
6 Pin Configuration and Functions
Pin FunctionsPIN
I/O DESCRIPTIONDBV, DCK, DRY,NAME DPW YFPDRL DSFA 1 2 1 A1 I Input AB 2 1 2 B2 I Input B
GND 3 3 3 B3 — GroundY 4 4 4 C4 O Output Y
VCC 5 5 6 A6 — Power Pin
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 VVI Input voltage range (2) –0.5 4.6 VVO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 VVO Output voltage range in the high or low state (2) –0.5 VCC + 0.5 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling RatingsMIN MAX UNIT
Tstg Storage temperature range –65 150 °CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000pins (1)
V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification 0 1000JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVCC Supply voltage 0.8 3.6 V
VCC = 0.8 V VCC
VCC = 1.1 V to 1.95 V 0.65 × VCCVIH High-level input voltage VVCC = 2.3 V to 2.7 V 1.6VCC = 3 V to 3.6 V 2VCC = 0.8 V 0VCC = 1.1 V to 1.95 V 0.35 × VCCVIL Low-level input voltage VVCC = 2.3 V to 2.7 V 0.7VCC = 3 V to 3.6 V 0.9
VI Input voltage 0 3.6 VVO Output voltage 0 VCC V
VCC = 0.8 V –20 μAVCC = 1.1 V –1.1VCC = 1.4 V –1.7
IOH High-level output currentVCC = 1.65 V –1.9 mAVCC = 2.3 V –3.1VCC = 3 V –4VCC = 0.8 V 20 μAVCC = 1.1 V 1.1VCC = 1.4 V 1.7
IOL Low-level output currentVCC = 1.65 V 1.9 mAVCC = 2.3 V 3.1VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/VTA Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal InformationDBV DCK DPW DRL DRY DSF
THERMAL METRIC (1) UNIT5 PINS 5 PINS 5 PINS 5 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal 298.6 314.4 291.8 349.7 554.9 407.1resistanceRθJC(top) Junction-to-case (top) thermal 240.2 128.7 224.2 120.5 385.4 232.0resistanceRθJB Junction-to-board thermal 134.6 100.6 245.8 171.4 388.2 306.9resistance
°C/WψJT Junction-to-top characterization 114.5 7.1 31.4 10.8 159.0 40.3parameterψJB Junction-to-board characterization 133.9 99.8 245.6 169.4 384.1 306.0parameterRθJC(bot) Junction-to-case (bottom) thermal n/a n/a 195.4 n/a n/a n/aresistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C TA = –40°C to 85°CPARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAXIOH = –20 μA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1
0.75 ×IOH = –1.1 mA 1.1 V 0.7 × VCCVCC
IOH = –1.7 mA 1.4 V 1.11 1.03IOH = –1.9 mA 1.65 V 1.32 1.3VOH VIOH = –2.3 mA 2.05 1.97
2.3 VIOH = –3.1 mA 1.9 1.85IOH = –2.7 mA 2.72 2.67
3 VIOH = –4 mA 2.6 2.55IOL = 20 μA 0.8 V to 3.6 V 0.1 0.1IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31 0.37IOL = 1.9 mA 1.65 V 0.31 0.35
VOL VIOL = 2.3 mA 0.31 0.33
2.3 VIOL = 3.1 mA 0.44 0.45IOL = 2.7 mA 0.31 0.33
3 VIOL = 4 mA 0.44 0.45
A or BII VI = GND to 3.6 V 0 V to 3.6 V 0.1 0.5 μAinputsIoff VI or VO = 0 V to 3.6 V 0 V 0.2 0.6 μAΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 μA
VI = GND or (VCC to 3.6 V),ICC 0.8 V to 3.6 V 0.5 0.9 μAIO = 0VI = VCC – 0.6 V (1),ΔICC 3.3 V 40 50 μAIO = 0
0 V 1.5Ci VI = VCC or GND pF
3.6 V 1.5Co VO = GND 0 V 3 pF
(1) One input at VCC – 0.6 V, other input at VCC or GND.
7.6 Switching Characteristics, CL = 5 pFover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
TA = 25°C TA = –40°C to 85°CFROM TOPARAMETER VCC UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX0.8 V 19.3
1.2 V ± 0.1 V 2.6 7.3 13 2.1 16.31.5 V ± 0.1 V 1.4 5.2 8.9 0.9 10.8
tpd A or B Y ns1.8 V ± 0.15 V 1 4.2 6.8 0.5 8.72.5 V ± 0.2 V 1 3 4.6 0.5 5.93.3 V ± 0.3 V 1 2.4 3.7 0.5 4.6
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7.7 Switching Characteristics, CL = 10 pFover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
TA = 25°C TA = –40°C to 85°CFROM TOPARAMETER VCC UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX0.8 V 22.3
1.2 V ± 0.1 V 1.5 8.5 14.9 1 17.91.5 V ± 0.1 V 1 6.2 10.2 0.5 11.8
tpd A or B Y ns1.8 V ± 0.15 V 1 5 7.9 0.5 9.52.5 V ± 0.2 V 1 3.6 5.4 0.5 6.53.3 V ± 0.3 V 1 2.9 4.4 0.5 5
7.8 Switching Characteristics, CL = 15 pFover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
TA = 25°C TA = –40°C to 85°CFROM TOPARAMETER VCC UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX0.8 V 25
1.2 V ± 0.1 V 3.6 9.9 16.5 3.1 20.61.5 V ± 0.1 V 2.3 7.2 11.3 1.8 13.7
tpd A or B Y ns1.8 V ± 0.15 V 1.6 5.8 8.9 1.1 11.12.5 V ± 0.2 V 1 4.3 6.1 0.5 7.73.3 V ± 0.3 V 1 3.4 5 0.5 6.2
7.9 Switching Characteristics, CL = 30 pFover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
TA = 25°C TA = –40°C to 85°CFROM TOPARAMETER VCC UNIT(INPUT) (OUTPUT) MIN TYP MAX MIN MAX0.8 V 34.6
1.2 V ± 0.1 V 4.9 13.1 21.1 4.4 26.21.5 V ± 0.1 V 3.4 9.5 14.4 2.9 17.4
tpd A or B Y ns1.8 V ± 0.15 V 2.5 7.7 11.2 2 142.5 V ± 0.2 V 1.8 5.7 7.8 1.3 9.83.3 V ± 0.3 V 1.5 4.7 6.4 1 7.8
7.10 Operating CharacteristicsTA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT0.8 V 4.1
1.2 V ± 0.1 V 4.11.5 V ± 0.1 V 4.1
Cpd Power dissipation capacitance f = 10 MHz pF1.8 V ± 0.15 V 4.12.5 V ± 0.2 V 4.23.3 V ± 0.3 V 4.3
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VCC (V)
TPD
(ns)
0 0.5 1 1.5 2 2.5 3 3.50
5
10
15
20
25
30
35
40
D001
TPD in ns
Temperature (qC)
TPD
(ns)
-50 0 50 100 1500
1
2
3
4
5
6
7
8
9
D001
TPD in ns
SN74AUP1G02SCES568H –JUNE 2004–REVISED OCTOBER 2014 www.ti.com
7.11 Typical Characteristics
Figure 1. TDP vs VCC Figure 2. TPD vs Temperature at 1.8 V
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VM
From OutputUnder Test
CL(see Note A)
LOAD CIRCUIT
1 MΩ
VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 VInput
Output
Output
NOTES: A. CL includes probe and jig capacitance.B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.C. The outputs are measured one at a time, with one transition per measurement.D. tPLH and tPHL are the same as tpd.E. All parameters and waveforms are not applicable to all devices.
VM VM
VM VM
VM
5, 10, 15, 30 pFVCC/2VCC
VCC = 1.2 V± 0.1 V
VCC = 0.8 VVCC = 1.5 V
± 0.1 VVCC = 1.8 V
± 0.15 VVCC = 2.5 V
± 0.2 VVCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pFVCC/2VCC
5, 10, 15, 30 pFVCC/2VCC
5, 10, 15, 30 pFVCC/2VCC
CLVMVI
5, 10, 15, 30 pFVCC/2VCC
5, 10, 15, 30 pFVCC/2VCC
thtsu
Data Input
Timing InputVCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMSSETUP AND HOLD TIMES
VOLTAGE WAVEFORMSPULSE DURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP1G02www.ti.com SCES568H –JUNE 2004–REVISED OCTOBER 2014
8 Parameter Measurement Information
8.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
Figure 3. Load Circuit and Voltage Waveforms
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NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns .D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pFVCC/2VCC
0.15 V
VCC = 1.2 V± 0.1 V
VCC = 0.8 VVCC = 1.5 V
± 0.1 VVCC = 1.8 V
± 0.15 VVCC = 2.5 V
± 0.2 VVCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pFVCC/2VCC0.1 V
5, 10, 15, 30 pFVCC/2VCC0.1 V
5, 10, 15, 30 pFVCC/2VCC0.1 V
CLVMVIV∆
5, 10, 15, 30 pFVCC/2VCC
0.15 V
5, 10, 15, 30 pFVCC/2VCC0.3 V
OutputWaveform 1
S1 at 2 × VCC(see Note B)
OutputWaveform 2
S1 at GND(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH − V∆
≈0 V
VCC
VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
OutputControl
VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZLtPHZ/tPZH
2 × VCCGND
TEST S1From Output
Under Test
CL(see Note A)
LOAD CIRCUIT
S1
GND
5 kΩ
5 kΩ
2 × VCC
SN74AUP1G02SCES568H –JUNE 2004–REVISED OCTOBER 2014 www.ti.com
8.2 Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 OverviewThe SN74LVC1G02 device contains one 2-input positive-NOR gate and performs the Boolean function Y = A + Bor Y = A × B.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPWpackage. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm squarefootprint saves significant board space over other package options while still retaining the traditionalmanufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for liveinsertion.
9.2 Functional Block Diagram
9.3 Feature Description• Wide operating VCC range of 0.8 V to 3.6 V• 3.6-V I/O tolerant to support down translation• Input hysteresis allows slow input transition and better switching noise immunity at the input• Ioff feature allows voltages on the inputs and outputs when VCC is 0 V• Low noise due to slower edge rates
9.4 Device Functional Modes
Table 1. Function TableINPUTS OUTPUT
YA BL L HL H LH L LH H L
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3.3 V Bus Driver
1 V Micro Processor
VCC
0.1 Fµ
1 V regulated
Driver µC
SN74AUP1G02SCES568H –JUNE 2004–REVISED OCTOBER 2014 www.ti.com
10 Application and Implementation
10.1 Application InformationThe AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portableapplications. This family ensures a very low static and dynamic power consumption across the entire VCC rangeof 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. Ithas a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive producesslower edges and prevents overshoot and undershoot on the outputs.
10.2 Typical Application
Figure 5. Typical Application Schematic
10.2.1 Design RequirementsThis device uses CMOS technology and has balanced output drive. Care should be taken to avoid buscontention because it can drive currents that would exceed maximum limits.
10.2.2 Detailed Design Procedure1. Recommended Input conditions
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions– Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid VCC
2. Recommend output conditions– Load currents should not exceed 20 mA on the output and 50 mA total for the part– Outputs should not be pulled above VCC
12 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated
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−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45Time − ns
Vo
ltag
e−
V
† AUP1G08 data at CL = 15 pF
OutputInput
Switching Characteristics
at 25 MHz†
SN74AUP1G02www.ti.com SCES568H –JUNE 2004–REVISED OCTOBER 2014
Typical Application (continued)10.2.3 Application Curves
Figure 7. Excellent Signal IntegrityFigure 6. AUP – The Lowest-Power Family
The AUP family of single gate logic makes excellent translators for the new lower voltage microprocessors thattypically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories thatare still powered by 3.3 V to the new uC power levels.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
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Vcc
Unused Input
Input
Output
Input
Unused Input Output
SN74AUP1G02SCES568H –JUNE 2004–REVISED OCTOBER 2014 www.ti.com
11 Power Supply RecommendationsThe power supply can be any voltage between the Min and Max supply voltage rating located in theRecommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a singlesupply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended foreach power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μFand a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin aspossible for best results.
12 Layout
12.1 Layout GuidelinesIn many cases, functions or parts of functions of digital logic devices are unused, for example, when only twoinputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not beleft unconnected because the undefined voltages at the outside connections result in undefined operationalstates. Figure 8 specifies the rules that must be observed under all circumstances. All unused inputs of digitallogic devices must be connected to a high or low bias to prevent them from floating. The logic level that shouldbe applied to any particular unused input depends on the function of the device. Generally they will be tied toGND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of thepart when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Figure 8. Layout Diagram
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SN74AUP1G02www.ti.com SCES568H –JUNE 2004–REVISED OCTOBER 2014
13 Device and Documentation Support
13.1 TrademarksAll trademarks are the property of their respective owners.
13.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
13.3 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
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PACKAGE OUTLINE
C
4X 0.270.17
3X 0.320.23
0.4 MAX
0.050.00
2X0.48
0.270.17
0.25 0.1
B 0.850.75
A
0.850.75
(0.1)
(0.06)
X2SON - 0.4 mm max heightDPW0005A-C01PLASTIC SMALL OUTLINE - NO LEAD
4221849/A 12/2014
PIN 1 INDEX AREA
SEATING PLANE
NOTE 4
1
2
3
4
0.1 C A B0.05 C
THERMAL PAD
5
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.4. The size and shape of this feature may vary.
SN74LVC1GXX and SN74AUP1GXXSN74LVC1GXX and SN74AUP1GXX
NOTE 4
SCALE 12.000
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EXAMPLE BOARD LAYOUT
0.05 MINALL AROUNDTYP
(0.48)
(0.78)
4X (0.42)
4X (0.22)
( 0.25)
4X (0.26)
4X (0.06)
( )VIA
0.1
(R ) TYP0.05
X2SON - 0.4 mm max heightDPW0005A-C01PLASTIC SMALL OUTLINE - NO LEAD
4221849/A 12/2014
SYMM
1
2
3
4
SYMM
LAND PATTERN EXAMPLESOLDER MASK DEFINED
SCALE:60X
SOLDER MASKOPENING, TYP
METAL UNDERSOLDER MASKTYP
5
NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
SN74LVC1GXX and SN74AUP1GXX
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EXAMPLE STENCIL DESIGN
(0.48)
(0.78)
4X (0.42)
4X (0.22)
4X (0.26)
4X (0.06)
( 0.24)
(0.21)TYP
(R ) TYP0.05
X2SON - 0.4 mm max heightDPW0005A-C01PLASTIC SMALL OUTLINE - NO LEAD
4221849/A 12/2014
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
SN74LVC1GXX and SN74AUP1GXX
SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREASCALE:100X
SYMM
1
2
3
4
SYMM
EDGESOLDER MASK
5
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Jul-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
SN74AUP1G02DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 H02R
SN74AUP1G02DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 H02R
SN74AUP1G02DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HB5 ~ HBF ~ HBK ~ HBR)
SN74AUP1G02DCKT ACTIVE SC70 DCK 5 250 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HB5 ~ HBR)
SN74AUP1G02DPWR ACTIVE X2SON DPW 4 3000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 B4
SN74AUP1G02DRLR ACTIVE SOT DRL 5 4000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HB7 ~ HBR)
SN74AUP1G02DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 (HB7 ~ HBR)
SN74AUP1G02DRY2 PREVIEW SON DRY 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB
SN74AUP1G02DRYR ACTIVE SON DRY 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB
SN74AUP1G02DSF2 PREVIEW SON DSF 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB
SN74AUP1G02DSFR ACTIVE SON DSF 6 5000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB
SN74AUP1G02YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS& no Sb/Br)
SNAGCU Level-1-260C-UNLIM (HB2 ~ HB7 ~ HBN)
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Jul-2014
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
SN74AUP1G02DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUP1G02DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUP1G02DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AUP1G02DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74AUP1G02DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AUP1G02DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74AUP1G02DPWR X2SON DPW 4 3000 180.0 8.4 0.91 0.91 0.5 4.0 8.0 Q3
SN74AUP1G02DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74AUP1G02DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74AUP1G02DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74AUP1G02DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74AUP1G02YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2014
Pack Materials-Page 1
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*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP1G02DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AUP1G02DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74AUP1G02DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AUP1G02DCKR SC70 DCK 5 3000 205.0 200.0 33.0
SN74AUP1G02DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74AUP1G02DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74AUP1G02DPWR X2SON DPW 4 3000 205.0 200.0 33.0
SN74AUP1G02DRLR SOT DRL 5 4000 184.0 184.0 19.0
SN74AUP1G02DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74AUP1G02DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74AUP1G02DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74AUP1G02YFPR DSBGA YFP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2014
Pack Materials-Page 2
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C
6X 0.220.12
6X 0.450.35
2X0.7
4X0.35
0.4 MAX
0.050.00
A 1.050.95 B
1.050.95
(0.11) TYP
(0.1)PIN 1 ID
4208186/F 10/2014
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
34
6
0.07 C A B0.05 C
SYMM
SYMM
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.3. Reference JEDEC registration MO-287, variation X2AAF.
MECHANICAL DATA
DSF (S-PX2SON-N6) PLASTIC SMALL OUTLINE NO-LEAD
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D: Max =
E: Max =
1.19 mm, Min =
0.79 mm, Min =
1.13 mm
0.73 mm
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IMPORTANT NOTICE
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