smd098 computation structuressmd098 computation structures lecture 1 21 hierarchical design...

SMD098 Computation Structures Lecture 1 1

SMD098 Computation StructuresSMD098 Computation Structures

Responsible for the course:Jonas Thor

Room: A2304Email: [email protected]

Examiner:My boss - Per Lindgren


Lecture outlineLecture outline

• What to do today!• Course introduction

– Goal and contents

– Examination

• ASIC (and FPGA) design flow

• Design alternatives


Today…Today…

• Register for the course - sign list• From the list I will generate an email alias, [email protected],

where I will post various information. Note that You are encouraged to use the mail alias if you find bugs in labs, have questions etc.

• Write down your user name at sm! If you don’t you will not get any extra qouta!


Course goalsCourse goals

• Give the student an understanding of functionally complex digital systems

• Give the student a fundamental competence in methods for designand implementation of digital systems

• Familiarize the student with synchronous digital design


Course contentsCourse contents

• A few (10) lectures focusing on:

– Design alternatives

– Register Transfer Level (RTL) design with VHDL– Synchronous design

– Design methodologies

– FPGA implementations

– CMOS technology


Course examinationCourse examination

• 4 “point” course, labs 2 points and exam is worth 2 points

• Grade determined by results on exam

• Some material covered in lectures is not available in the text book, but will be in the final exam.


Teaching...Teaching...

• There are few lectures and you are supposed to pick up most of the material while working with the labs

• When you have questions you are encouraged to contact me personally or by email. You may also use the mail alias

• Investigate alternate data sources other than me and the textbook

• I plan to put as much material as possible on the course web pages


Required text bookRequired text book

• Digital System Design with VHDL, Mark Zwolinsky, 2000

• Start reading chapters 1- 3• Your old book from “Digitalteknik”

might be useful as well• Most of the material for todays

lecture can be found in the paper “ASIC Design”, S. Gupta and R. K. Gupta. Make sure you get a copy of the paper!


LabsLabs

• Software available on Solaris machines. 30 licenses of NC VHDL, 15 licenses of Synplify and unlimited (?) licenses available for Xilinx. Let me know if you experience any problems with the licenses

• Hardware available in A1502. Detail about this next lecture


Hardware Hardware -- XSV100 boardsXSV100 boards


Hardware Hardware -- XSV100 boardsXSV100 boards


LabsLabs

• Lab 1 Tutorial November 6

• Lab 2 ALU design November 13

• Lab 3.1 PS/2 keyboard interfacing November 21

• Lab 3.2 RS232 serial port interfacing November 27

• Lab 3.3 Ethernet PHY interfacing December 11

In all labs, except lab 2, the XSV board will be usedYou will have one week to complete each lab, except lab 3.3 where you will have two weeks

Deadline


Key competence areas in design of embedded systemsKey competence areas in design of embedded systems

• Digital design – what this course is all about • Analog design

• Mixed mode design

• Software engineering and hardware/software co-design

• In this course, when we talk about ASIC design we most often mean digital ASIC design

• Common for students to think that digital designer does not have to know anything about analog design! Not true! Digital circuits are analog at low level. Every digital designer should now the basics of circuit theory and analog design. Take a few SME courses!


What’s an ASIC?What’s an ASIC?

• Application Specific Integrated Circuit– “Specialized circuits block or entire chip which are designed

specifically for a given application”

– So, it’s not a CPU but the ASIC may contain a CPU

What’s a SOC?What’s a SOC?

• System-on-a-chip

– Systems that previously needed to be implemented on PCBs (Printed Circuit Boards) may be implemented on a single chip.


ASIC design flowASIC design flow Behavior (system) Level

Function the system must implement. Delay, area, power etc constraints

Register Transfer Level

Components and their interconnect

Gate (logic) Level

Low level components and nets

Mask (geometric) Level

Physical layout of IC

System partitioningPipelining and scheduling

Resource allocationResource binding

State machine optimizationMulti-level logic optimization

Retiming and resynthesisTechnology mapping

Post-layout transistor sizing

FloorplanningClock tree design

Cell placementDetailed routing

Power network design

Behavioral synthesis

Logic synthesis

Physical synthesis


Definition of Register Transfer LevelDefinition of Register Transfer Level

• Inputs and outputs are defined• Architecture (and of course function) of circuit is defined • Placing of memory elements (flip-flops etc) are known

Example of RTL model in schematic form


Abstraction levels Abstraction levels –– YY--chartchart


Physical abstraction levelsPhysical abstraction levels

Package

Die

Pad

Wire bond

I/O pins

Inverter layoutChip (die)

Package

Printed Circuit Board


Design example Design example –– a hardware implementation of the GCD algorithma hardware implementation of the GCD algorithm

• Find the Greatest Common Divisor for two unsigned chars (1 byte)• Algorithm flow chart and corresponding behavioral VHDL code

processvariable A, B, Swap : integer range 0 to 255;

beginA := A_in;B := B_in;if (A /= 0 and B /= 0) then

while (B /= 0) loopwhile (A >= B) loop

A := A-B;end loop;Swap := A; A := B; B := Swap;

end loop;else

A := 0;end if;Y <= A;

end process;


GCD algorithm RTL descriptionGCD algorithm RTL description• With RTL synthesis tools it is not possible to use the behavioral VHDL code:

– use a behavioral synthesis tool or– write RTL VHDL code. This is what we do in this course and this is what is

most common in the industry. A RTL VHDL description can be written that infers the sequential structure below.

The tools will not do the job for you! Good tools are helpful, but you are the designer!


Hierarchical design representationHierarchical design representation

Top-down design methodologyvs

Bottom-up design methodology


ASIC design flowASIC design flow

• The requirements is the basis for the specification

• A behavioral model may be written in C or some other high level language.

• A RTL model for the design is written in the design entry phase… flow continues on following slides


Design entryDesign entry

• Traditionally performed with schematic entry tools, but with increased complexity schematic entry is not feasible

• Hardware Description Languages (HDL) allows designer to model hardware using abstract programming. Two HDLs are dominant: VHDL and Verilog (both are standardized by IEEE)

• Mixed HDL and schematic entry tools

• Module generators. Generate multiplexers, memory, data path elements for the specific target technology

• IP cores, Intellectual Property. Synthesizable VHDL/Verilog model or netlist of complex cores. For instance PCI, processor core, etc


What is VHDL?What is VHDL?

• VHSIC (Very High Speed Integrated Circuits) Hardware Description Language

• Created by USA Department of Defense. Adopted as an IEEE standard in 1987. Latest standard is IEEE 1076 ‘93

• Intended for documenting and and modeling digital systems at different abstraction levels ranging from system level down to gate level

• Only a subset of the language is synthesizable, and that subset may differ from tool to tool. We will write RTL VHDL

• More about VHDL next lecture and in the first lab


RTL functional simulationRTL functional simulation

• At this stage you have a HDL RTL model with no timing information. Only the function of the RTL model is verified

• The Unit Under Test (UUT) is instantiated in a HDL test bench and verified in a simulator

• The reference vector may come from a high level model

WAVEFORM GENERATION

COMPARE RESULTS

UNIT UNDER TEST

REFERENCE VECTORS

STIMULUS VECTORS OUTPUT VECTORS

TEST VECTOR

FILERESULTS

FILE

Optional Optional

HDL TESTBENCH


SynthesisSynthesis

• Language synthesis. HDL code is compiled to known structural elements

• Optimization. Different algorithms are used to make your design as small and/or as fast as possible, depending on what you are optimizing for

• Technology mapping. The optimized structure is mapped to the target technology. The available components in the target technology isdefined in a technology library

• The output is a netlist readable for the implementation tools


FloorplanningFloorplanning, placement and route, placement and route

• Floorplanning. Arranges some or all of the blocks or cells in the design. Floorplanning is done manually by the aid of tools

• Placement. Decides the placement of all cells• Route. Makes the connections between the cells


Circuit extractionCircuit extraction• The implemented design is converted to a HDL description

• The delays of logic and interconnects are determined

Static timing analysisStatic timing analysis• Evaluates if timing constraints have been met

• Uses graph algorithms to evaluate delay through all paths

Post layout simulationPost layout simulation• Simulates the implemented design using same test bench as in

functional simulation

• Timing information is available. But for a fully synchronous design static timing analysis should cover all timing constraints


FPGA design flow FPGA design flow -- used in labsused in labs

FPGA design is much less complex than to ASIC design –this is why we use FPGAs in the course.


Design alternativesDesign alternatives

• Microprocessors

– Digital Signal Processors (DSP), micro controllers, etc

• Dedicated standard chipsets– PCI chipset, GPS chipset, etc

• Application specific integrated circuits (ASIC)

– Full custom, cell based, gate arrays

• Programmable logic

– Simple Programmable Logic Devices (SPLD), Complex Programmable Logic Devices (CPLD), Field Programmable Gate Arrays (FPGA) will be used in the labs


Types of Types of ASICsASICs

Standard cellsHierarchical cells

Macro cellsGenerators: memory/PLA datapath components etc

Cell based

Mask programmableGate arrays

Field programmableAnti-fuse basedMemory based

Array based

Semi CustomFull Custom

Types of ASICs


Different types of ASICsDifferent types of ASICs

• Full custom ASICs– Some or all of the logic cells, circuits or layout is specific for one ASIC.

Detailed design down to transistor level– For high volume specific applications

– Mixed analog/digital devices • Standard cell based ASICs

– Libraries of standard cells. Designers connect predefines cells to create desired functionality

• Gate arrays– Internal structure is an array of gates with initially unspecified

interconnect. Designer specifies gate types and interconnection


IDT 64 bit IDT 64 bit RISControllerRISController


Simple Programmable Logic DevicesSimple Programmable Logic Devices

Programmable Array Logic (PAL)AND-OR arrays are common blocks in SPLD and CPLD architectures

Implements two level logic functions like:

CDDBCBAF ++=


Simple Programmable Logic DevicesSimple Programmable Logic Devices

Programmable AND Array32 x 64

MACRO

MC0

MACRO

MC1

MACRO

MC2

MACRO

MC3

MACRO

MC4

MACRO

MC5

MACRO

MC6

MACRO

MC7

OE/I9 I/O0 I/O1 I/O2 I/O3 I/O4

8

I1 - I8 CLK/I0

17713D-1I/O5 I/O6 I/O7

1 00 1

1 1

0 X

*SG1

SG1

SL0X

D Q

Q

1 01 10 X

1 11 00 0VCC

CLK

SL0X

OE

ToAdjacentMacrocell

FromAdjacent

Pin

1 10 X

1 0

SL1X

I/OX

Vantis PALV16V8

Macrocell


Complex Programmable Logic DevicesComplex Programmable Logic Devices

CPLDs have much higher capacity than SPLDs, but the architecture is similar.

In-System Programming ControllerJTAGController

I/OBlocks

FunctionBlock 1

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

JTAG Port

3

36

I/O/GTS

I/O/GSR

I/O/GCK

I/O

I/O

I/O

I/O

2 or 4

1

I/O

I/O

I/O

I/O

3

FunctionBlock 2

36

FunctionBlock 3

36

18

18

18

18FunctionBlock N

36

Fast

CO

NN

EC

T S

witc

h M

atrix

Macrocell 18

Macrocell 1

ProgrammableAND-Array

ProductTerm

Allocators

FromFastCONNECT

Switch Matrix

X5878

36

1

To FastCONNECTSwitch Matrix

To I/O Blocks

OUT

GlobalSet/Reset

3

18

PTOE18

18

GlobalClocks

X5879

ToFastCONNECTSwitch Matrix

AdditionalProductTerms(from othermacrocells)

GlobalSet/Reset

GlobalClocks

AdditionalProductTerms(from othermacrocells)

To I/O Blocks

OUT

1

0

36

3

PTOE

D/T QS

R

ProductTerm

Allocator

Product Term Set

Product Term Clock

Product Term Reset

Product Term OE

Xilinx XC9500 architecture

Function block

Macro cell


Field Programmable Gate Arrays Field Programmable Gate Arrays -- Xilinx XC4000Xilinx XC4000

We will use Xilinx Virtex in the labs -to be covered more later


Design alternatives Design alternatives -- when to choose what?when to choose what?CPU, ASIC or FPGACPU, ASIC or FPGA

• Highly application dependent. What kind of algorithm are you trying to implement?

– Processors execute in a sequential manner

– ASICs and FPGAs are not restricted to sequential execution• Performance. High data rates?

– ASIC have highest performance

– FPGAs can in many applications outperform a processor

• Flexibility, can the function of the device easily be altered?

– Processors are most flexible in that sense it is easy to modify and recompile a program

– FPGAs can be reconfigured

– Function in an ASIC is fixed


• Is power consumption an issue?– ASICs have the lowest power consumption. Silicon is tailored for

the specific application

• Time to market

– Processors, very short

– FPGAs, short

– ASICs, very long• Volume, cost

– ASICs have high initial costs. Best choice for high volume designs

– FPGAs are most expensive, but low initial cost

– Processors are cheap. Ideal if fast enough

Design alternatives Design alternatives -- when to choose what?when to choose what?CPU, ASIC or FPGACPU, ASIC or FPGA


Hybrid chipsHybrid chips

Atmel AVR

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