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SLX FPGA Quick Start Guide

Version 2020.2

Date 2020-6-30

Quick Start Guide

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Contents

Introduction ............................................................................................................................................................................................................. 1

The SLX FPGA Workflow ........................................................................................................................................................................... 1

SLX FPGA Features....................................................................................................................................................................................... 2

Getting Started ....................................................................................................................................................................................................... 4

Installing SLX .................................................................................................................................................................................................... 4

Installing Vivado .............................................................................................................................................................................................. 4

Starting SLX FPGA ........................................................................................................................................................................................ 4

Importing Project ............................................................................................................................................................................................ 5

Configuring the SLX FPGA Project ...................................................................................................................................................... 7

Application Transformation Toward Optimized IP Block .............................................................................................................. 9

Discovering / Resolving Synthesizability Issues with the Function Mapping Editor.............................................. 9

Finding and Optimizing Parallel Loops .......................................................................................................................................... 11

Hardware Optimization ............................................................................................................................................................................. 14

HLS Pragma Insertion ............................................................................................................................................................................... 15

Performing Synthesis ............................................................................................................................................................................... 16

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Introduction

This document provides a quick step-by-step guide to navigate through the different features of an SLX FPGA project with the Vivado HLS workflow for creating FPGA IP blocks.

The SLX FPGA Workflow

The recommended workflow can be summarized into the following steps:

Figure 1.1: Recommended SLX FPGA Workflow

After these steps are completed, the application source code can be exported to Vivado HLS as an SLX optimized project.

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SLX FPGA Features

The most common SLX FPGA features are accessible through the SLX menu or via the following SLX toolbar buttons.

Figure 1.2: SLX toolbar features

Command Functionality

Configure Project Primary mechanism to edit the configuration of the project.

Clean Project

Cleans all generated output files for the project. The action must be triggered after any major modification of the configuration or source code.

Run Code Compiles and runs the application binary generated using the SLX compiler to ensure that application functionality is correct prior to further analysis.

Workflow tools for Transforming Application to Optimized IP Block:

Function Mapping Editor

Opens the editor that helps defining hardware (FPGA) and software partitioning, checking HW mapped functions for synthesizability, analyzing selected functions for parallelism, triggering SLX optimization to properly exploit HLS pragmas, and performing manual design space exploration.

Find and Optimize Parallel Loops

Analyzes the program to discover potential parallelism and run optimization algorithms to determine appropriate HLS pragmas.

Generate HLS-Aware Code

Generate the HLS pragmas automatically calculated by SLX FPGA, or manually set up into the application source code. Opens a CodeGen wizard allowing the selection and fine tuning of suggested pragmas.

Synthesize

Calls the Vivado HLS compiler to run on the modified source code with inserted pragmas. A successful synthesis results in a Vivado HLS project containing a synthesis report, and HDL code for the selected HW function.

Show Synthesis Report

Displays statistics such as Performance Estimates, Area/Resource Utilization Estimates, Interface Summary and other relevant data after the project has been synthesized.

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Code Analysis and Optimization Reports:

SLX Hints

Navigates through the generated hints in the SLX Hints view. Provides a view of all generated hints, such detected parallelism, data dependencies and partitioning hints.

SW Call Graph

Displays the software call graph of the application with data on function runtimes, computational costs and relationships between function callers and callees.

Code Analysis Graph

Displays a graphical representation that combines function execution times with the variable accesses in the entire program, which can be filtered over multiple criteria.

Memory Analysis

Displays detailed statistics for all the variables in the application. This includes read and write accesses with reference to source code location of each access. It includes all global, local and heap variables.

Table 1.1: SLX FPGA features

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Getting Started

Installing SLX

The following steps are described in detail in the Installation Guide:

• Download the installation package and SLX license from the Silexica Licensing portal

• Install SLX FPGA and set up the license on your machine

Installing Vivado

Install Xilinx Vivado HLS (2019.1 or 2019.2) on your computer with the valid license.

Starting SLX FPGA

SLX FPGA can be started by clicking the SLX desktop icon (Windows, Linux). Alternatively, to run SLX FPGA from the command line on Linux, open the terminal and navigate to the root folder of the SLX FPGA installation. Next, type the following commands to start SLX FPGA: “source exports” followed by “SLX”.

When SLX starts, the following dialog screen is displayed to configure the default workspace:

Figure 2.1: SLX Launcher

Specify a desired workspace directory and click “Launch”. The following Welcome screen is displayed for creating a new project or importing an existing project.

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Figure 2.2: SLX welcome screen

Importing Project

The Import section of the Welcome screen can be used to import FPGA Projects, Xilinx SDx projects and Xilinx Vivado HLS Projects. SLX FPGA comes with a series of sample projects. The “keccak” sample project is used in this document for demonstration. Click “Import FPGA Project” from the Welcome screen.

Figure 2.3: Import Project screen

From the list of projects under silexica/examples/fpga, check the “keccak” checkbox. Click Finish to import the project into the workspace.

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Configuring the path to Xilinx Vivado tools

SLX FPGA needs to be configured with the installation path of Xilinx Vivado tools. Click “Please configure the path to Xilinx tools…” at the top of the screen to access Xilinx Setup. The Xilinx Setup screen is also accessible via Window -> Preferences by expanding SLX -> SLX FPGA Project configuration.

Figure 2.4: SLX FPGA Xilinx tools configuration link

Please make sure to select the top-level Xilinx directory of Xilinx tools instead of the Vivado directory.

Figure 2.5: SLX FPGA Xilinx tools configuration screen

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Configuring the SLX FPGA Project

Click configure to set the Configuration Details for the project.

The Basic Options section is used to select the Synthesis Flow and the FPGA Part name. This document uses the Vivado HLS flow for demonstration purposes. Choose “Vivado HLS” in the Synthesis Flow dropdown. The “FPGA Part is not valid” warning is displayed.

The FPGA Part corresponds to the supported Xilinx device that belongs to a device family and architecture. Click the “Select” button to open the FPGA Part selector.

Figure 2.6: Configuring the Basic Options

Figure 2.7: The FPGA Part selector

The filters at the top of the screen can be used to help narrow down the selection criteria. Click OK to

finalize the selection.

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Figure: 2.8: Basic Options configured for the Vivado HLS Synthesis Flow

The Xilinx Platform Archive field allows for the configuration of a FPGA Part by importing an existing

DSA (Xilinx Device Support Archive) file, or a collection of DSA files in a compressed archive. DSA files

contain the part name (FPGA Part) for the pre-implemented system it targets. The method of choosing

the FPGA Part using a Xilinx Platform Archive will not be utilized for the purposes of this demonstration.

Configure the Build Options section as follows. For the keccak project, the following values should

already be pre-populated. Ensure that the base path is set to “.”, which means all the files within the

project tree are in scope of analysis.

Figure: 2.9: Configuring the Build Options

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Application Transformation Toward Optimized IP Block

The process starts with the Function Mapping Editor (accessed by clicking the button on the main toolbar). This feature provides a centralized interface to facilitate access to the most important SLX FPGA features: selecting a Top-Level Hardware function (if one has not been selected), checking the Synthesizability of functions and running “Find and Optimize Parallel Loops” to perform automatic design space exploration for supported HLS pragmas.

Discovering / Resolving Synthesizability Issues with the Function Mapping Editor

Clicking on the Function Mapping Editor opens the Function Mapping Graph. Functions in the application are represented using rounded rectangles. The border color represents where functions are mapped: functions that have been mapped to the FPGA display a red border, while those that are not mapped have a blue border. The top-left icon represents the synthesizability status of functions.

• A function whose synthesizability is unknown because it was not yet evaluated for synthesizability will

display a question mark .

• Functions which can be mapped to the FPGA (synthesizable) display a green check mark

• Functions which need to be rewritten to be made synthesizable display a red cross .

A function mapped to the FPGA as a Top-Level Function will also show a star icon .

A Top-Level Hardware Function (e.g. the keccak function) must be selected. When creating an FPGA IP block, the top-level function and everything below it will become the FPGA IP. The Top-Level Hardware function can be specified via the Configuration Editor (Figure 3.1) or via the Function Mapping Editor (Figure 3.2).

Figure 3.1: Setting a Top-Level Hardware Function in the Configuration Editor

Figure 3.2: Setting a Top-Level Hardware Function in the Function Mapping Graph

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To check a function for synthesizability, right-click on the function and click “Check for Synthesizability”.

Figure 3.3: Checking individual functions for synthesizability

If a function is found to be synthesizable, it can be mapped to the FPGA by right-clicking and selecting “Map to FPGA” on the context menu.

Figure 3.4: Selecting a Synthesizable function to map to the FPGA

If a function is found not to be synthesizable, the following notification is displayed:

Status is “Not synthesizable”: “<name of function>” is not synthesizable, click here

to investigate.

Clicking the link opens a source panel with the function highlighted and centered, as well as synthesizability hints for the function. In general, a code rewrite must be performed for this case to ensure that the source code can be synthesized. Guidance is available by clicking on the question mark icon at the right of the hint. After the code has been modified, repeat the steps above to re-run synthesizability checks until the desired outcome has been

achieved. Figure 3.4 displays an example of a hint guidance accessed by clicking the icon to the right of the function in the SLX Hints view.

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Figure 3.5: Resolving Synthesizability Issues

Finding and Optimizing Parallel Loops

SLX FPGA uses static and dynamic analysis to extract available Data-Level Parallelism (DLP) and Pipeline-Level Parallelism (PLP) in the application. Parallelism detection and optimization can be invoked when a function is first mapped to the FPGA, by clicking on the notification displayed at the top of the Function Mapping Graph (Fig 3.2).

The analysis can also be triggered by clicking Find and Optimize parallel loops in the context menu or by right-clicking on the function mapping graph and selecting “Find and Optimize Parallel Loops”. SLX will also analyze all existing callee functions whenever “Find and Optimize Parallel Loops” is executed on the selected function.

Figure 3.6: Find and Optimize Parallel Loops within a Function

The parallel regions of a function can be viewed in the Properties tab > Parallel Loops section of the Function Mapping Editor. The parallel code blocks detected by SLX FPGA are sorted by the order in which they appear in

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the source code. If there are nested loops, the inner loops in the source code are grouped inside their outer loops in hierarchical order. Clicking on a loop populates the details of the loop to the right. The loop number and its line number are displayed at the top. Under the loop name are configurations that help take advantage of available parallelism:

• Pragmas are automatically generated for available unroll and pipelining options.

• Unrolling and Pipelining options can be enabled, disabled and configured for the loop.

• The Unroll Factor is only used for DLP loops and represents the number of times, n, that the body of a loop has been replicated to create n copies. The Initiation Interval represents the number of clock cycles between the start times of consecutive loop iterations in pipelined loops.

For more information on Loop Pipelining and Loop Unrolling, see the Xilinx Support article.

Figure 3.7: Displaying and Configuring Parallel Loops within a function

Parallel loops are also displayed within the SLX Hints view, accessed by clicking the SLX Hints tab or by right-clicking on the function in the Function Mapping Editor and clicking “Show related hints”. Hints are organized in a hierarchical manner as a table, reflecting the application structure. To see only hints related to Parallelism, type “PARTITIONING” in the Name column filter:

Figure 3.8: SLX Hints for the function keccak

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• The Name column displays icons that either correspond to a hint or structural information about the application. These icons help distinguish between the different classes of information:

o corresponds to a function in the source code

o corresponds to a loop

o groups hints related to a particular type of parallelism

o corresponds to information specific to a type of parallel partition. For instance, hints with

this icon will report available parallelism or the causes for missing parallelism

• The Status column indicates the Status of a parallel partition by a small checkbox:

o the parallelization strategy associated with the code section (i.e., a loop) is feasible, meaning that the code in the loop can be executed concurrently

o the parallelization strategy associated with the code section is not feasible, and there are blockers that hinder parallelism

Figure 3.9: SLX Hints window showing parallel sections

Double-click on a line of interest in the SLX Hints view to jump to the exact line of code and reveal pragmas inserted by SLX FPGA.

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Figure 3.10: Revealing pragmas within code

Hardware Optimization

SLX FPGA will maximize the performance of every function that needs to be implemented as an IP block, while respecting the resource constraints imposed by the available FPGA resources or set manually by the user. The suggested design is computed during a global optimization that simultaneously considers:

• Loop unrolling and pipelining

• Array partitioning and reshaping

• In-lining and selecting appropriate interfaces

The estimated hardware performance can be seen in the synthesis report presented at the completion of HLS synthesis. For advanced users, where adjustments to the SLX FPGA proposed design need to be made, SLX FPGA allows reconfiguration of the Parallel regions, Interfaces and Bandwidth to achieve the desired effect. Using the Properties view of the Function Mapping Editor, the:

• Interfaces section allows the selection of interface ports for the return values and arguments of the Top-Level hardware function. The detailed information includes the interface type to be used for the selected port as well as all its associated configurations.

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• Bandwidth section allows setting the data-rate constraint for both input and output ports of the IP block in terms of bandwidth. As an alternative, a specific bus width can also be specified on individual ports in the Interfaces section.

Figure 3.11: Interfaces and Bandwidth in the functions Properties view

HLS Pragma Insertion

From the SLX FPGA main menu, click Generate HLS-Aware Code . Pragma code generation is guided through a Code Transformation Wizard.

Figure 3.12: Code Transformation Wizard

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The code transformation wizard allows the selection of pragmas.

The first step allows the visualization of all code transformations that are suggested by SLX, and enable or disable them if desired. In this step, the generated code can be refreshed and inspected to see how the code transformations will affect the original application before applying them. When desired pragmas have been selected, click Next.

In the second step, the generated code can be manually modified (i.e., modifying the pragmas), extra HLS pragmas can be inserted, and the code can be formatted. Once satisfied with the results, click Finish.

Performing Synthesis

From the SLX menu, click Synthesize Project . At this point, SLX will invoke the Vivado HLS tool to synthesize the C/C++ code, guided by the SLX inserted pragmas, into an RTL IP block. The IP block can then be used in either the Vivado Design Suite or in the Xilinx Platform Studio (XPS). This is available in the “hls” folder within the project (it is a Vivado HLS project folder which can be directly imported into Vivado HLS).

Figure 3.13: IP generated after synthesis with Place & Route Synthesis Strategy

The Performance, Utilization Estimates and Interface Summary data can be seen in the Synthesis Report (Figure 3.13). To view a raw-text version of the report, click the “Show detailed report” link at

the top of the Synthesis Report or click the icon on the main toolbar.

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Figure 3.14: Sample Synthesis Report