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www.EandTmagazine.com June 2014 Engineering & Technology

ELECTRONICS CIRCUIT INNOVATION

ALTHOUGH THE FROTHY enthusiasm cosseting the idea of the Internet of Things – webs of tiny sensors communicating wirelessly – for example, may not last the year before temporarily disappearing from view, the technologies needed to make sensors live for years on a lithium coin cell, or even harvest energy from the environment, will continue. One such technology would reverse the trend of the last 50 years, and opt for slow computing – very slow computing, possibly.

The power used by the CMOS (complementary metal-oxide semiconductor) logic that sits in practically all microprocessors is controlled by a formula

that links the square of the voltage to the frequency at which the transistors switch. Because of the quadratic relationship, lowering the voltage has a dramatic effect on energy consumption.

Intel is one of a group of companies investigating the potential of near-threshold and sub-threshold logic, where the supply voltage to each transistor is reduced to the point where it barely switches on. The technology takes advantage of the way in which small amounts of current pass through the transistor as it moves from the off state to the on.

This is enough to charge the capacitances in downstream logic that help move from one

state to another. However, with less current passing, the longer the entire process takes. A chip that happily operates at gigahertz frequencies at 1V has trouble switching at more than one megahertz when that voltage falls towards the threshold point, at around 0.25V for the latest process technologies; and yet, this is something that chip designers are willing to work with.

“We need to be able to operate at a lower voltage when we don’t have a lot of activity and scale that [up] when we do,” explains Wen-Hann Wang, vice president and managing director of chip maker Intel Labs.

At the International Solid State Circuits Conference (ISSCC) in February 2014 Intel >

SLOWIS THE NEW FAST(AND OTHER STORIES FROM

THE CUTTING EDGE OF CHIP TECH…)

Staying ahead in the chip market is a challenge for

designers and fabricators alike: for the former the need is to go slow, decreasing switch rates for lower power consumption; for the latter, finding ways to

repurpose production processes more competitively.

By Chris Edwards

Engineering & Technology June 2014 www.EandTmagazine.com

60 ELECTRONICS CIRCUIT INNOVATION

< demonstrated a graphics processor that operates close to the threshold region to deliver an efficiency measured in gigaflops per watt 2.7 times higher than that achieved at a ‘normal’ voltage, which is about 0.4V higher.

A problem with this type of design – and a key reason why it has not made it into mainstream production outside of some sensor processors (such as those developed by Imperial College, London spin-out Toumaz Group) – is that small variations in voltage often caused by the switching of surrounding logic have a dramatic effect on speed, which makes it difficult to design circuits using traditional techniques.

Aligning voltage and clock speedVivek De, director of circuit technology research at Intel Labs, points out that this effect compels designers to use higher voltages than are desirable to operate at a guaranteed speed. Intel uses measurements taken during testing to work out the safest minimum voltage for a given clock speed.

In work with the University of Michigan, ARM has investigated other approaches. The Razor technique uses error-detection to work out if a sudden voltage drop has caused logic to switch too slowly and, after pushing the voltage up, allows the operation to start again.

For its graphics processor Intel did not push the voltage all the way down to the threshold voltage of its 22nm finFET process (‘finFET’ describes a nonplanar, double-gate transistor built onto a silicon-on-insulator (SOI) substrate, based on the earlier DELTA (single-gate) transistor design). There is a further drawback of such low-voltage logic.

Even below the threshold voltage, transistors do not quite switch off completely; they ‘leak’ current; and as the supply voltage falls, the leakage gets worse.

Regular logic can run quickly and switch-off until it is needed again, which cuts leakage dramatically; but because of the time

they take to process data at their low clock speeds, sub-threshold logic circuits do not have the same option – so leakage spirals-up. The result is that energy consumption has a minimum around the transistor’s native threshold voltage before it overtakes the energy lost in actual computation.

The leakage issue is why some of the companies involved in this area continue to avoid near-threshold logic. Christopher Neil, senior vice-president of the industrial and medical solutions group at Maxim Integrated – which is working on ARM processors that can operate from the low levels of power supplied by environmental harvesting – says that the plan is to continue with standard CMOS.

“They are saying that they think it will be achieved through the use of asynchronous logic,” Neil reports, “and to really shut down when the blocks are not being used.”

The shutdown option is one that near-threshold logic can still use. For its graphics processor, Intel used registers – logic gates that hold data values that retain their contents when the supply voltage is removed. Although the charge leaks out, the gates reactivate before they lose their contents entirely.

ARM is also working on near-threshold logic that can shut-off not only between operations, but mid-way through each one to reduce the impact of leakage when operating at very slow clock speeds. Mike Muller, CTO of ARM, reckons that there are real implementation choices to be made about how slow processes are handled: “The way you design at 20kHz is entirely different to 2GHz or even 2MHz. We’ve developed a whole lot of schemes,” he says.

When, almost three years ago, Intel said that it was time to abandon a transistor structure that had been in use for decades, and go with the finFET, much of the rest of the IC industry seemed to agree. However, questions over how enthusiastic other companies are about making the move to the

new 3D structure that is more difficult to make, and may not be entirely appropriate for the mobile devices that Intel has had a hard time breaking-in to, remain.

The top supplier of mobile chips, Qualcomm seems happy to stay on the 20nm process from its main supplier TSMC rather than move down to the equivalent finFET-based process (which TSMC calls its 16nm offering), even though it has the same interconnect structure as the 20nm. The industry’s hesitance may provide an opening for an alternative to the finFET to come forward.

Working with research institute CEA-Leti in Grenoble, Franco-Italian company STMicroelectronics has pursued the option of changing the substrate of the wafer rather than the transistor itself, with a process known as fully-depleted silicon on insulator (FD-SOI). This slides a layer of insulating oxide underneath the silicon which is used as the substrate for building transistors.

‘Partially-depleted SOI’The oxide stops electric fields penetrating down into the chip, and helps focus them on the narrow channel through which electrons pass when a transistor is switched on. This makes it easier for the gate of a transistor to control when electrons pass.

Deep submicron transistors built on bulk silicon have less control so they have become very leaky. The finFET approaches the problem from a different angle by, in effect, wrapping the gate electrode around three walls of a very narrow, elevated channel.

Chip vendor AMD and technology giant IBM have used SOI for almost a decade in their microprocessors, but have done so in a form that involves more design effort.

The so-called ‘partially-depleted SOI’ has a comparatively thick silicon channel, between the transistor gate and the oxide layer, which allows charge to linger in a way that it does not in conventional devices.

This complicates design, and has made >

‘FD-SOI is great, maybe, on paper, but it has no commitment. If you as

the developer of the technology won’t buy it, then why

should I?’Malcolm Penn, Future Horizons

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www.EandTmagazine.com June 2014 Engineering & Technology

Question: what can you do with an old chip fab facility? This is the problem that faced the reborn UK-based Plessey Semiconductors after it bought back the Roborough, Plymouth, fab it had previously owned – and it’s almost always faced an uncertain future.

Soon after it opened as one of the most advanced fabs in Europe (if not the world), Plessey’s Roborough site was under threat. Despite a near ideal geological location of which its builders boasted at the ribbon-cutting ceremony – far away from the threat of earthquakes unlike competitors along the west coast of the US or the Pacific Rim – GEC and Siemens were moving in to break-up Plessey. Plessey’s used the Roborough facility as an example of what would be lost if GEC and Siemens were allowed to take the company over.

Although GEC kept the fab running as part of GEC-Plessey Semiconductors, technology at the plant was eventually outpaced by overseas competitors and manufacturing focused on what would soon become trailing-edge processes. The plant opened at a time when a significant fab technology shift was beginning – the move from 150mm to 200mm.

To try to keep the fab reasonably up to date, GEC invested tens of millions of pounds in the mid-1990s to upgrade some of its equipment to handle 200mm wafers, helping to at least keep it cost-competitive with rivals; but that is where the Roborough plant stuck for the next 20 years as it was passed to a series of companies; in Q1/2014 the position of a 200mm fab is more precarious than ever.

Wafer size is one of the less obvious contributors to Moore’s Law, under which the cost per transistor is meant to halve

every two years. Because chip production is a sequence of chemically assisted batch-processing steps, the more chips you can process at once that are likely to work at the end of the sequence the cheaper each of them will be. In the decade after Intel founder Gordon Moore first identified the trend and gave his name to it, wafer sizes increased rapidly, having started out in the 1960s at less than an inch across.

Progress slowed after the 1970s. Moore quipped just over a decade ago, in his keynote at the International Solid State Circuits Conference in San Francisco, that his predictions were not always accurate. He showed a photomontage of how big wafers should have been in 2003 if the trend had been followed – close to 6ft across rather than the vinyl LP-sized disc of 2014. This has provided some breathing space for the fabs built in the late-1980s and 1990s that could handle 200mm wafers; but now that is changing.

The shift to 300mm was delayed several times and, although fabs running on the larger wafers account for just over a quarter of all IC production at present, there is now a move underway at a second generation of suppliers to take products made today on older processes on 200mm equipment to 300mm lines. Their aim is to take advantage of a potential halving in production costs that would allow them to undercut rivals using the older lines.

The plan at Plessey is to expand out from traditional markets under threat from this 300mm transition and, in effect, do the same to another market. Plessey has settled on LED lighting as chips are now made on much smaller wafers – largely because the materials they use are often more fragile than silicon as well as being more

expensive. Breakthroughs in the ability to put high-brightness LED materials, such as gallium nitride, onto a silicon substrate have made it possible to consider manufacture on what for that market are very large, potentially very cheap wafers.

Michael LeGoff, CEO of Plessey, explained at the recent International Electronics Forum organised by Future Horizons: “Like anything in semiconductors, you have to go big – or you go home. The plan is to run a fully-depreciated fab on technology that’s been developed at a UK university, and get that into the marketplace, so that when you put those very low-cost LEDs into a bulb it costs you a fiver rather than the £30 that it’s priced at today.”

In moving to 200mm LED production, Plessey is not going to be alone. In Q4/2013, using technology from Brightlux, Toshiba launched its own range of GaN-on-silicon. Matthias Diephaus, its director of marketing for opto semiconductors, says: “We are the first company to start mass-production of GaN LEDs on 200mm silicon wafers. We can get more chips from the wafer and also take advantage of the lower costs of the wafer compared to traditional sapphire substrates.”

LeGoff says he is confident that there is enough pent-up global demand for LEDs to make full use of the fab. He expects “half of the lighting on the planet to convert to LED”. The transition to solid-state lighting has yet to happen: “The demand is so large, our feeling is that there is sufficient demand for all players at this stage... Because we are running in an IC fab it provides the opportunity to run very large LEDs or very, very small. That gives us all kinds of different markets to participate in.”

CASE STUDY: PLESSEY SEMICONDUCTORS

FAB FUTURES CAN EMBRACE DEVELOPMENTS IN CONCOMITANT TECHNOLOGIES

Plessey Semiconductors’ Roborough facility is getting a new lease on life

Engineering & Technology June 2014 www.EandTmagazine.com

62 ELECTRONICS CIRCUIT INNOVATION

< that form of SOI something of a speciality process. FD-SOI’s much thinner silicon channel eliminates the lingering-charge problem. However, it is harder to make and suffers from another problem: low mobility. You cannot push as many electrons through the channel as you can with conventional bulk-silicon transistors.

Acceptable ‘bias’Those behind the process argue that the mobility issue is something of a red herring for manufacturers of mobile devices as they run at slower speeds, and do not need the high current.

The mobility issue is bigger for higher-power processors such as Intel’s PC products. The thin channel of the FD-SOI means that it does not leak much; and the insulated substrate has one other advantage – you can drive a charge into the silicon underneath it to ‘bias’ the gate. A bias in one direction speeds up the transistor. In the other direction, it slashes leakage even further.

These techniques make it possible to cut the supply voltage, which reduces energy further. According to David Jacquet, principal engineer at STMicroelectronics (ST), on one 32bit processor test chip, the design team cut the voltage by 40 per cent and got the same performance as one made on bulk silicon. Jean-René Lequepeys, vice president of the silicon components division at CEA-Leti, claims that FD-SOI “will scale down to 10nm, and the technology for 14nm is available today... Design kit for 10nm will be available in June 2014”.

Lequepeys says speed enhancements planned for finFETs could be applied to FD-SOI, “and we can also introduce what we call monolithic 3D, where we put transistors on top of transistors”.

The problem for FD-SOI is an apparent

There’s more online...Power pushes UK’s electronics sector forwardhttp://bit.ly/eandt-uk-electronics-sectorScotland’s silicon survivorshttp://bit.ly/eandt-raytheon-analysisIntel and Samsung hit the 22nm acceleratorhttp://bit.ly/eandt-22nm-gamble

lack of commitment. ST had originally selected FD-SOI as the preferred process for the NovaThor mobile phone processor. But, with the unit haemorrhaging money for several years, ST cut its ties to the operation and the future of NovaThor remains doubtful, although the company said last year it would continue product engineering work in the hope of finding a new customer.

This does, however, mean that the developer of the technology has little internal use for it and lacks the capacity to make it in volume. Instead, GlobalFoundries has taken a licence to make it for third parties and ST said at its annual results meeting at the beginning of the year that another major foundry will license the technology.

Troublesome processes?Malcolm Penn, CEO of market analyst Future Horizons, reckons that FD-SOI has “a marketing problem... It does not have a lot of credibility... How credible is it when you aren’t going to use it yourself ? It is great, maybe, on paper, but it has no commitment. If you as the developer of the technology won’t buy it then why should I?”.

Yet finFET processes from the foundries may prove more troublesome than expected. Design teams are already aware of the changes they need to make, but early work on circuits has shown that the energy consumed by switching – caused by the high capacitance of the narrow fin structures – is worse than expected.

Manufacturers are looking at ways to alter their logic to make it switch less often. Some may give FD-SOI another look as it seems to be much more in line with the requirements of mobile devices, as long as they can be sure that development won’t suddenly be terminated – and they are left at the wrong end of a technological blind alley. *

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